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from b2698c21f2c Daily bump. new 299a53d7979 Enable gcc support for UINTR new 83927c63897 Enable Intel HRESET Instruction new 72eb8335848 RISC-V: Add support for -mcpu option.
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Summary of changes: gcc/common/config/i386/cpuinfo.h | 5 ++ gcc/common/config/i386/i386-common.c | 30 ++++++++ gcc/common/config/i386/i386-cpuinfo.h | 2 + gcc/common/config/i386/i386-isas.h | 2 + gcc/common/config/riscv/riscv-common.c | 91 ++++++++++++++++++++-- gcc/config.gcc | 6 +- gcc/config/i386/cpuid.h | 2 + gcc/config/i386/{clwbintrin.h => hresetintrin.h} | 31 ++++---- gcc/config/i386/i386-builtin-types.def | 1 + gcc/config/i386/i386-builtin.def | 8 ++ gcc/config/i386/i386-builtins.c | 5 ++ gcc/config/i386/i386-builtins.h | 1 + gcc/config/i386/i386-c.c | 5 +- gcc/config/i386/i386-expand.c | 22 ++++++ gcc/config/i386/i386-options.c | 9 ++- gcc/config/i386/i386.h | 11 ++- gcc/config/i386/i386.md | 47 +++++++++++- gcc/config/i386/i386.opt | 8 ++ gcc/config/i386/{fxsrintrin.h => uintrintrin.h} | 60 +++++++++------ gcc/config/i386/x86gprintrin.h | 4 + gcc/config/riscv/riscv-cores.def | 49 ++++++++++++ gcc/config/riscv/riscv-protos.h | 14 ++++ gcc/config/riscv/riscv.c | 97 +++++++++++++----------- gcc/config/riscv/riscv.h | 25 ++++-- gcc/config/riscv/riscv.opt | 4 + gcc/config/riscv/t-riscv | 2 + gcc/doc/extend.texi | 10 +++ gcc/doc/invoke.texi | 35 +++++++-- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 4 + gcc/testsuite/gcc.target/i386/hreset-1.c | 11 +++ gcc/testsuite/gcc.target/i386/uintr-1.c | 21 +++++ gcc/testsuite/gcc.target/i386/uintr-2.c | 17 +++++ gcc/testsuite/gcc.target/i386/uintr-3.c | 9 +++ gcc/testsuite/gcc.target/i386/uintr-4.c | 9 +++ gcc/testsuite/gcc.target/i386/uintr-5.c | 10 +++ gcc/testsuite/gcc.target/i386/x86gprintrin-1.c | 3 +- gcc/testsuite/gcc.target/i386/x86gprintrin-2.c | 3 +- gcc/testsuite/gcc.target/i386/x86gprintrin-3.c | 3 +- gcc/testsuite/gcc.target/i386/x86gprintrin-4.c | 6 +- gcc/testsuite/gcc.target/i386/x86gprintrin-5.c | 6 +- gcc/testsuite/gcc.target/riscv/mcpu-1.c | 18 +++++ gcc/testsuite/gcc.target/riscv/mcpu-2.c | 18 +++++ gcc/testsuite/gcc.target/riscv/mcpu-3.c | 18 +++++ gcc/testsuite/gcc.target/riscv/mcpu-4.c | 18 +++++ gcc/testsuite/gcc.target/riscv/mcpu-5.c | 19 +++++ gcc/testsuite/gcc.target/riscv/mcpu-6.c | 10 +++ gcc/testsuite/gcc.target/riscv/mcpu-7.c | 10 +++ 47 files changed, 684 insertions(+), 115 deletions(-) copy gcc/config/i386/{clwbintrin.h => hresetintrin.h} (67%) copy gcc/config/i386/{fxsrintrin.h => uintrintrin.h} (58%) create mode 100644 gcc/config/riscv/riscv-cores.def create mode 100644 gcc/testsuite/gcc.target/i386/hreset-1.c create mode 100644 gcc/testsuite/gcc.target/i386/uintr-1.c create mode 100644 gcc/testsuite/gcc.target/i386/uintr-2.c create mode 100644 gcc/testsuite/gcc.target/i386/uintr-3.c create mode 100644 gcc/testsuite/gcc.target/i386/uintr-4.c create mode 100644 gcc/testsuite/gcc.target/i386/uintr-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-7.c