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from dafd63d7c5c RISC-V: Implement .SAT_TRUNC for vector unsigned int new 5be97039aa6 rs6000: load high and low part of 128bit vector independent [...]
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Summary of changes: gcc/config/rs6000/vsx.md | 17 +++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr110040-1.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr110040-2.c | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr110040-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr110040-2.c