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from b5e7bf5f78a [RISCV] Support llvm-objdump -M no-aliases and -M numeric new f37f4831288 AMDGPU/GlobalISel: Legalize constant 32-bit loads new 6c1da931e78 AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
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Summary of changes: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 5 ++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 19 ++++- lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 3 + lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 ++- .../GlobalISel/legalize-load-constant-32bit.mir | 64 ++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-sextload.mir | 98 ++++++++++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-zextload.mir | 97 +++++++++++++++++++++ 7 files changed, 293 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir