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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/ci/llvm-project.
from 3400d0293a14 [CMake] Update cache file for Win to ARM Linux cross toolc [...] adds 33504b3bbe10 [PowerPC] Allow absolute expressions in relocations adds 09fba23d41f7 [compiler-rt] Implement __clear_cache on FreeBSD/powerpc adds e8f03f2057ee Force GHashCell to be 8-byte-aligned. adds 0f56ce0fb207 [DebugInfo][InstrRef] Avoid a crash from mixed variable lo [...] adds 571c7d8f6dae Reland "[llvm][AArch64] Insert "bti j" after call to setjmp" adds 0fbe860711be [Clang][Fortify] drop inline decls when redeclared adds b83c4a2dc0fb [x86] Fix infinite loop inside DAG combiner with lzcnt feature. adds 9a3e81e1f91f [InstCombine] canonicalize select with signbit test adds e7a9fd4f57d6 [LV] Add test case for PR54427. adds 0d2efbb8b82c [LV] Always use add to add scalar iv and (startidx + step) [...] adds ebf29ba9f0a3 [LV] Remove stray debug dump added in 0d2efbb8b82c. adds 324127d8da95 [libcxx] Add some missing xlocale wrapper functions for OpenBSD adds dc30b0d3320d [ELF] --emit-relocs: fix missing STT_SECTION when the firs [...] adds 50c6ba751fa2 [RISCV] Only try LUI+SH*ADD+ADDI for int materialization i [...] adds 58d5fbe2c20b [llvm-mt] Add support /notify_update adds 21ce6cfd1d93 [RISCV] Add tests showing incorrect BUILD_VECTOR lowering adds 9efcce92b55b [RISCV] Fix lowering of BUILD_VECTORs as VID sequences adds e19be4195b87 [RISCV] Add another test showing incorrect BUILD_VECTOR lowering adds 1f4c7b2a9120 [RISCV] Don't emit fractional VIDs with negative steps adds a36801750327 [asan] Always skip first object from dl_iterate_phdr adds 0e27d08cdeb3 [RISCV] Fix crash for section alignment with .option norvc adds 2e7e14177186 workflows: Add a test to ensure that the LLVM version is correct adds 1f9140064dfb Bump version to 14.0.3
No new revisions were added by this update.
Summary of changes: .github/workflows/version-check.py | 32 ++++++ .github/workflows/version-check.yml | 26 +++++ clang/docs/ClangCommandLineReference.rst | 2 +- clang/docs/ReleaseNotes.rst | 6 +- clang/include/clang/Driver/Options.td | 2 +- clang/lib/CodeGen/CGExpr.cpp | 14 ++- clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 3 + .../CodeGen/fread-inline-builtin-late-redecl.c | 26 +++++ compiler-rt/lib/asan/asan_linux.cpp | 30 +++--- compiler-rt/lib/builtins/clear_cache.c | 5 +- libcxx/CMakeLists.txt | 2 +- libcxx/include/__support/openbsd/xlocale.h | 20 ++++ libcxxabi/CMakeLists.txt | 2 +- libunwind/CMakeLists.txt | 2 +- lld/COFF/DebugTypes.cpp | 6 +- lld/ELF/Writer.cpp | 41 +++++--- lld/test/ELF/emit-relocs-synthetic.s | 54 ++++++++++ llvm/CMakeLists.txt | 2 +- llvm/include/llvm/CodeGen/FastISel.h | 7 ++ llvm/include/llvm/CodeGen/SelectionDAG.h | 13 +++ llvm/include/llvm/CodeGen/SelectionDAGISel.h | 1 + llvm/lib/CodeGen/MachineFunction.cpp | 3 - llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 3 +- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 3 +- .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 10 +- llvm/lib/Target/AArch64/AArch64.td | 5 + .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 34 ++++++ llvm/lib/Target/AArch64/AArch64FastISel.cpp | 8 ++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 10 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 11 ++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 ++ .../Target/AArch64/GISel/AArch64CallLowering.cpp | 12 ++- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 63 +++++------ .../Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 2 + .../PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | 2 + .../Target/PowerPC/MCTargetDesc/PPCFixupKinds.h | 4 + .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 4 +- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp | 13 ++- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 +- .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 8 +- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 54 +++++----- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 71 +++++++------ llvm/lib/Target/X86/X86ISelLowering.cpp | 21 ++-- .../Transforms/InstCombine/InstCombineSelect.cpp | 17 +++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 15 ++- .../CodeGen/AArch64/setjmp-bti-no-enforcement.ll | 51 +++++++++ llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll | 83 +++++++++++++++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 55 ++++++++++ llvm/test/CodeGen/RISCV/imm.ll | 36 +++++++ .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 37 +++++++ llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll | 34 ++++++ llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll | 117 +++++++++++++++++++++ llvm/test/MC/PowerPC/ppc64-abs-reloc.s | 22 ++++ llvm/test/MC/RISCV/align-option-relax.s | 8 ++ llvm/test/MC/RISCV/align.s | 8 ++ llvm/test/Transforms/InstCombine/ashr-lshr.ll | 80 +++++++------- llvm/test/Transforms/InstCombine/logical-select.ll | 4 +- .../Transforms/InstCombine/truncating-saturate.ll | 4 +- .../LoopVectorize/induction-unroll-novec.ll | 46 ++++++++ llvm/test/tools/llvm-mt/notify_update.test | 16 +++ llvm/tools/llvm-mt/Opts.td | 2 +- llvm/tools/llvm-mt/llvm-mt.cpp | 25 ++++- llvm/utils/gn/secondary/llvm/version.gni | 2 +- llvm/utils/lit/lit/__init__.py | 2 +- llvm/utils/release/build_llvm_package.bat | 4 +- .../llvm/include/llvm/Config/llvm-config.h | 2 +- 70 files changed, 1094 insertions(+), 237 deletions(-) create mode 100755 .github/workflows/version-check.py create mode 100644 .github/workflows/version-check.yml create mode 100644 clang/test/CodeGen/fread-inline-builtin-late-redecl.c create mode 100644 lld/test/ELF/emit-relocs-synthetic.s create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti.ll create mode 100644 llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll create mode 100644 llvm/test/MC/PowerPC/ppc64-abs-reloc.s create mode 100644 llvm/test/MC/RISCV/align-option-relax.s create mode 100644 llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll create mode 100644 llvm/test/tools/llvm-mt/notify_update.test