[Tcwg-commits] [llvm] branch master updated (3583102 -> 11601c0)

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from 3583102 [mips][mc] Fix a crash when disassembling odd sized sections new 11601c0 [ARM] GlobalISel: Add reg bank mappings for stores

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Summary of changes: lib/Target/ARM/ARMRegisterBankInfo.cpp | 2 ++ test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 43 +++++++++++++++++++++++ 2 files changed, 45 insertions(+)