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from 81460d13a7b [LVI] Look through extractvalue of insertvalue new df591a43ba2 [X86] Fix pshuflw formation from repeated shuffle mask (PR43230) new 2d0b4264f32 [Intrinsic] Add the llvm.umul.fix.sat intrinsic new fb1c8990aef [CodeGen] Handle SMULFIXSAT with scale zero in TargetLoweri [...]
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Summary of changes: docs/LangRef.rst | 67 +++ include/llvm/CodeGen/ISDOpcodes.h | 2 +- include/llvm/CodeGen/TargetLowering.h | 5 +- include/llvm/IR/Intrinsics.td | 3 + include/llvm/Target/TargetSelectionDAG.td | 1 + lib/Analysis/VectorUtils.cpp | 2 + lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 +- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 84 +++- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 13 +- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 3 + lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 + lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 1 + lib/CodeGen/SelectionDAG/TargetLowering.cpp | 92 +++- lib/CodeGen/TargetLoweringBase.cpp | 1 + lib/IR/Verifier.cpp | 3 +- lib/Target/X86/X86ISelLowering.cpp | 4 +- test/CodeGen/PowerPC/smulfixsat.ll | 52 +++ test/CodeGen/PowerPC/umulfixsat.ll | 36 ++ test/CodeGen/X86/mulfix_combine.ll | 38 ++ test/CodeGen/X86/umul_fix_sat.ll | 542 ++++++++++++++++++++++ test/CodeGen/X86/vector-mulfix-legalize.ll | 45 ++ test/CodeGen/X86/vector-shuffle-256-v16.ll | 25 +- test/Transforms/Scalarizer/intrinsics.ll | 12 + test/Verifier/intrinsic-immarg.ll | 18 + 25 files changed, 995 insertions(+), 72 deletions(-) create mode 100644 test/CodeGen/PowerPC/smulfixsat.ll create mode 100644 test/CodeGen/PowerPC/umulfixsat.ll create mode 100644 test/CodeGen/X86/umul_fix_sat.ll