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from 35290cc AMDGPU: Remove brev intrinsic new 1b5d21e [Hexagon] Handle instruction latency for 0 or 2 cycles
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Summary of changes: lib/Target/Hexagon/HexagonInstrInfo.cpp | 32 +++++ lib/Target/Hexagon/HexagonInstrInfo.h | 4 + lib/Target/Hexagon/HexagonMachineScheduler.cpp | 22 ++++ lib/Target/Hexagon/HexagonSubtarget.cpp | 159 +++++++++++++++++++++++++ lib/Target/Hexagon/HexagonSubtarget.h | 10 ++ 5 files changed, 227 insertions(+)