[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (3c707d73f26 -> 30365472489)

24 Dec 2020


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig
in repository toolchain/ci/llvm-project.
from  3c707d73f26 [NewGVN] Remove for_each_found (NFC)
      adds  0219cf7dfaf [NewPM] Fix objc-arc-apelim pass typo
      adds  4d479443934 [RISCV] Define the vfmin, vfmax RVV intrinsics
      adds  032600b9aef [RISCV] Define vmerge/vfmerge intrinsics.
      adds  bdef1f87aba [llvm-readobj] - Dump the ELF file type better.
      adds  6301871d06d [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwn [...]
      adds  221fdedc692 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses
      adds  65ba0cd3955 [mlir] Modernize std-to-llvm operation conversion doc
      adds  8451d4872ed [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All  [...]
      adds  32a884c9c52 [mlir] Add translation of omp.wsloop to LLVM IR
      adds  19a0d0a40ce [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() [...]
      adds  25a02c3d1a6 Revert "PR24076, PR33655, C++ CWG 1558: Consider the instan [...]
      adds  eb9483b2105 [format] Add overload to parseConfiguration that accept llv [...]
      adds  7ed9cfc7b19 [mlir] Remove static constructors from LLVMType
      adds  c3acda0798f [VE] Vector 'and' isel and tests
      adds  acaa6e4260c [NFC] Uniquify 'const' in TargetTransformInfoImpl.h
      adds  a9f14cdc620 [ARM] Add bank conflict hazarding
      adds  6e603464959 [OpenMP] Fixing Typo in Documentation
      adds  5426b2f9ed9 [clang-format] PR48535 clang-format Incorrectly Removes Spa [...]
      adds  031743cb5b3 [clang-format] PR48539 ReflowComments breaks Qt translation [...]
      adds  1d0dc9be6d7 [MLIR][SPIRV] Add rewrite pattern to convert select+cmp int [...]
      adds  2522fa053b6 [clangd] Do not take stale definition from the static index.
      adds  9fb074e7bb1 [BPI] Improve static heuristics for "cold" paths.
      adds  e122a71a0a2 [TableGen] Add the !substr() bang operator
      adds  9d1140e18e6 [lld-macho] Simulator & DriverKit executables should always be PIE
      adds  631501b1f90 [OpenMP] Fixing typo on memory size in Documenation
      adds  7ad666798f1 Revert 741978d727 and things that landed on top of it.
      adds  42980a789d2 [mlir][spirv] Convert functions returning one value
      adds  fcf9479f7d6 [lldb] Don't instrument demangling.
      adds  a9448872fec [lldb] Refactor and simplify GetCommandSPExact interface
      adds  e0110a47402 [RISCV] Add intrinsics for vfmv.v.f
      adds  b920adf3b4f This is a test commit
      adds  3b3a9d24188 Updated GettingInvolved.md to reflect Flang Biweekly Call changes
      adds  b1191c84380 [IROutliner] Adding support for elevating constants that ar [...]
      adds  bbd758a7913 Revert "This is a test commit"
      adds  1876a2914fe Revert more changes that landed on top of 741978d727
      adds  74186880ba9 [mlir][vector] Add more vector Ops canonicalization
      adds  4c37453a04f clang: Build and run FrontendTests with CLANG_ENABLE_STATIC [...]
      adds  e1248447092 [LoopIdiom] Introduce 'left-shift until bittest' idiom
      adds  cb2e5980bae [LoopIdiom] 'left-shift until bittest' idiom: support const [...]
      adds  a0ddc61c5b9 [LoopIdiom] 'left-shift until bittest' idiom: support canon [...]
      adds  2b61e7c68cd [LoopIdiom] 'left-shift until bittest' idiom: support rewri [...]
      adds  a16fbff17d3 [mlir][spirv] Create a pass for testing SCFToSPIRV patterns
      adds  34e70d722df Append ".__part." to every basic block section symbol.
      adds  930c74f12d7 [mlir][spirv] NFC: rename SPIR-V conversion files for consistency
      adds  897990e614c [IROutliner] Use isa instead of dyn_cast where the casted v [...]
      adds  ae895ac4b9f [mlir][spirv] De-template deserialization
      adds  fc41777702a [mlir][spirv] De-template serialization
      adds  de127d83d81 [InstCombine] Add tests for PR48577 (NFC)
      adds  899faa50f20 [InstCombine] Check inbounds in load/store of gep null tran [...]
      adds  1a7ac29a89f [RISCV] Add ISel support for RVV vector/scalar forms
      adds  c7e825b910a [format][NFC] Use unsigned char as the base of all enums in [...]
      adds  87087a02ae4 [InstCombine] Add tests for gep of null (NFC)
      adds  eb79fd3c928 [InstCombine] Fold gep inbounds of null to null
      adds  759b8c11c39 [InstCombine] Handle different pointer types when folding g [...]
      adds  cce473e0c56 [IRSim] Adding commutativity matching to structure checking
      adds  05039266024 [IRSim] Adding support for isomorphic predicates
      adds  f8079355c60 [InstCombine] canonicalizeAbsNabs(): don't propagate NSW fl [...]
      adds  374f1d81feb [clang-format] Fix handling of TextProto comments
      adds  47877c9079c [clang-format] Add SpaceBeforeCaseColon option
      adds  45a4f34bd19 Revert "[IRSim] Adding support for isomorphic predicates"
      adds  74b3acefc7b [clangd] Fix case mismatch crash on in CDB on windows after [...]
      adds  d97e9f1a3d8 [lldb] Simplify ObjectFile::FindPlugin (NFC)
      adds  7143923f86b Fix lldb test failure due to D93082.
      adds  be89d7460b6 [lld][test] Relax test assertion of cmake defaults appearin [...]
      adds  747f67e034a [AMDGPU] Fix adjustWritemask subreg handling
      adds  245218bb355 Basic: Support named pipes natively in SourceManager and Fi [...]
      adds  3ee43adfb20 Basic: Add native support for stdin to SourceManager and Fi [...]
      adds  ca1ab0c66d1 [mlir] Add tensor passes to passes.md
      adds  d29f93bda51 [DAGCombiner] Don't create sexts of deleted xors when they  [...]
      adds  69132d12dea [Clang] Reverse test to save on indentation. NFC.
      adds  48ad8194a56 [IRSim] Adding support for isomorphic predicates
      adds  db7a2f347f1 Precommit transform tests that have poison as insertelement [...]
      adds  30365472489 Precommit analysis/etc tests for inselt poison placeholder
No new revisions were added by this update.
Summary of changes:
 .../clangd/GlobalCompilationDatabase.cpp           |   11 +-
 clang-tools-extra/clangd/index/Merge.cpp           |    6 +
 clang-tools-extra/clangd/unittests/IndexTests.cpp  |   34 +
 clang/docs/ClangFormatStyleOptions.rst             |   10 +
 clang/docs/ReleaseNotes.rst                        |    3 +
 clang/docs/tools/dump_format_style.py              |    2 +-
 clang/include/clang/AST/Type.h                     |    4 +-
 clang/include/clang/Basic/CodeGenOptions.h         |    2 -
 clang/include/clang/Basic/DiagnosticDriverKinds.td |    2 +
 .../include/clang/Basic/DiagnosticFrontendKinds.td |    2 +
 clang/include/clang/Basic/FileEntry.h              |    9 +
 clang/include/clang/Basic/FileManager.h            |   11 +
 clang/include/clang/Driver/Options.td              | 1362 +++----
 clang/include/clang/Format/Format.h                |   81 +-
 clang/lib/AST/ItaniumMangle.cpp                    |    4 -
 clang/lib/Basic/FileEntry.cpp                      |    1 +
 clang/lib/Basic/FileManager.cpp                    |   25 +-
 clang/lib/Basic/SourceManager.cpp                  |   50 +-
 clang/lib/CodeGen/CodeGenAction.cpp                |  126 +-
 clang/lib/Format/BreakableToken.cpp                |   13 +-
 clang/lib/Format/Format.cpp                        |   18 +-
 clang/lib/Format/TokenAnnotator.cpp                |   15 +-
 clang/lib/Frontend/CompilerInstance.cpp            |   58 +-
 clang/lib/Frontend/CompilerInvocation.cpp          |  902 ++++-
 clang/test/CXX/drs/dr15xx.cpp                      |   14 -
 clang/test/CodeGen/basic-block-sections.c          |   10 +-
 clang/test/CodeGenCXX/mangle-template.cpp          |   20 -
 clang/test/Format/error-config.cpp                 |    4 +-
 clang/test/Misc/dev-fd-fs.c                        |   13 +
 clang/test/Profile/c-generate.c                    |    2 +-
 .../test/SemaTemplate/instantiation-dependence.cpp |   74 -
 .../test/SemaTemplate/partial-spec-instantiate.cpp |   18 +-
 clang/unittests/CMakeLists.txt                     |    2 +-
 clang/unittests/Format/FormatTest.cpp              |  135 +
 clang/unittests/Format/FormatTestComments.cpp      |    6 +
 clang/unittests/Format/FormatTestTextProto.cpp     |   16 +-
 .../unittests/Frontend/CompilerInvocationTest.cpp  |   84 +-
 clang/www/cxx_dr_status.html                       |    2 +-
 flang/docs/GettingInvolved.md                      |    6 +-
 lld/MachO/Driver.cpp                               |   33 +-
 lld/test/ELF/lto/basic-block-sections.ll           |    8 +-
 lld/test/MachO/driver.test                         |    2 +-
 lld/test/MachO/platform-version.s                  |    2 +-
 lld/test/MachO/x86-64-reloc-unsigned.s             |    4 +
 lldb/include/lldb/Interpreter/CommandInterpreter.h |    2 +-
 lldb/source/Commands/CommandObjectCommands.cpp     |    7 +-
 lldb/source/Core/Mangled.cpp                       |    9 -
 lldb/source/Interpreter/CommandInterpreter.cpp     |  139 +-
 lldb/source/Symbol/ObjectFile.cpp                  |  228 +-
 lldb/test/Shell/Unwind/basic-block-sections.test   |   14 +-
 llvm/docs/TableGen/ProgRef.rst                     |   10 +-
 llvm/include/llvm/Analysis/BranchProbabilityInfo.h |  153 +-
 .../include/llvm/Analysis/IRSimilarityIdentifier.h |   37 +-
 .../llvm/Analysis/LazyBranchProbabilityInfo.h      |    2 +-
 .../llvm/Analysis/TargetTransformInfoImpl.h        |  196 +-
 llvm/include/llvm/IR/IntrinsicsRISCV.td            |   15 +
 llvm/include/llvm/Option/OptParser.td              |   18 +-
 llvm/include/llvm/TableGen/Record.h                |    2 +-
 llvm/include/llvm/Transforms/IPO/IROutliner.h      |   13 +-
 llvm/lib/Analysis/BranchProbabilityInfo.cpp        |  645 ++--
 llvm/lib/Analysis/IRSimilarityIdentifier.cpp       |  226 +-
 llvm/lib/Analysis/OptimizationRemarkEmitter.cpp    |    2 +-
 llvm/lib/CodeGen/MachineBasicBlock.cpp             |    5 +-
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |   14 +-
 llvm/lib/Passes/PassRegistry.def                   |    2 +-
 llvm/lib/TableGen/Record.cpp                       |   28 +-
 llvm/lib/TableGen/TGLexer.cpp                      |    1 +
 llvm/lib/TableGen/TGLexer.h                        |    6 +-
 llvm/lib/TableGen/TGParser.cpp                     |   95 +-
 llvm/lib/TableGen/TGParser.h                       |    1 +
 .../Target/AMDGPU/AMDGPUInstructionSelector.cpp    |   18 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp          |    4 +-
 llvm/lib/Target/ARM/ARM.td                         |    4 +-
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp           |   25 +
 llvm/lib/Target/ARM/ARMBaseInstrInfo.h             |    4 +
 llvm/lib/Target/ARM/ARMHazardRecognizer.cpp        |  173 +
 llvm/lib/Target/ARM/ARMHazardRecognizer.h          |   32 +
 llvm/lib/Target/ARM/ARMSubtarget.cpp               |    1 +
 llvm/lib/Target/ARM/ARMSubtarget.h                 |    2 +
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp        |   46 +
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h          |    3 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp        |   57 +
 llvm/lib/Target/RISCV/RISCVISelLowering.h          |    4 +
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td    |  191 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td |  166 +
 llvm/lib/Target/VE/VVPInstrInfo.td                 |    3 +
 llvm/lib/Target/VE/VVPInstrPatternsVec.td          |    3 +
 llvm/lib/Target/VE/VVPNodes.def                    |    1 +
 llvm/lib/Transforms/IPO/IROutliner.cpp             |  209 +-
 .../InstCombine/InstCombineLoadStoreAlloca.cpp     |   24 +-
 .../Transforms/InstCombine/InstCombineSelect.cpp   |    7 +-
 .../InstCombine/InstructionCombining.cpp           |    7 +
 llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp  |  326 +-
 llvm/lib/Transforms/Scalar/LoopPredication.cpp     |    2 +-
 .../Analysis/BlockFrequencyInfo/redundant_edges.ll |    2 +-
 llvm/test/Analysis/BranchProbabilityInfo/basic.ll  |   40 +-
 .../BranchProbabilityInfo/deopt-intrinsic.ll       |    4 +-
 .../Analysis/BranchProbabilityInfo/deopt-invoke.ll |  107 +
 llvm/test/Analysis/BranchProbabilityInfo/loop.ll   |  209 +-
 .../Analysis/BranchProbabilityInfo/noreturn.ll     |   35 +-
 .../Analysis/BranchProbabilityInfo/unreachable.ll  |  154 +
 .../CostModel/AArch64/kryo-inseltpoison.ll         |   26 +
 .../PowerPC/insert_extract-inseltpoison.ll         |  187 +
 .../CostModel/SystemZ/vectorinstrs-inseltpoison.ll |   56 +
 .../X86/insert-extract-at-zero-inseltpoison.ll     |   40 +
 .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll |   39 +
 .../X86/masked-intrinsic-cost-inseltpoison.ll      | 1911 ++++++++++
 .../CostModel/X86/uniformshift-inseltpoison.ll     |   39 +
 .../CostModel/X86/vector-insert-inseltpoison.ll    | 1270 +++++++
 .../CostModel/X86/vector_gep-inseltpoison.ll       |   17 +
 .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 1843 ++++++++++
 .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 1867 ++++++++++
 .../CostModel/X86/vshift-shl-cost-inseltpoison.ll  | 2197 +++++++++++
 .../Analysis/DemandedBits/vectors-inseltpoison.ll  |  136 +
 .../irtranslator-invoke-probabilities.ll           |    2 +-
 .../GlobalISel/extractelement-stack-lower.ll       | 1675 +++++----
 .../CodeGen/AMDGPU/GlobalISel/extractelement.ll    |   16 +-
 .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll |   64 +-
 .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll    |  260 +-
 .../GlobalISel/llvm.amdgcn.global.atomic.fadd.ll   |   30 +-
 .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll  |   89 +-
 .../transform-block-with-return-to-epilog.ll       |    4 +-
 llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll   |    2 +-
 llvm/test/CodeGen/ARM/sub-cmp-peephole.ll          |    2 +-
 .../CodeGen/ARM/v8m.base-jumptable_alignment.ll    |   22 +-
 llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll        |  182 +-
 llvm/test/CodeGen/PowerPC/pr36292.ll               |    5 +-
 llvm/test/CodeGen/PowerPC/sms-cpy-1.ll             |    1 +
 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll    |  822 +++++
 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll    |  794 ++++
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll          |  881 +++++
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll          | 1201 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll        |  441 +++
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll        |  601 +++
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll          |  881 +++++
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll          | 1201 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll       |  421 +++
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll       |  421 +++
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll        |  482 +++
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll        |  868 +++++
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll        |  482 +++
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll        |  868 +++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll       |  482 +++
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll       |  868 +++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll       |  482 +++
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll       |  868 +++++
 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll         |  973 +++++
 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll         | 1189 ++++++
 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll     | 1109 ++++++
 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll     | 1081 ++++++
 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll    |  845 +++++
 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll    |  817 +++++
 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll         |  266 ++
 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll    |  845 +++++
 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll    |  817 +++++
 llvm/test/CodeGen/SPARC/missinglabel.ll            |    2 +-
 llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir       |    4 +-
 llvm/test/CodeGen/SystemZ/sext-zext.ll             |   19 +
 llvm/test/CodeGen/Thumb2/schedm7-hazard.ll         |   38 +
 llvm/test/CodeGen/VE/Vector/vec_and.ll             |  132 +
 .../WebAssembly/switch-unreachable-default.ll      |    4 +-
 llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll   |   19 +-
 .../X86/basic-block-sections-blockaddress-taken.ll |    4 +-
 .../X86/basic-block-sections-clusters-branches.ll  |    8 +-
 .../X86/basic-block-sections-clusters-eh.ll        |    4 +-
 .../CodeGen/X86/basic-block-sections-clusters.ll   |    8 +-
 .../X86/basic-block-sections-directjumps.ll        |   14 +-
 llvm/test/CodeGen/X86/basic-block-sections-eh.ll   |    4 +-
 llvm/test/CodeGen/X86/basic-block-sections-list.ll |   16 +-
 .../CodeGen/X86/basic-block-sections-listbb.ll     |    4 +-
 .../CodeGen/X86/basic-block-sections-mir-parse.mir |    6 +-
 .../X86/basic-block-sections-unreachable.ll        |    2 +-
 llvm/test/CodeGen/X86/basic-block-sections.ll      |   12 +-
 llvm/test/CodeGen/X86/basic-block-sections_2.ll    |   61 +
 llvm/test/CodeGen/X86/block-placement.ll           |    4 +-
 .../test/CodeGen/X86/cfi-basic-block-sections-1.ll |    8 +-
 ...r-basic-block-sections-callee-save-registers.ll |    4 +-
 .../CodeGen/X86/gcc_except_table_bb_sections.ll    |   22 +-
 .../CodeGen/X86/misched_phys_reg_assign_order.ll   |    6 +-
 llvm/test/CodeGen/X86/pr27501.ll                   |   10 +-
 llvm/test/CodeGen/X86/pr37916.ll                   |    2 +-
 llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll      |  117 +-
 llvm/test/DebugInfo/X86/basic-block-sections_1.ll  |   24 +-
 .../X86/stack-value-piece-inseltpoison.ll          |  114 +
 llvm/test/Object/elf-unknown-type.test             |   10 -
 llvm/test/Other/scalable-vectors-core-ir.ll        |   12 +-
 llvm/test/TableGen/substr.td                       |   81 +
 .../Attributor/dereferenceable-2-inseltpoison.ll   |  847 +++++
 llvm/test/Transforms/BDCE/vectors-inseltpoison.ll  |  102 +
 .../AArch64/gather-scatter-opt-inseltpoison.ll     |  113 +
 .../bypass-slow-div-debug-info-inseltpoison.ll     |   76 +
 .../ARM/sink-add-mul-shufflevector-inseltpoison.ll |  219 ++
 .../CodeGenPrepare/ARM/sinkchain-inseltpoison.ll   |  107 +
 .../X86/gather-scatter-opt-inseltpoison.ll         |  113 +
 .../X86/sink-addrmode-inseltpoison.ll              |  321 ++
 .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll   |  406 +++
 .../X86/x86-shuffle-sink-inseltpoison.ll           |  257 ++
 .../2016-08-30-MaskedScatterGather-inseltpoison.ll |   42 +
 ...xpr-vector-constainsundef-crash-inseltpoison.ll |   25 +
 .../GVN/non-integral-pointers-inseltpoison.ll      |  456 +++
 .../IROutliner/outlining-commutative-fp.ll         |  107 +
 .../Transforms/IROutliner/outlining-commutative.ll |  254 ++
 .../IROutliner/outlining-constants-vs-registers.ll |   42 +-
 .../IROutliner/outlining-different-constants.ll    |   24 +-
 .../IROutliner/outlining-different-globals.ll      |   14 +-
 .../IROutliner/outlining-isomorphic-predicates.ll  |  170 +
 .../AMDGPU/old-pass-regressions-inseltpoison.ll    |  143 +
 .../dereferenceable-inseltpoison.ll                |  357 ++
 .../AArch64/sve-bitcast-inseltpoison.ll            |   13 +
 .../amdgcn-demanded-vector-elts-inseltpoison.ll    | 3828 ++++++++++++++++++++
 .../InstCombine/X86/x86-addsub-inseltpoison.ll     |  194 +
 .../InstCombine/X86/x86-avx512-inseltpoison.ll     | 3407 +++++++++++++++++
 .../InstCombine/X86/x86-pack-inseltpoison.ll       |  635 ++++
 .../InstCombine/X86/x86-sse-inseltpoison.ll        |  694 ++++
 .../InstCombine/X86/x86-sse2-inseltpoison.ll       |  541 +++
 .../InstCombine/X86/x86-sse41-inseltpoison.ll      |  124 +
 .../X86/x86-vec_demanded_elts-inseltpoison.ll      |  110 +
 .../X86/x86-vector-shifts-inseltpoison.ll          | 3783 +++++++++++++++++++
 .../InstCombine/X86/x86-xop-inseltpoison.ll        |  305 ++
 llvm/test/Transforms/InstCombine/abs-1.ll          |    6 +-
 llvm/test/Transforms/InstCombine/abs_abs.ll        |  148 +-
 .../Transforms/InstCombine/bitcast-inseltpoison.ll |  573 +++
 .../InstCombine/bitcast-vec-canon-inseltpoison.ll  |  167 +
 .../InstCombine/broadcast-inseltpoison.ll          |  179 +
 .../InstCombine/extractelement-inseltpoison.ll     |  332 ++
 .../InstCombine/fold-vector-zero-inseltpoison.ll   |   35 +
 llvm/test/Transforms/InstCombine/getelementptr.ll  |   34 +
 .../InstCombine/icmp-bc-vec-inseltpoison.ll        |  127 +
 .../InstCombine/inselt-binop-inseltpoison.ll       |  635 ++++
 .../insert-extract-shuffle-inseltpoison.ll         |  735 ++++
 llvm/test/Transforms/InstCombine/load.ll           |   19 +-
 .../InstCombine/masked_intrinsics-inseltpoison.ll  |  271 ++
 .../Transforms/InstCombine/pr38984-inseltpoison.ll |   41 +
 .../InstCombine/scalarization-inseltpoison.ll      |  335 ++
 .../select-extractelement-inseltpoison.ll          |  213 ++
 llvm/test/Transforms/InstCombine/select_meta.ll    |    4 +-
 .../InstCombine/shift-add-inseltpoison.ll          |  122 +
 .../shufflevector-div-rem-inseltpoison.ll          |  122 +
 llvm/test/Transforms/InstCombine/store.ll          |   26 +-
 .../trunc-extractelement-inseltpoison.ll           |  195 +
 .../InstCombine/udiv-pow2-vscale-inseltpoison.ll   |   27 +
 .../InstCombine/vec_demanded_elts-inseltpoison.ll  |  850 +++++
 .../vec_extract_var_elt-inseltpoison.ll            |   26 +
 .../InstCombine/vec_gep_scalar_arg-inseltpoison.ll |   16 +
 .../InstCombine/vec_phi_extract-inseltpoison.ll    |  107 +
 .../InstCombine/vec_shuffle-inseltpoison.ll        | 1790 +++++++++
 .../InstCombine/vector-casts-inseltpoison.ll       |  413 +++
 .../InstCombine/vector_gep1-inseltpoison.ll        |   74 +
 .../vector_insertelt_shuffle-inseltpoison.ll       |   93 +
 .../vscale_extractelement-inseltpoison.ll          |  185 +
 .../vscale_insertelement-inseltpoison.ll           |  102 +
 .../ConstProp/InsertElement-inseltpoison.ll        |   52 +
 .../InstSimplify/ConstProp/vscale-inseltpoison.ll  |  301 ++
 .../ConstProp/vscale-shufflevector-inseltpoison.ll |   39 +
 .../Transforms/InstSimplify/select-inseltpoison.ll | 1007 +++++
 .../Transforms/InstSimplify/vscale-inseltpoison.ll |  199 +
 .../test/Transforms/JumpThreading/thread-prob-3.ll |    4 +-
 .../AMDGPU/selects-inseltpoison.ll                 |   95 +
 .../X86/load-width-inseltpoison.ll                 |   40 +
 .../X86/vectorize-i8-nested-add-inseltpoison.ll    |  165 +
 .../LoopIdiom/X86/left-shift-until-bittest.ll      | 1049 ++++--
 .../ARM/vctp-chains-inseltpoison.ll                |  257 ++
 .../p8-unrolling-legalize-vectors-inseltpoison.ll  |  256 ++
 ...08-30-MaskedScatterGather-xfail-inseltpoison.ll |   43 +
 .../PGOProfile/counter_promo_nest-inseltpoison.ll  |  165 +
 .../PhaseOrdering/X86/addsub-inseltpoison.ll       |  101 +
 .../PhaseOrdering/X86/horiz-math-inseltpoison.ll   |  153 +
 .../X86/scalarization-inseltpoison.ll              |   71 +
 .../PhaseOrdering/vector-trunc-inseltpoison.ll     |   23 +
 .../base-vector-inseltpoison.ll                    |  279 ++
 .../check_traversal_order-inseltpoison.ll          |   38 +
 .../live-vector-nosplit-inseltpoison.ll            |  119 +
 .../accelerate-vector-functions-inseltpoison.ll    | 1300 +++++++
 .../AArch64/insertelement-inseltpoison.ll          |   44 +
 .../AArch64/transpose-inseltpoison.ll              |  294 ++
 .../AMDGPU/add_sub_sat-inseltpoison.ll             |  336 ++
 .../SLPVectorizer/AMDGPU/bswap-inseltpoison.ll     |   38 +
 .../SLPVectorizer/AMDGPU/round-inseltpoison.ll     |   38 +
 .../ARM/extract-insert-inseltpoison.ll             |   31 +
 .../non-vectorizable-intrinsic-inseltpoison.ll     |   57 +
 .../SLPVectorizer/X86/PR35865-inseltpoison.ll      |   29 +
 .../X86/alternate-calls-inseltpoison.ll            |   65 +
 .../X86/alternate-cast-inseltpoison.ll             |  466 +++
 .../SLPVectorizer/X86/alternate-fp-inseltpoison.ll |  179 +
 .../X86/alternate-int-inseltpoison.ll              |  497 +++
 .../SLPVectorizer/X86/arith-fp-inseltpoison.ll     | 1365 +++++++
 .../X86/blending-shuffle-inseltpoison.ll           |  200 +
 .../SLPVectorizer/X86/cmp_commute-inseltpoison.ll  |  283 ++
 .../X86/crash_scheduling-inseltpoison.ll           |   81 +
 .../X86/external_user_jumbled_load-inseltpoison.ll |   43 +
 .../X86/extract-shuffle-inseltpoison.ll            |   22 +
 .../SLPVectorizer/X86/fptosi-inseltpoison.ll       |  534 +++
 .../SLPVectorizer/X86/hadd-inseltpoison.ll         |  433 +++
 .../SLPVectorizer/X86/hsub-inseltpoison.ll         |  433 +++
 .../insert-element-build-vector-inseltpoison.ll    |  540 +++
 .../SLPVectorizer/X86/load-merge-inseltpoison.ll   |  208 ++
 .../SLPVectorizer/X86/pr31599-inseltpoison.ll      |   30 +
 .../SLPVectorizer/X86/pr42022-inseltpoison.ll      |  278 ++
 .../SLPVectorizer/X86/pr44067-inseltpoison.ll      |  118 +
 .../SLPVectorizer/X86/pr47629-inseltpoison.ll      |  664 ++++
 .../SLPVectorizer/X86/sext-inseltpoison.ll         | 1039 ++++++
 .../SLPVectorizer/X86/sign-extend-inseltpoison.ll  |   62 +
 .../SLPVectorizer/X86/sitofp-inseltpoison.ll       | 1331 +++++++
 .../SLPVectorizer/X86/value-bug-inseltpoison.ll    |  108 +
 .../X86/vec_list_bias-inseltpoison.ll              |  105 +
 .../SLPVectorizer/X86/zext-inseltpoison.ll         | 1123 ++++++
 .../vectorizable-functions-inseltpoison.ll         |   78 +
 .../Transforms/Scalarizer/basic-inseltpoison.ll    |  561 +++
 .../Scalarizer/dbgloc-bug-inseltpoison.ll          |   44 +
 .../Scalarizer/order-bug-inseltpoison.ll           |   24 +
 .../ARM/speculate-vector-ops-inseltpoison.ll       |  112 +
 .../speculate-vector-ops-inseltpoison.ll           |   60 +
 .../spec-other-inseltpoison.ll                     |   88 +
 .../rebuild-ssa-infinite-loop-inseltpoison.ll      |   53 +
 .../AMDGPU/as-transition-inseltpoison.ll           |   36 +
 .../VectorCombine/Hexagon/load-inseltpoison.ll     |   17 +
 .../X86/extract-binop-inseltpoison.ll              |  575 +++
 .../VectorCombine/X86/insert-binop-inseltpoison.ll |  234 ++
 .../X86/insert-binop-with-constant-inseltpoison.ll |  728 ++++
 .../VectorCombine/X86/load-inseltpoison.ll         |  649 ++++
 .../X86/scalarize-cmp-inseltpoison.ll              |  290 ++
 llvm/test/tools/llvm-readobj/ELF/file-types.test   |   10 +-
 llvm/tools/llvm-readobj/ELFDumper.cpp              |   37 +-
 .../Analysis/IRSimilarityIdentifierTest.cpp        |  190 +-
 llvm/utils/gn/secondary/clang/unittests/BUILD.gn   |    2 +-
 mlir/docs/ConversionToLLVMDialect.md               |  467 ---
 mlir/docs/Dialects/SPIR-V.md                       |    2 +-
 mlir/docs/LLVMDialectMemRefConvention.md           |  439 +++
 mlir/docs/Passes.md                                |    4 +
 mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp         |   21 +-
 mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp         |   21 +-
 .../{ConvertGPUToSPIRV.h => GPUToSPIRV.h}          |   10 +-
 .../{ConvertGPUToSPIRVPass.h => GPUToSPIRVPass.h}  |   19 +-
 .../mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h  |    4 +-
 .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h   |    4 +-
 mlir/include/mlir/Conversion/Passes.h              |    9 +-
 mlir/include/mlir/Conversion/Passes.td             |   17 +
 .../mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h        |    4 +-
 .../SCFToSPIRVPass.h}                              |   14 +-
 .../{ConvertSPIRVToLLVM.h => SPIRVToLLVM.h}        |    8 +-
 ...{ConvertSPIRVToLLVMPass.h => SPIRVToLLVMPass.h} |   10 +-
 .../StandardToLLVM/ConvertStandardToLLVM.h         |   10 +-
 ...{ConvertStandardToSPIRV.h => StandardToSPIRV.h} |   16 +-
 ...StandardToSPIRVPass.h => StandardToSPIRVPass.h} |   14 +-
 .../{ConvertVectorToSPIRV.h => VectorToSPIRV.h}    |   10 +-
 ...vertVectorToSPIRVPass.h => VectorToSPIRVPass.h} |   12 +-
 mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td        |    4 +-
 mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h       |  109 +-
 mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td      |    5 +
 .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h   |   31 +
 mlir/include/mlir/Dialect/Vector/VectorOps.td      |    1 +
 .../include/mlir/Target/LLVMIR/ModuleTranslation.h |    3 +
 mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp    |   54 +-
 .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp  |   31 +-
 mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h     |    6 +-
 .../GPUCommon/IndexIntrinsicsOpLowering.h          |   13 +-
 .../Conversion/GPUCommon/OpToFuncCallLowering.h    |    5 +-
 .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp  |    8 +-
 mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt      |    8 +-
 .../{ConvertGPUToSPIRV.cpp => GPUToSPIRV.cpp}      |    7 +-
 ...onvertGPUToSPIRVPass.cpp => GPUToSPIRVPass.cpp} |   15 +-
 .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp |   61 +-
 mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp  |    2 +-
 mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt   |    2 +-
 .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp |    2 +-
 .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp |    2 +-
 mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt      |    5 +-
 mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp      |    5 +-
 .../SCFToSPIRVPass.cpp}                            |   25 +-
 mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt     |    4 +-
 .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp   |   11 +-
 .../{ConvertSPIRVToLLVM.cpp => SPIRVToLLVM.cpp}    |   26 +-
 ...vertSPIRVToLLVMPass.cpp => SPIRVToLLVMPass.cpp} |    6 +-
 .../Conversion/StandardToLLVM/StandardToLLVM.cpp   |  110 +-
 mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt |    6 +-
 .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp   |    4 +-
 ...vertStandardToSPIRV.cpp => StandardToSPIRV.cpp} |   12 +-
 ...dardToSPIRVPass.cpp => StandardToSPIRVPass.cpp} |    9 +-
 .../VectorToLLVM/ConvertVectorToLLVM.cpp           |   26 +-
 .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp |    4 +-
 mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt   |    1 +
 .../lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp |   43 +-
 .../VectorToSPIRVPass.cpp}                         |   33 +-
 mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp         |   45 +-
 mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp           |  121 +-
 mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp         |   17 +-
 mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp        |   12 +-
 mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt           |    1 +
 mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td |   30 +
 .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp |   35 +
 .../Dialect/SPIRV/Transforms/SPIRVConversion.cpp   |   12 +-
 mlir/lib/Dialect/Vector/VectorOps.cpp              |   99 +-
 mlir/lib/Target/LLVMIR/ModuleTranslation.cpp       |  132 +-
 mlir/lib/Target/SPIRV/Deserialization.cpp          |  106 +
 mlir/lib/Target/SPIRV/Serialization.cpp            |   62 +-
 ...est_spirv_entry_point.mlir => entry-point.mlir} |    0
 mlir/test/Conversion/GPUToSPIRV/if.mlir            |  167 -
 mlir/test/Conversion/GPUToSPIRV/loop.mlir          |   98 -
 mlir/test/Conversion/SCFToSPIRV/for.mlir           |   86 +
 mlir/test/Conversion/SCFToSPIRV/if.mlir            |  156 +
 .../StandardToSPIRV/std-ops-to-spirv.mlir          |   26 +
 .../SPIRV/Transforms/glsl_canonicalize.mlir        |  113 +
 mlir/test/Dialect/Vector/canonicalize.mlir         |   47 +
 mlir/test/Target/openmp-llvm.mlir                  |   34 +-
 mlir/test/lib/Dialect/SPIRV/CMakeLists.txt         |    1 +
 .../lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp |   39 +
 mlir/test/lib/Transforms/TestConvertCallOp.cpp     |    3 +-
 mlir/tools/mlir-opt/mlir-opt.cpp                   |    2 +
 .../mlir-spirv-cpu-runner.cpp                      |    4 +-
 mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp           |   50 +-
 .../mlir-vulkan-runner/mlir-vulkan-runner.cpp      |    4 +-
 openmp/docs/design/Runtimes.rst                    |    4 +-
 412 files changed, 85182 insertions(+), 5289 deletions(-)
 delete mode 100644 clang/test/SemaTemplate/instantiation-dependence.cpp
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
 create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
 create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
 create mode 100644 llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltp [...]
 create mode 100644 llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
 create mode 100644 llvm/test/CodeGen/VE/Vector/vec_and.ll
 create mode 100644 llvm/test/CodeGen/X86/basic-block-sections_2.ll
 create mode 100644 llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll
 delete mode 100644 llvm/test/Object/elf-unknown-type.test
 create mode 100644 llvm/test/TableGen/substr.td
 create mode 100644 llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt- [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debu [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevec [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inse [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inselt [...]
 create mode 100644 llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltp [...]
 create mode 100644 llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash- [...]
 create mode 100644 llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative.ll
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll
 create mode 100644 llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regress [...]
 create mode 100644 llvm/test/Transforms/InferFunctionAttrs/dereferenceable-inseltp [...]
 create mode 100644 llvm/test/Transforms/InstCombine/AArch64/sve-bitcast-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector- [...]
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inse [...]
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/fold-vector-zero-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltp [...]
 create mode 100644 llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/pr38984-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/udiv-pow2-vscale-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vector_insertelt_shuffle-insel [...]
 create mode 100644 llvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/InsertElement-insel [...]
 create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevecto [...]
 create mode 100644 llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltp [...]
 create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/X86/load-width-inseltp [...]
 create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-neste [...]
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltp [...]
 create mode 100644 llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-v [...]
 create mode 100644 llvm/test/Transforms/NewGVN/2016-08-30-MaskedScatterGather-xfai [...]
 create mode 100644 llvm/test/Transforms/PGOProfile/counter_promo_nest-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/PhaseOrdering/vector-trunc-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/RewriteStatepointsForGC/base-vector-inselt [...]
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (3c707d73f26 -> 30365472489)