[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (120a5e9a745 -> 02c19658ffe)

30 Sep 2019


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig
in repository toolchain/ci/llvm-project.
from  120a5e9a745 [ARM] Cortex-M4 schedule additions
      adds  72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter
      adds  83476b813e2 [clang-format] Reference qualifiers in member templates cau [...]
      adds  8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...]
      adds  d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...]
      adds  c5133606627 [MC] Emit unused undefined symbol even if its binding is not set
      adds  eb78dea4ccd [Docs] Moves article links to new pages
      adds  a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass
      adds  aabf8cbfca8 Add test case peeking through vector concat when combining  [...]
      adds  0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops.
      adds  00966d1791f Don't crash if a variable with a constexpr destructor has a [...]
      adds  1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...]
      adds  6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...]
      adds  9a5e3d39f69 Undef the macros after their use
      adds  1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...]
      adds  4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...]
      adds  34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...]
      adds  317d991fa51 AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor
      adds  5951e3f8134 [X86] Remove some redundant isel patterns. NFCI
      adds  e794c049b3e [SystemZ]  Add SystemZPostRewrite in addPostRegAlloc() inst [...]
      adds  0f30960619f Reland "[utils] Implement the llvm-locstats tool"
      adds  58e8c793d0e Revert "[SCEV] add no wrap flag for SCEVAddExpr."
      adds  1249126c7c6 Revert "Update polly test for SCEV change."
      adds  b3438f1cc04 [ARM][CGP] Allow signext arguments
      adds  5a2a14db0bc [TargetLowering] Simplify expansion of S{ADD,SUB}O
      adds  aac03ae06a8 [ARM][MVE] Change VCTP operand
      adds  180f1feba9f [llvm-locstats] Fix the test for the Hexagon target
      adds  8569c0f1ab8 Pre-commit a test case for PR43129.
      adds  dc7dbb1a888 NFC changes to SelectionDAGBuilder::visitBitTestHeader(), p [...]
      adds  e3b4f0ec256 [NFC][ARM][MVE] More tests
      adds  e7714fe7bff [lldb][clang][modern-type-lookup] Use ASTImporterSharedStat [...]
      adds  5a039d55710 [lldb] Partly revert 370734: Test 'frame select -r' and fix [...]
      adds  17380227e83 [Alignment][NFC] Remove LoadInst::setAlignment(unsigned)
       new  02c19658ffe [Alignment][NFC] Adding a max function.
The 1 revisions listed above as "new" are entirely new to this
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Summary of changes:
 clang/include/clang/AST/ExternalASTMerger.h        |    6 +
 clang/lib/AST/ExternalASTMerger.cpp                |   12 +-
 clang/lib/CodeGen/CGCleanup.cpp                    |    2 +-
 clang/lib/Format/TokenAnnotator.cpp                |   25 +-
 clang/lib/Sema/SemaDeclCXX.cpp                     |    3 +-
 clang/test/SemaCXX/constant-expression-cxx2a.cpp   |    9 +
 clang/unittests/Format/FormatTest.cpp              |   68 +
 lld/test/ELF/arm-attributes.s                      |    6 +-
 lld/test/ELF/ppc64-abs64-dyn.s                     |    8 +-
 lld/test/ELF/ppc64-relocs.s                        |    4 +-
 .../test/commands/frame/select/TestFrameSelect.py  |    4 -
 .../modern-type-lookup/libcxx/Makefile             |    3 +
 .../libcxx/TestLibCxxModernTypeLookup.py           |   20 +
 .../modern-type-lookup/libcxx/main.cpp             |    6 +
 lldb/source/Commands/CommandObjectFrame.cpp        |   32 +-
 llvm/CMakeLists.txt                                |    4 +
 llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c     |    6 +
 llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml     |    3 +
 llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli    |    5 +
 .../transforms/scalar_opts/llvm_scalar_opts.ml     |    3 +
 .../transforms/scalar_opts/llvm_scalar_opts.mli    |    5 +
 .../transforms/scalar_opts/scalar_opts_ocaml.c     |    5 +
 llvm/docs/CommandGuide/index.rst                   |    1 +
 llvm/docs/CommandGuide/llvm-locstats.rst           |   79 +
 llvm/docs/ProgrammingDocumentation.rst             |    5 +
 llvm/docs/Reference.rst                            |   24 +-
 llvm/docs/SubsystemDocumentation.rst               |   28 +-
 llvm/docs/_templates/indexsidebar.html             |    2 +
 llvm/docs/index.rst                                |    3 -
 llvm/include/llvm-c/Transforms/IPO.h               |    3 +
 llvm/include/llvm-c/Transforms/Scalar.h            |    3 +
 llvm/include/llvm/IR/IRBuilder.h                   |    6 +-
 llvm/include/llvm/IR/Instructions.h                |    2 -
 llvm/include/llvm/MC/MCLinkerOptimizationHint.h    |    2 +
 llvm/include/llvm/Support/Alignment.h              |    8 +
 .../llvm/Transforms/Vectorize/SLPVectorizer.h      |    9 +-
 llvm/lib/Analysis/ScalarEvolution.cpp              |    2 +-
 llvm/lib/CodeGen/AtomicExpandPass.cpp              |    4 +-
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |    8 +-
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp   |   31 +-
 llvm/lib/IR/Core.cpp                               |    2 +-
 llvm/lib/IR/Instructions.cpp                       |    8 +-
 llvm/lib/MC/ELFObjectWriter.cpp                    |    3 -
 llvm/lib/Target/AMDGPU/VOP2Instructions.td         |   32 +-
 llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp          |    7 +-
 llvm/lib/Target/ARM/MVETailPredication.cpp         |    6 +-
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp          |    2 +-
 llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp   |    5 +-
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp            |   80 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            | 1330 +--------
 llvm/lib/Target/X86/X86InstrAVX512.td              |   78 -
 llvm/lib/Target/X86/X86TargetTransformInfo.cpp     |   86 +-
 llvm/lib/Transforms/IPO/ArgumentPromotion.cpp      |    2 +-
 llvm/lib/Transforms/IPO/Attributor.cpp             |    2 +-
 llvm/lib/Transforms/IPO/IPO.cpp                    |    4 +
 .../InstCombine/InstCombineAtomicRMW.cpp           |    2 +-
 .../Transforms/InstCombine/InstCombineCalls.cpp    |    2 +-
 .../InstCombine/InstCombineLoadStoreAlloca.cpp     |    8 +-
 .../Instrumentation/DataFlowSanitizer.cpp          |    2 +-
 .../Transforms/Scalar/AlignmentFromAssumptions.cpp |    2 +-
 llvm/lib/Transforms/Scalar/DivRemPairs.cpp         |    2 -
 llvm/lib/Transforms/Scalar/GVNHoist.cpp            |    5 +-
 llvm/lib/Transforms/Scalar/LICM.cpp                |    2 +-
 llvm/lib/Transforms/Scalar/SROA.cpp                |    8 +-
 llvm/lib/Transforms/Scalar/Scalar.cpp              |    4 +
 llvm/lib/Transforms/Utils/VNCoercion.cpp           |    2 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |  159 +-
 llvm/test/Analysis/ScalarEvolution/limit-depth.ll  |    2 +-
 llvm/test/Analysis/ScalarEvolution/nsw.ll          |    2 +-
 llvm/test/Analysis/ScalarEvolution/trip-count12.ll |    2 +-
 llvm/test/Analysis/ScalarEvolution/trip-count9.ll  |    8 +-
 llvm/test/CodeGen/AArch64/sadd_sat.ll              |   10 +-
 llvm/test/CodeGen/AArch64/sadd_sat_vec.ll          |  470 +--
 llvm/test/CodeGen/AArch64/ssub_sat.ll              |   11 +-
 llvm/test/CodeGen/AArch64/ssub_sat_vec.ll          |  511 +---
 .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir  |   30 +-
 .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir   |   30 +-
 .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir  |   30 +-
 llvm/test/CodeGen/AMDGPU/saddo.ll                  |  478 ++--
 llvm/test/CodeGen/ARM/CGP/arm-cgp-overflow.ll      |    7 +-
 llvm/test/CodeGen/ARM/CGP/arm-cgp-phis-ret.ll      |   32 +
 llvm/test/CodeGen/ARM/CGP/arm-cgp-signed.ll        |   31 +-
 llvm/test/CodeGen/ARM/addsubo-legalization.ll      |  193 +-
 .../ARM/build-attributes-optimization-minsize.ll   |    6 +-
 .../ARM/build-attributes-optimization-mixed.ll     |    6 +-
 .../ARM/build-attributes-optimization-optnone.ll   |    6 +-
 .../ARM/build-attributes-optimization-optsize.ll   |    6 +-
 .../CodeGen/ARM/build-attributes-optimization.ll   |    6 +-
 llvm/test/CodeGen/RISCV/arith-with-overflow.ll     |   28 +-
 llvm/test/CodeGen/SystemZ/cond-move-09.mir         |   29 +
 .../Thumb2/LowOverheadLoops/basic-tail-pred.ll     |   14 +-
 .../cond-vector-reduce-mve-codegen.ll              |   28 +-
 .../Thumb2/LowOverheadLoops/mve-float-loops.ll     | 2014 +++++++++++++
 .../Thumb2/LowOverheadLoops/mve-tail-data-types.ll |   21 +-
 .../test/CodeGen/Thumb2/LowOverheadLoops/nested.ll |    2 +-
 .../Thumb2/LowOverheadLoops/tail-pred-widen.ll     |    2 +-
 .../CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll |    4 +-
 .../LowOverheadLoops/vector-arith-codegen.ll       |   34 +-
 .../LowOverheadLoops/vector-reduce-mve-tail.ll     |    4 +-
 llvm/test/CodeGen/X86/avx512-cvt.ll                |   17 +-
 llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll    |  144 +-
 llvm/test/CodeGen/X86/combine-mulo.ll              |   29 +-
 llvm/test/CodeGen/X86/machine-combiner-int-vec.ll  |  117 +-
 llvm/test/CodeGen/X86/midpoint-int-vec-128.ll      |   12 +-
 llvm/test/CodeGen/X86/midpoint-int-vec-256.ll      |   24 +-
 llvm/test/CodeGen/X86/midpoint-int-vec-512.ll      |   84 +-
 llvm/test/CodeGen/X86/mulo-pow2.ll                 |   13 +-
 llvm/test/CodeGen/X86/sadd_sat.ll                  |   32 +-
 llvm/test/CodeGen/X86/sadd_sat_vec.ll              | 2882 ++++++++-----------
 llvm/test/CodeGen/X86/ssub_sat.ll                  |   36 +-
 llvm/test/CodeGen/X86/ssub_sat_vec.ll              | 2993 ++++++++------------
 llvm/test/CodeGen/X86/switch-bt.ll                 |   40 +
 llvm/test/CodeGen/X86/vec_int_to_fp.ll             |   16 +-
 llvm/test/CodeGen/X86/vec_saddo.ll                 |  965 ++-----
 llvm/test/CodeGen/X86/vec_ssubo.ll                 |  998 ++-----
 llvm/test/CodeGen/X86/vector-bitreverse.ll         |  100 +-
 llvm/test/CodeGen/X86/vector-fshl-256.ll           |    9 +-
 llvm/test/CodeGen/X86/vector-fshl-512.ll           |   56 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-256.ll       |   20 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-512.ll       |   42 +-
 llvm/test/CodeGen/X86/vector-fshr-256.ll           |   29 +-
 llvm/test/CodeGen/X86/vector-fshr-512.ll           |  154 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll       |   20 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll       |   82 +-
 llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll      |    6 +-
 llvm/test/CodeGen/X86/vector-rotate-128.ll         |   77 +-
 llvm/test/CodeGen/X86/vector-rotate-256.ll         |   69 +-
 llvm/test/CodeGen/X86/vector-rotate-512.ll         |   92 +-
 llvm/test/CodeGen/X86/vector-shift-ashr-128.ll     |    3 +-
 llvm/test/CodeGen/X86/vector-shift-ashr-256.ll     |   18 +-
 llvm/test/CodeGen/X86/vector-shift-ashr-512.ll     |   18 +-
 llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll  |    9 +-
 llvm/test/CodeGen/X86/vector-shuffle-combining.ll  |   71 +
 llvm/test/MC/ARM/directive-arch-armv2.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv2a.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv3.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv3m.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv4.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv4t.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv5.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv5t.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv5te.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv6-m.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv6.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv6k.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv6t2.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv6z.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7-a.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7-m.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7-r.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7.s            |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7a.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7e-m.s         |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7em.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7m.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv7r.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-armv8-a.s          |    2 +-
 llvm/test/MC/ARM/directive-arch-armv8.2-a.s        |    2 +-
 llvm/test/MC/ARM/directive-arch-armv8a.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-iwmmxt.s           |    2 +-
 llvm/test/MC/ARM/directive-arch-iwmmxt2.s          |    2 +-
 .../MC/ARM/directive-eabi_attribute-overwrite.s    |    2 +-
 llvm/test/MC/ARM/directive-eabi_attribute.s        |    2 +-
 llvm/test/MC/ARM/directive-fpu-multiple.s          |    2 +-
 llvm/test/MC/ARM/directive-object_arch-2.s         |    2 +-
 llvm/test/MC/ARM/directive-object_arch.s           |    2 +-
 llvm/test/MC/ELF/undef.s                           |   22 +
 llvm/test/MC/ELF/weakref.s                         |    9 +
 .../DivRemPairs/X86/div-expanded-rem-pair.ll       |   36 +
 .../SLPVectorizer/AArch64/gather-root.ll           |  102 +-
 .../Transforms/SLPVectorizer/AArch64/horizontal.ll |   16 -
 .../SLPVectorizer/AArch64/spillcost-di.ll          |    4 +-
 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll  |  153 +
 .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll |   13 +-
 .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll |    5 -
 llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll  |   72 +-
 llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll  |   16 -
 .../Transforms/SLPVectorizer/X86/bad-reduction.ll  |   28 -
 .../SLPVectorizer/X86/horizontal-list.ll           |  354 +--
 .../SLPVectorizer/X86/horizontal-minmax.ll         |  476 +---
 .../Transforms/SLPVectorizer/X86/horizontal.ll     |  148 -
 .../Transforms/SLPVectorizer/X86/long_chains.ll    |    8 +-
 .../SLPVectorizer/X86/reassociated-loads.ll        |   31 -
 .../SLPVectorizer/X86/reduction_loads.ll           |   24 -
 .../SLPVectorizer/X86/reduction_unrolled.ll        |   35 +-
 .../Transforms/SLPVectorizer/X86/remark_horcost.ll |    4 -
 .../SLPVectorizer/X86/reorder_repeated_ops.ll      |   22 -
 .../Transforms/SLPVectorizer/X86/undef_vect.ll     |   10 -
 .../SLPVectorizer/X86/used-reduced-op.ll           |  529 ++++
 .../SLPVectorizer/X86/vectorize-reorder-reuse.ll   |   42 -
 llvm/test/lit.cfg.py                               |    5 +
 llvm/test/tools/llvm-locstats/lit.local.cfg        |    2 +
 llvm/test/tools/llvm-locstats/locstats.ll          |  174 ++
 llvm/unittests/Support/AlignmentTest.cpp           |   23 +
 llvm/utils/llvm-locstats/CMakeLists.txt            |    7 +
 llvm/utils/llvm-locstats/llvm-locstats.py          |  208 ++
 polly/test/DeLICM/reduction_looprotate_hoisted.ll  |    2 +-
 197 files changed, 8537 insertions(+), 9747 deletions(-)
 create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/modern-type [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/modern-type [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/modern-type [...]
 create mode 100644 llvm/docs/CommandGuide/llvm-locstats.rst
 create mode 100644 llvm/test/CodeGen/SystemZ/cond-move-09.mir
 create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
 create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll
 create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
 create mode 100644 llvm/test/tools/llvm-locstats/lit.local.cfg
 create mode 100644 llvm/test/tools/llvm-locstats/locstats.ll
 create mode 100644 llvm/utils/llvm-locstats/CMakeLists.txt
 create mode 100755 llvm/utils/llvm-locstats/llvm-locstats.py
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (120a5e9a745 -> 02c19658ffe)