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from 924f39d [Hexagon] Explicitly reserve aliases of reserved registers new f3a691f AMDGPU: Combine fp16/fp64 subtarget features
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Summary of changes: lib/Target/AMDGPU/AMDGPU.td | 29 +++++++++++++++------- lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 9 +++---- lib/Target/AMDGPU/AMDGPUSubtarget.h | 7 +++--- test/CodeGen/AMDGPU/default-fp-mode.ll | 33 ++++++++++++++++++++++++- test/CodeGen/AMDGPU/fcanonicalize.f16.ll | 20 +++++++-------- test/CodeGen/AMDGPU/fcanonicalize.ll | 4 +-- test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll | 25 ++++++++++++++----- test/CodeGen/AMDGPU/fmuladd.f16.ll | 18 +++++++------- test/CodeGen/AMDGPU/hsa-fp-mode.ll | 8 +++--- test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 8 +++--- test/CodeGen/AMDGPU/v_mac.ll | 7 +++--- test/CodeGen/AMDGPU/v_mac_f16.ll | 8 +++--- test/CodeGen/AMDGPU/v_madak_f16.ll | 4 +-- 13 files changed, 117 insertions(+), 63 deletions(-)