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from 970d21048e1 Update email address in CODE_OWNERS new ce3ccf7b692 [ARM] MVE: support QQPRRegClass and QQQQPRRegClass new ebb2f49e2da AMDGPU/GlobalISel: Select G_BRCOND for vcc new ec01b2964e0 [ARM] Fix MVE_VQxDMLxDH instruction class new 962c2a67ea8 AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
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Summary of changes: lib/Target/AMDGPU/AMDGPUGISel.td | 3 + lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 72 ++++++++++++++-------- lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + lib/Target/ARM/ARMISelLowering.cpp | 5 +- lib/Target/ARM/ARMInstrMVE.td | 15 +++-- test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir | 43 +++++++++++++ .../AMDGPU/GlobalISel/inst-select-brcond.mir | 47 ++++++++++---- 7 files changed, 142 insertions(+), 46 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir