[Tcwg-commits] [llvm] branch stable updated (008f70d -> 3b7d88c)

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from 008f70d Updating branches/google/stable to r277323 adds 16e549f [SimplifyCFG] Range reduce switches adds 1ca1358 [X86] Regenerate a test to pick up shuffle comments that were [...] adds 6c739fb [AVX-512] Fix duplicate column in AVX512 execution dependency [...] adds 3b0f898 [SimplifyCFG] Try and pacify buildbots after r277325 adds a2cd077 [AVX-512] Fix a test missed in r277327. adds deeb6ba [AArch64] Return the correct size for TLSDESC_CALLSEQ adds a77b56f [SimplifyCFG] Fix nasty RAUW bug from r277325 adds 25fd149 Fixed MSVC out of range shift warning adds ec511c2 Fixed test check ordering issue on windows buildbots adds f6cf26b [X86] Use implicit masking of SHLD/SHRD shift double instructions adds 1704eb6 [AMDGPU] refactor DS instruction definitions. NFC. adds a738e21 [mips][fastisel] Correct argument lowering for (f64, f64, i32 [...] adds b1a08ae Add removed inline-assembly-comment test from r277146 adds c765d8530 [Hexagon] Check for offset overflow when reserving scavenging slots adds c54b1ec Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC adds 6687e3a [Verifier] Resume instructions can only be in functions w/ a [...] adds c6005fe Included test for r277360. adds e018866 [CFLAA] Make CFLAnders more conservative with new Values. adds 665f603 [AArch64] Add support for Samsung Exynos M2 (NFC). adds 4df351d [CFLAA] Remove modref queries from CFLAA. adds 16082a3 [Hexagon] Generate vector printing instructions adds 8be735f [DAGCombine] Make sext(setcc) combine respect getBooleanContents adds d794313 [Hexagon] Tidy up some code, NFC adds 71a7b1e Revert r277372, it is causing buildbot failures adds abaa42d [LV] Use getPointerOperand helper where appropriate (NFC) adds 8a44831 [LV] Move isGatherOrScatterLegal into LoopVectorizationLegali [...] adds fa60227 [Profile] IR profiling minor cleanup /nfc adds 9296f21 [Hexagon] Tidy up some code, NFC: reapply r277372 with a fix adds 075c1e2 [ExecutionEngine][MCJIT][Orc] Replace RuntimeDyld::SymbolInfo [...] adds 822ef4e [msf] Teach LLVM to parse a split Fpm. adds 95c3ece Build llvm with ccache if package is present adds 6b6b112 [WebAssembly] Add asm.js-style exception handling support adds 3a6d437 [PM] Port SpeculativeExecution to the new PM adds 4c02879 Simplify some code found when it was moved in r277177 adds f4cfadb [Orc] Fix common symbol support in ORC. adds 23429a5 [WebAssembly] Support CFI for WebAssembly target adds a9ed4cc [ADT] NFC: Generalize GraphTraits requirement of "NodeType *" [...] adds 0e6a15a Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing [...] adds 6fc4119 [MC] Fix handling of end-of-line preprocessor comments adds e9cc165 Fix test from rL277407. adds 8127414 Tie the Verifier class to a Module; NFCI adds e9e0746 CodeExtractor : Add ability to preserve profile data. adds b1fa8fe Revert r277408 and r277407 adds 308cf93 [Verifier] Disallow illegal ptr<->int casts in ConstantExprs adds f21ab36 [Verifier] Improve test coverage for rL277413 adds f29090a Minor code cleanups. NFC. adds 7a4565f [AVX-512] Correct ExeDomain for many AVX-512 instructions. adds c9e6422 [Inliner] Clean up doxygen comments to match modern style. adds 8d6665d [AVX-512] Use SSE_MUL_ITINS_S/SSE_DIV_ITINS_S for the scalar [...] adds a99d4e1 [AVX-512] Mark VADDPS/PD and VMULPS/PD as commutable. This ne [...] adds c2fcbdb AArch64: Fix end iterator dereference adds 5d4d268 AArch64: Add missing branch relaxation tests adds 1cee04d AArch64: BranchRelaxtion cleanups adds 08fb6f0 AArch64: Consolidate branch inversion logic adds 3638aec AArch64: Assert on branch displacement bits adds 0691cf2 [AVX512] Don't use i128 masked gather/scatter/load/store. Do [...] adds df98886 [LoadStoreVectorizer] Don't use a linear walk for an existenc [...] adds 921ae8e [ARM] Some saturation instructions not DSP-only adds 0bdecd2 [mips] Update the P5600 scheduler for isComplete = 1 adds 99853c1 [GlobalISel] Const-ify MachineInstrs passed to MachineLegalizer. adds a124aa1 [GlobalISel] Don't legalize non-generic instructions. adds b484275 [GlobalISel] Don't RegBankSelect target-specific instructions. adds 02c2861 HexagonVectorPrint.cpp: Fix r277370. Don't use getInstrVecReg [...] adds d18c8aa [ARM] Improve smul* and smla* isel for Thumb2 adds d743680 test commit adds 0712e11 Revert rL277454 adds 22973d3 [MC] Fix handling of end-of-line preprocessor comments adds 90b7f56 [LV] Untangle the concepts of uniform and scalar adds 6a35fca [GlobalISel] Require isSSA in GISel passes. adds 3797d93 [CodeGen] Generalize MachineFunctionProperties::print comma h [...] adds e6be5e7 [LVI] NFC. Fix a typo getValueFromFromCondition -> getValueFr [...] adds 143e93e [WebAssembly] Remove a README.txt entry that is now implemented. adds 07d95766 Revert "[MC] Fix handling of end-of-line preprocessor comments" adds 46fe427 [GlobalISel] Add Legalized MachineFunction property. adds a877bb8 [AArch64][GlobalISel] Mark basic binops/memops as legal. adds d170182 [GlobalISel] Set, require, and verify Legalized MF property. adds 155b8551 [LV] Generate both scalar and vector integer induction variables adds 31c3e4f [GlobalISel] Add RegBankSelected MachineFunction property. adds 1f82c34 [GlobalISel] Verify RegBankSelected MF property. adds 7abac75 [GlobalISel] Set and require RegBankSelected MF property. adds e2e5c07 [LVI] NFC. Sink a condition type check from the caller down t [...] adds c32071c Rewrite the use optimizer to be less memory intensive and 50% [...] adds fc114db [GlobalISel] Add Selected MachineFunction property. adds 35426be [GlobalISel] Verify Selected MF property. adds 9618468 [GlobalISel] Set the Selected MF property. adds c1f8f3a MSVC 2013 does not implement C++11 unions properly, so remove [...] adds 93a0b12 [AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests. adds c37e7b9 [MC] Fix Intel Operand assembly parsing for .set ids adds a4e94eb [Hexagon] Improvements to address mode checks in TargetLowering adds aeac124 [Hexagon] Remove unused option adds 1b1291f [Hexagon] Prefer _io over _rr for 64-bit store with constant offset adds 9ce2f98 [AArch64] Remove useless 'import re' from CodeGen lit.local.c [...] adds af5f075 [AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC. adds a846118 AMDGPU: Track physical registers in SIWholeQuadMode adds 0fa8922 Fix handling of end-of-line preprocessor comments Attempt 2 adds bc280d0 [LoopUnroll] Ensure we create prolog loops in simplified form. adds 3db9295 test commit adds 87d2983 AMDGPU: Stay in WQM for non-intrinsic stores adds ee53c92 [IRCE] Preserve DomTree and LCSSA adds 55fcee6 [IRCE] Rename variable; NFC adds 558bab8 Fixes for post-commit review comments on r277480 adds 22b561a AArch64: properly calculate cmpxchg status in FastISel. adds ba9543c [LoopVectorize] Change comment for isOutOfScope in collectLoo [...] adds 23d7717 [NVPTX] remove unnecessary named metadata update that happens [...] adds f8cfb2f [lli] Add the ability for OrcLazyJIT to accept multiple input [...] adds 9ef092d [LoopUnroll] Switch the default value of -unroll-runtime-epil [...] adds 559102f [LoopUnroll] Fix a PowerPC test broken by r277524. adds 8d96db9 [Hexagon] Recognize vcombine in copy propagation adds 9222178 PDB: Mark extended file pages as free by default. adds 35142a9 Move to having a single real instructionClobbersQuery adds 4968ef3 [CFLAA] Be more conservative with values we haven't seen. adds c2a3bce Imported statistics types changes adds 94166e7 AMDGPU: fdiv -1, x -> rcp -x adds 2ca02f6 [sanitizer] Implement a __asan_default_options() equivalent f [...] adds a1c5f9f [InstCombine] replace dyn_casts with matches; NFCI adds d5adfbc More fixes to get good error messages for bad archives. adds d022ddb ARM: only form SMMLS when SUBE flags unused. adds 75834f7 [WebAssembly] Initial SIMD128 support. adds 66c2ec1 [safestack] Layout large allocas first to reduce fragmentation. adds 09f1981 pdbdump: Do not treat stream 0 pages as allocated pages. adds ffc05ed Fix a test for r277545. adds d8ef8b0 [WebAssembly] Remove unnecessary subtarget checks in peephole pass adds f9a5081 [Verifier] Add more tests related to non-integral pointers adds b1f5b4a CommandFlags.h/llc: Move StopAfter/StartBefore options to llc. adds 9d6e4f2 Support for lifetime begin/end markers in the MemorySSA use o [...] adds 1e0bd5f add vector test for icmp+sub adds 2cc035a Add -lowertypetests-bitsets-level to control bitsets generation. adds 4e5f8f5 [Inliner] clang-format various parts of the inliner prior to [...] adds 265028f [MSSA] Fix a caching bug. adds 3d1a470 [PM] Significantly refactor the pass pipeline parsing to be e [...] adds 0f1f982 [PM] Remove the NDEBUG condition around isModulePassName. adds e86c4eb RecordStreamer: handle inline asm "lazy_reference" and mark s [...] adds 8843600 [ADCE] Refactor anticipating new functionality (NFC) adds 26d2b7b [IfConversion] Bugfix: Don't use undef flag while adding use [...] adds d226185 [XRay] Make the xray_instr_map section specification more correct adds 91b6bfa [PM] Add a generic 'repeat N times' pass wrapper to the new p [...] adds 9d383c5 [PM] Add the explicit copy, move, swap, and assignment boiler [...] adds d4bcc6c [PM] Fix a mis-named parameter in parseLoopPass -- the pass m [...] adds 48f2d1d [AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vc [...] adds 5267dec Teach CorrelatedValuePropagation to mark adds as no wrap adds 3a37cd2 [Loop Vectorizer] Move store-predication into its own functio [...] adds 41fc0ec [InstCombine] Add select-bitext.ll tests adds 1345035 add a vector variant of each test adds c3332e4 [Hexagon] Do not check alignment for unsized types in isLegal [...] adds 305565b Disable shrinking of SNaN constants adds e7cee5a Hexagon: Use llvm_unreachable. NFC. adds 17638d0 Revert "Teach CorrelatedValuePropagation to mark adds as no wrap" adds 29b012c [msf] Make FPM reader use MappedBlockStream. adds d619aa8 [ARM] Constant Materialize: imms with specific value can be e [...] adds 406cfb6 [CloneFunction] Don't remove side effecting calls adds 3f2fe11 use local variables; NFC adds 245fddf [CloneFunction] Don't crash if the value map doesn't hold something adds e69cb72 [Hexagon-ish] Add function to print cell map contents in bit tracker adds 38caf19 Adding -verify-machineinstrs option to PowerPC tests adds 8fa25a1 IR: Drop uniquing when an MDNode Value operand is deleted adds 8ff1935 [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors adds a0149b5 Revert "More fixes to get good error messages for bad archives." adds aecf69d [InstCombine] use m_APInt to allow icmp (binop X, Y), C folds [...] adds e5d1578 Reapply "More fixes to get good error messages for bad archives." adds 9b6e245 [X86][SSE] Enable target shuffle combining to combine multipl [...] adds d22c167 [InstCombine] Cleanup select-bitext.ll tests adds 52f0f65 Pass EphValues by const-ref as it is not modified in the callee adds dd5930f [InstCombine] Refactor optimization of zext(or(icmp, icmp)) t [...] adds bfbf2aa I can't reproduce this buildbot failure locally, so temporari [...] adds 94c82b2 [MSSA] Add logic for special handling of atomics/volatiles. adds c6b62aa [InstCombine] use m_APInt to allow icmp eq (srem X, C1), C2 f [...] adds cd112f0 [MSSA] Add special handling for invariant/constant loads. adds 9cdc9da [MSSA] clang-format. NFC. adds 8c1e5c7 Revert "[CloneFunction] Don't remove side effecting calls" adds 3ed1883 opt-bisect-legacy-pass-manager.ll: Test only works with defau [...] adds 5494503 [IndVars] Un-grepify test; NFC adds a9161e1 GVN-hoist: compute MSSA once per function (PR28670) adds c30fea9 GVN-hoist: compute DFS numbers once adds 48b1e39 GVN-hoist: limit the length of dependent instructions adds 0a9d62e [MSSA] Fix a bug in MemorySSA's move ctor. adds 9de637b Revert "[ARM] Constant Materialize: imms with specific value [...] adds dfe91b4 [PPC] Handling CallInst in PPCBoolRetToInt adds b48816b Clean up of libObject/Archive interfaces and change the last [...] adds f29318e [InstCombine] use m_APInt to allow icmp eq (add X, C1), C2 fo [...] adds 8669eef RenameIndependentSubregs: Fix liveness query in rewriteOperands() adds e1dd154 llvm-profdata: Clarify the top level help adds 6775a0d pdbdump: Fix crash bug. adds f935d6f pdbdump: Add a test to verify the result of PDB -> YAML -> PD [...] adds e718640 GVN-hoist: enable by default adds 00b08e7 Make GVN Hoisting obey optnone/bisect. adds 411e616 [PM] Change the name of the repeating utility to something le [...] adds b290294 Revert "GVN-hoist: enable by default" & "Make GVN Hoisting ob [...] adds 8da786c Reinstate "[CloneFunction] Don't remove side effecting calls" adds ad1fd74 Forgot the dyn_cast_or_null intended for r277691. adds e56e9e7 Add popcount(n) == bitsize(n) -> n == -1 transformation. adds 7f30223 Fix intrinsics.ll test adds 579ced7 AMDGPU: Fix a slow test by using basic regalloc adds 499b5cd [XRay] Align entry and return sleds to 2 byte boundaries adds de3bef5 Typo fix in comment. NFC adds 4a2734b [mips] Enable tail calls by default adds 3808648 [X86][SSE] Don't decide when to scalarize CTTZ/CTLZ for perfo [...] adds 1d5ec21 Remove LLVM_ENABLE_LIBCXXABI adds 65787e2 [LLVM-COV]Replace tabs to the space indentations in the HTML [...] adds d81c2d5 [X86][SSE] Add initial costs for vector CTTZ/CTLZ adds 2bdfdf9 [X86] Dropped XOP ctbits checks - they match the AVX checks adds d2c9774 [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instruc [...] adds 17c4ba4 [X86] Heuristic to selectively build Newton-Raphson SQRT estimation adds 14ae142 [Hexagon] Clear kill flags from modified registers in peephol [...] adds 7c37f8e [X86][SSE] Split off shuffle mask canonicalization from lower [...] adds bd9e8a1 [InstCombine] use m_APInt to allow icmp eq (sub C1, X), C2 fo [...] adds 25db202 [mips] Set Personality and LSDA encoding for FreeBSD adds 230bca5 Shamelessly add myself to CREDITS.TXT adds 4ebfadf LoadStoreVectorizer: Remove TargetBaseAlign. Keep alignment f [...] adds 2c8de85 add tests for missing vector folds adds dbed1dc [X86][SSE] Rename target shuffle unary permute matching funct [...] adds 47b6d67 [InstCombine] use m_APInt to allow icmp eq (op X, Y), C folds [...] adds 24c0d9d [Hexagon] Validate register class when doing bit simplification adds df48bd9 [llvm-cov] Add some documentation for the -tab-size option adds 1d5ec70 [WebAssembly] Check return value of getRegForValue in FastISel adds 5c3c157 remove FIXME comments (fixed with r277738) adds 143570a GlobalISel: add code to widen scalar G_ADD adds 75fec5d GlobalISel: also add G_TRUNC to IRTranslator. adds 8c8f13e [InstCombine] use m_APInt to allow icmp eq (or X, C1), C2 fol [...] adds 8acfa94 [macho2yaml] String table can contain null strings adds 837c797 AArch64: don't assume all i128s are BUILD_PAIRs adds 92cd0ec [CodeView] Use llvm::Error instead of std::error_code. adds 77990e6 [OpenCL] Add missing tests for getOCLTypeName adds 0d2bdaf [InstCombine] use m_APInt to allow icmp eq (and X, C1), C2 fo [...] adds 5964d13 [coroutines] Part 4[ab]: Coroutine Devirtualization: Lower co [...] adds 6429bcf [ExecutionEngine] Refactor - Roll JITSymbolFlags functionalit [...] adds ca17b84 GVNHoist: Don't hoist convergent calls adds 5b8a0c5 GlobalISel: refuse to halve size of 1-byte & odd-sized LLTs. adds 6857d7c GlobalISel: implement narrowing for G_ADD. adds c123b93 [Mach0YAML] Change n_type from uint8_t to llvm::yaml::Hex8 adds b7f706d [CloneFunction] Add a testcase for r277691/r277693 adds 3ca2c43 GlobalISel: add support for G_MUL adds df7cecc GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR. adds 74bccc3 Clean up the logic of the Archive::Child::Child() with an ass [...] adds 749f338 [LIT][Darwin] Preload libclang_rt.asan_osx_dynamic.dylib when [...] adds 9615dd0 [InstCombine] use m_APInt to allow icmp eq (mul X, C1), C2 fo [...] adds e788186 [LV, X86] Be more optimistic about vectorizing shifts. adds 05d8fd3 IR: Provide an IRBuilder Inserter that calls a callback after [...] adds 1fc6fa7 GVN-hoist: fix early exit logic adds 412eade GVN-hoist: enable by default adds 4544896 [LIT][Darwin] Change %ld64 to be prefixed with DYLD_INSERT_LIBRARIES adds afba697 InstCombine: Replace some never-null pointers with references. NFC adds 784afcb InstCombine: Clean up some trailing whitespace. NFC adds fd14e43 [InstCombine] try to fold (select C, (sext A), B) into logical ops adds 632e6aa [PowerPC] fix passing long double arguments to function (soft-float) adds eca7f45 Reapply r276973 "Adjust Registry interface to not require plu [...] adds 319f67f [X86][SSE] Added target shuffle combine binary compute matchi [...] adds 14f1319 Add a missing backslash to my previous commit adds eb34f44 Reformat. adds d55759c LLLexer.cpp: Avoid using BitsToDouble() to preserve SNaN like [...] adds 0d58c98 [X86][SSE] Consistently use the target shuffle root value typ [...] adds ebdd31d testing commit access adds 4a1befb [X86][SSE] Update the the target shuffle matches to use the e [...] adds 1c1a946 reduce tests; auto-generate checks adds 904a536 [SimplifyCFG] Make range reduction code deterministic. adds 36ae0d9 Actually, r277337 was fine. Just kill the DAGs that made the [...] adds 348f66d [SystemZ] Add missing classes and instructions adds 1025a61 [PowerPC] Wrong fast-isel codegen for VSX floating-point loads adds e648a06 opt: Adding -O0 to opt tool adds 3c7b828 Fix TargetParser unit tests for ARM / AArch64. adds 9c9f23f Fix gdb pretty printers to work with Python 3. adds 1249b27 GlobalISel: IRTranslate PHI instructions adds bdea192 [X86][SSE] Add initial support for 2 input target shuffle combining. adds 47dc780 GlobalISel: clear pending phis after MachineFunction translated adds 9fb630e Do not assign new discriminator for all intrinsics. adds cedb0b6 Add the first of what will be a long line of additional error [...] adds cd923bb [ORC] Change LogicalDylib::LogicalModuleHandle from an iterat [...] adds a2ef549 [SCEV] Don't infinitely recurse on unreachable code adds fcb7a4a [AutoFDO] Fix handling of empty profiles adds 6b9dec8 fix documentation comments; NFC adds c5201e3 [ConstantFolding] Don't create illegal (non-integral) inttoptrs adds 853b86f [ADCE] Refactoring for new functionality (NFC) adds 51ae50f WholeProgramDevirt: print remarks with devirtualized method names. adds 506c14d Update outdated comments in the new PM internals (NFC) adds 4613003 [sanitizers] trace buffer API to use user-allocated buffer. adds ffccedb Replace hot-callsite based heuristic to use its own threshold [...] adds 549a67c [SCEV] Un-grep'ify tests; NFC adds f77a198 Remove cold callsite heuristic that is not necessary because [...] adds 927cc57 [FlattenCFG] Simplify + remove unused variable. NFCI. adds 82b9d1c [ARM] Constant Materialize: imms with specific value can be e [...] adds 716b378 AMDGPU/SI: Increase SGPR limit to 96 on Tonga/Iceland adds a377039 Make YAML support SmallVector adds 3483f21 [CodeView] Decouple record deserialization from visitor dispatch. adds f5e11c4 Rewrite domination verifier to handle local domination as well. adds b081e9c [MSSA] Match assert vs llvm_unreachable style in verification [...] adds 029b060 PowerPC: Add a triple to this test adds d1226ba Fix non portable include path. adds 41d635e [LoopSimplify] Fix updating LCSSA after separating nested loops. adds 4aa9fee CodeView: Remove an unused variable adds 466b4f2 [MSSA] Use depth first iterator instead of custom version. adds 5d9e141 Revert "Make YAML support SmallVector" adds 4b55580 [InstCombine] refactor ctlz/cttz folds (NFCI) adds ab23f22 Resubmit "Make YAML support SmallVector" adds 265e61a [IRCE] Preserve loop-simplify form adds 9c82886 [IRCE] Remove unused headers; NFC adds faa5bfd Fix a -Wunused-const-variable due to a bug in clang. adds 38365da [ORC] Add (partial) weak symbol support to the CompileOnDeman [...] adds 392ab36 Revert "[LoopSimplify] Fix updating LCSSA after separating ne [...] adds f655859 IfConversion: factor out 2 functions to skip debug instrs. NFC adds 7926289 IfConversion: Document countDuplicatedInstructions. NFC adds e0b41b5 IfConverter: Split ScanInstructions into 2 functions. adds d9a9f7d CodeGen: If Convert blocks that would form a diamond when tai [...] adds 84f6a48 Revert r277896. adds fa28832 Part 4c: Coroutine Devirtualization: Devirtualize coro.resume [...] adds 3f4f336 Revert "(refs/bisect/bad) GVN-hoist: enable by default" adds 9da24c7 [InstCombine] Don't coerce non-integral pointers to integers adds 8682b37 [ADT] Make the triple test 1000x faster through more focused [...] adds 470962f [CallGraphSCCPass] Use an ArrayRef instead of a pair of iterators adds 2982845 [ValueTracking] Teach computeKnownBits about [su]min/max adds bc3aa5c [CodeGen] Fix a -Wdocumentation warning adds 284030a Move helpers into anonymous namespaces. NFC. adds 0f888a7 [X86][SSE] Add 2 input shuffle support to matchBinaryVectorShuffle adds fb0b339 [LoadCombine] Simplify code with a brace init. NFC. adds a44f29c [Inliner] Use function_ref for functors which are never taken [...] adds 599a666 [ARM] Don't copy MCInsts in loop. NFC. adds 5cd1324 [X86][SSE] Regenerate SSE1 shuffle tests adds 7e8350b [libfuzzer] do not warn about missing pcbuffer functions: the [...] adds 39e5fc9 [X86][SSE] Enable commutation between MOVHLPS and UNPCKHPD adds 372fbdf [X86] Add VRCPSSr_Int, VRSQRTSSr_Int, VSQRTSSr_Int, and VSQRT [...] adds 3fe381a [AVX-512] Add AVX512 run line to a test and re-generate the c [...] adds 7c9196a [AVX-512] Add AVX-512 scalar CVT instructions to hasUndefRegUpdate. adds 6bb60d2 [AVX-512] Add SQRT/RCP14/RNDSCALE to hasUndefRegUpdate. adds 2007f37 [Coroutines] Part 5: Add CGSCC restart trigger adds 1a066c4 [Coroutines] Passify the build bots. Remove restart-trigger.l [...] adds 303ae67 CoroSplit: Squash unused variable FnTrigger warning in NDEBUG adds 2e5c533 [X86][AVX2] Improve sign/zero extension on AVX2 targets adds 1efe1f7 [libFuzzer] don't print bogus error message adds 3aa06ba [libFuzzer] make libFuzzer work with a bit older clang versions adds 9350f36 [ORC] Re-apply r277896, removing bogus triples and datalayout [...] adds fdf5e1e [RuntimeDyld] Replace manual flag checks with JITSymbolFlags: [...] adds 5ca8eaf [RuntimeDyld] Remove symbol that is unused as of r277943. adds 5a98b58 [ExecutionEngine][RuntimeDyld] Move JITSymbol from ExecutionE [...] adds 0f98731 Revert "Revert "[LoopSimplify] Fix updating LCSSA after separ [...] adds 8b05589 [X86] Simplify a shuffle mask copy. NFC adds 1048e17 [AVX-512] Add andnps/andnpd to the avx512vl stack folding test. adds facbf76 [X86] Add commutable floating point max/min instructions to t [...] adds 0c8a344 [InstCombine] Infer inbounds on geps of allocas adds 2a07d9f [InstSimplify] Try hard to simplify pointer comparisons adds 7428509 [InstSimplify] Fold gep (gep V, C), (sub 0, V) to C adds 8e53235 AVX-512: Added a test for cmp intrinsics adds edf4139 [X86][AVX512] Add sext/zext to 512-bit vector tests adds 751a136 [X86][AVX512BW] Add sext/zext AVX512BW 512-bit vector tests adds 661baf2 AVX-512: Changed lowering of BITCAST between i1 vectors and i [...] adds 1223b84 [X86] lowerVectorShuffle - ensure that undefined mask element [...] adds 778de48 [AVX-512] Add EVEX encoded floating point MAX/MIN instruction [...] adds 1a28a71 [AVX-512] Add 512-bit logical operations to load folding tabl [...] adds 29b5c03 Revert r277905, it caused PR28894 adds c850b51 [SLC] Emit an intrinsic instead of a libcall for pow. adds 44aa102 [AVX-512] Improve lowering of inserting a single element into [...] adds 0ba29b6 [SROA] Fix crash with lifetime intrinsic partially covering alloca. adds 87b8240 [SimplifyLibCalls] Emit sqrt intrinsic instead of a libcall. adds 4a8f62e [MC] Delete use of *structors_used. adds 97b394f [JumpThreading] Fix handling of aliasing metadata. adds cd3dcaa [MSSA] Fix PR28880 by fixing use optimizer's lower bound trac [...] adds 95c2919 [PM] Function-level TLI is also immutable. adds d4b4a02 [PM] Invalidate CallGraphAnalysis because it holds AssertingVH adds ec1bd22 [PM] BasicAA needs to be invalidated since it holds pointers [...] adds 6f2a8d3 [PM] More workaround for PR28400 adds 6d4afae Add some comments linking back to PR28400. adds b387189 [SelectionDAG] Refactor visitInlineAsm a bit. NFCI. adds 0074173 [mips][ias] Fix all the hacks related to MIPS-specific unary [...] adds 0985f50 Revert r277988: [mips][ias] Fix all the hacks related to MIPS [...] adds 4185a58 [X86][SSE] Assert if the shuffle mask indices are not -1 or w [...] adds b1fa576 Fix Wdocumentation unknown parameter warning adds 7dd6fd6 Re-commit r277988: [mips][ias] Fix all the hacks related to M [...] adds 1eae80e [AArch64] PR28877: Don't assume we're running after legalizat [...] adds c14eb9a [LVI] NFC. Extract LHS, RHS, Predicate locals in getValueFrom [...] adds b827587 [LVI] NFC. Rename confusing local NegOffset to Offset adds fe11e98 [LVI] NFC. On the fast dest path use inverse predicate instea [...] adds 9ecdaba GVN-hoist: enable by default adds 43949cd Revert r2277979. adds c6b5e88 [SystemZ] Add support for the .insn directive adds b85d8f4 [ARM] Add support for embedded position-independent code adds eee9c60 [MemorySSA] Ensure address stability of MemorySSA object. adds cf83621 [X86] Improve code size on X86 segment moves adds 32217d6 [BuildingAJIT] Fix a couple of typos in the Chapter 3 draft. adds c97b57b Re-add SystemZ SNaN test adds 555c63f [MemorySSA] Fix windows build breakage caused by r278028 adds a27deb3 RefreshCallGraph does not modify the SCC, adding "const" to m [...] adds 363a89e [LoopUnroll] Simplify loops created by unrolling. adds e19c246 [Hexagon] Add pattern for 64-bit mulhs adds d2aa4c0 [MemorySSA] Fix windows build breakage caused by r278028 (take 2) adds cedd288 [X86] Support the "ms-hotpatch" attribute. adds 5090f4a InstCombine: Remove a redundant #ifdef NDEBUG. NFC adds d77fdcb Revert "[X86] Support the "ms-hotpatch" attribute." adds fbda701 [RuntimeDyld][Orc][MCJIT] Add partial weak-symbol support to [...] adds 2ea3c70 Do not ignore SizeOfOptionalHeader in COFF header even if PE [...] adds 06c9df2 Revert r278065 while I investigate some build-bot breakage. adds 922b42a Revert "Do not ignore SizeOfOptionalHeader in COFF header eve [...] adds d55ce11 [WebAssembly] Fix CFI index to account for padding nullptr function adds f7c3c99 [x86] split combineVSelectWithAllOnesOrZeros into a helper fu [...] adds b79146f CodeView: extract the OMF Directory Header adds 20b343c Consistently use FunctionAnalysisManager adds 2fb9a98 Consistently use ModuleAnalysisManager adds a4f9d70 Consistently use LoopAnalysisManager adds 2058f10 Consistently use CGSCCAnalysisManager adds e7c6190 [WebAssembly] Fix bugs in WebAssemblyLowerEmscriptenExceptions pass adds 9a82d30 X86InstrInfo: Update liveness in classifyLea() adds 4f5ecb3 [X86] Remove unnecessary bitcast from the front of AVX1Only 2 [...] adds abbe1e8 [X86] Cleanup patterns for AVX/SSE for PS operations. Always [...] adds c59de2e [X86] Remove the Fv packed logical operation alias instructio [...] adds fa0ea29 [AVX-512] Add support for execution domain switching masked l [...] adds 380a420 [X86] Reduce duplicated code in the execution domain lookup f [...] adds 3d7517b [LVI] NFC. Fix a typo Bofore -> Before adds ba77973 [X86][SSE] Fix memory folding of (v)roundsd / (v)roundss adds 7a7dcf6 Teach CorrelatedValuePropagation to mark adds as no wrap adds 76ebea1 [modules]Add missing include. adds a552eea Revert 278107 which causes buildbot failures and in addition [...] adds 8b56a91 [XRay] Test for xray_instr_map in object file. (NFC) adds 3928702 [X86][XOP] Add support for combining target shuffles to VPPERM adds 1b988ac AVX-512: A new test for FMA intrinsic adds 5a9fa77 Add `#ifdef __cplusplus` around `extern "C"` in Compiler.h. NFC. adds 04876e5 [X86][XOP] Add support for combining target shuffles to VPERM [...] adds 861388b [LVI] Make LVI smarter about comparisons with non-constants adds f78dbb9 [Profile] turn off verbose warnings by default adds 9c5bb05 add tests for missing vector icmp folds adds 7e67a70 regenerate checks adds 7f4d342 update to use FileCheck and auto-generate checks adds 7734cde add tests for missing vector icmp folds adds a8ca6b6 test-release.sh: Drop autoconf support adds 9abb949 auto-generate checks adds 1019cf0 auto-generate checks adds cfc3af0 auto-generate checks adds 9cd4907 [AliasAnalysis] Treat invariant.start as read-memory adds 4cdc985 [DAGCombiner] Better support for shifting large value type by [...] adds 543ae79 [X86] Don't model UD2/UD2B as a terminator adds c93602e [vim] Update the llvm.vim syntax file adds 04d404b Re-apply r278065 (Weak symbol support in RuntimeDyld) with a [...] adds bf1a5ce update to use FileCheck and auto-generate checks adds 17a2f3f [llvm-cov] Swapped the line and count columns. adds f69ccb7 [EarlyCSE] Teach about CSE'ing over invariant.start intrinsics adds b2b51a4 regenerate checks and remove 'opt' run dependency adds 2962e3e [ADT] Change iterator_adaptor_base's default template argumen [...] adds 6aabb5f Without explicitly including <string>, I'm getting an error o [...] adds 8b93225 Recommit "Use ValueOffsetPair to enhance value reuse during S [...] adds fc25cfb Fix the runtime error caused by "Use ValueOffsetPair to enhan [...] adds d5ab2f8 [ExecutionEngine] Disable weak symbol tests for COFF. adds c14478f add test cases for missed vselect optimizations (PR28895) adds c1cf490 GlobalISel: first translation support for Constants. adds a533def Add a platform independent version of __PRETTY_FUNCTION__. adds 4dd8705 [WebAssembly] Add -emscripten-cxx-exceptions-whitelist option adds 6c6978f [ValueTracking] Improve ValueTracking on left shift with nsw flag adds 4b47096 [LoopSimplify] Rebuild LCSSA for the inner loop after separat [...] adds 84aa82e GlobalISel: support 'undef' constant. adds dc89d2a Make LLVM_PRETTY_FUNCTION support __func__. adds 5987faf [IR] Remove some unused #includes (NFC) adds 1e3f45d [scudo] Documentation update for Scudo, from https://reviews. [...] adds 37a4ac8 [Inliner,OptDiag] Add hotness attribute to opt diagnostics adds c70a5f4 [OptDiag] Add class Doxygen comment adds 74dacfe Do not directly use inline threshold cl options in cost analysis. adds 1ea5b39 [SimplifyLibCalls] Restore the old behaviour, emit a libcall. adds 430591f [x86] Fix a bug in the auto-upgrade from r276416 where we fai [...] adds 822ef54 [ARM] Improve sxta{b|h} and uxta{b|h} tests adds d8d5e79 [DAGCombine] Avoid INSERT_SUBVECTOR reinsertions (PR28678) adds 2fe1508 Regenerate test adds 3206f9e [X86][SSE] Regenerate SSE1 tests adds a223dd9 [X86][SSE] Reorder shuffle mask undef helper predicates. NFCI adds 06ab33e [LVI] Relax the assertion about LVILatticeVal type in getCons [...] adds 607fac7 [X86][SSE] Only treat SM_SentinelUndef as UNDEF in shuffle ma [...] adds f7b6243 Teach CorrelatedValuePropagation to mark adds as no wrap adds 5e9462a [LVI] NFC. Make getValueFromCondition return LVILatticeValue [...] adds ce8c913 Add a test case for r278217 "[LVI] Relax the assertion about [...] adds 6e8b851 [X86][SSE] Add support for combining target shuffles to MOVSS/MOVSD adds 680006e use different comparison predicates for better test coverage adds 72349b2 [LVI] Handle conditions in the form of (cond1 && cond2) adds de70ff2 [X86][SSE] Regenerate vector shift lowering tests adds c038ba9 [X86][XOP] Tweak vpermil2pd test to stop it being combined away adds e9a0993 [Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32 adds 94826b8 [Hexagon] Delete HexagonSelectCCInfo.td adds 9cba8e9 Fix build break of VS 2013 debug builds adds bd0032e [Coroutines] Part 6: Elide dynamic allocation of a coroutine [...] adds 3b54bd1 [Hexagon] Use integer instructions for floating point immediates adds 6b89c90 GlobalISel: avoid inserting redundant COPYs for bitcasts. adds d5551e6 GlobalISel: fixup copy/paste comment error adds c047ae7 [Hexagon] Fix table-gen decode conflict warnings for CONST32/64 adds 9a1106c Fix LCSSA increased compile time adds d8f5868 [ADT] Add make_scope_exit(). adds 570eecd [Hexagon] Add extra patterns for single-precision min/max ins [...] adds 3072594 [Hexagon] Simplify the SplitConst32/64 pass adds 5ae015e TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG adds bb35e90 [ADT] Removed synthesized constructor introduced in r278251, [...] adds 4425f12 [X86][SSE] Dropped blend(insertps(x,y),zero) combine - this i [...] adds c04b985 Codegen: Tail Merge: Be less aggressive with special cases. adds 089ce6a [Hexagon] Remove unused variants of LO/HI instructions adds 72626e1 [ValueTracking] An improvement to IR ValueTracking on Non-neg [...] adds be7124c LiveIntervalAnalysis: fix a crash in repairOldRegInRange adds 9c0625f [IndVarSimplify] Eliminate zext of a signed IV when the IV is [...] adds 944f969 [x86, AVX] allow FP vector select folding to bitwise logic op [...] adds d3396f4 [sancov] Run more sancov tests on non-x86-Linux machines adds 898f0e0 AMDGPU: Use CreateStackObject instead of CreateSpillStackObject adds 34c6b12 AMDGPU: Change insertion point of si_mask_branch adds 0576028 AMDGPU: Remove unnecessary cast adds 054b698 AMDGPU: Remove empty file comment adds a9d5cfb AMDGPU: Set sizes on control flow pseudos adds 7616e5d AMDGPU: s_setpc_b64 should be an indirect branch adds 9715a2d Fix UB in APInt::ashr adds 455668a [sancov] Port sancov -print-coverage-pcs to COFF adds de2cc1c Disable sancov tests failing due to apparent endianness issues adds 3da1bfb CodeGen: If Convert blocks that would form a diamond when tai [...] adds 0d1c7a1 Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough. adds e70f4f7 Changed sign of LastCallToStaticBouns adds 4a0373d AMDGPU/SI: Implement amdgcn image intrinsics with sampler adds 3b3a95a GlobalISel: implement simple function calls on AArch64. adds be91a8e [LangRef] Fix formatting (no semantic change) adds 9aa5ced GlobalISel: add tests forgotten in r278293. adds 006d0e7 [ADT] Move LLVM_ATTRIBUTE_UNUSED_RESULT to the function, othe [...] adds 4974668 GlobalISel: support same ConstantExprs as Instructions. adds 50b70a6 [MachOYAML] Don't output empty ExportTrie adds 4971243 [Statepoints] Minor cosmetic change; NFC adds a31d08b Make more fields of InlineParams Optional. adds a01f239 [WebAssembly] Cleanup trailing whitespace adds b894886 [Profile] improve warning control option adds bc13ca6 [AVX-512] Fix the 128-bit and 256-bit nontemporal load patter [...] adds e0ce251 [AVX-512] Add patterns to allow EVEX encoded stores of v16i16 [...] adds d91ccf5 [AVX-512] Promote 512-bit integer loads to v8i64 similar to w [...] adds 9c53423 [Debug Info] Added a LIT test that covers the fix committed i [...] adds ac9ca3b Avoid false dependencies of undef machine operands adds 33ca8b8 [AVX512] Fix extractelement i1 lowering. The previous impleme [...] adds 452ae8e Fixed VS2015 (Update 3) warning - differing const/volatile qu [...] adds 9fd9770 Resolution-based LTO API. adds 6f0ab85 Revert "Resolution-based LTO API." adds 3876e2e [AMDGPU] fix failure on printing of non-existing instruction [...] adds 543fef7 Extend trip count instead of truncating IV in LFTR, when legal adds d27913e Revert "[AMDGPU] fix failure on printing of non-existing inst [...] adds d418a91 revert 278334 adds 2d320e5 Restore "Resolution-based LTO API." adds 4636b0c getParent()->getParent() == getFunction() ; NFC adds 583b94d use auto* with dyn_cast ; NFC adds 31aaf81 Fix bot failure from r278338 due to missing dependences adds 16fc409 fix comment; NFC adds 67914cb [SLP] Make RecursionMaxDepth a command line option (NFC) adds 91c138b CodeGen: Check for a terminator in llvm::getFuncletMembership adds 9040acb IR: Don't cast the end iterator to Instruction* adds 8949cc2 X86: Use operator lookup for operator==, NFC adds 3f8d4e3 [MCJIT] Improve documentation and error handling for MCJIT::r [...] adds c4513c6 More missing llvm-lto2 dependencies adds a4d7181 Remove FIXME about asserting on the end iterator adds f1ef4a3 GlobalISel: clear vreg mapping after translating each function adds a6a3520 Add (hopefully last) remaining missing dependences to llvm-lto2 adds 9bcebab AMDGPU : Add LLVM intrinsics for SAD related instructions. adds aba9f58 Hexagon: Avoid dereferencing end() in HexagonCopyToCombine::f [...] adds 523717c AMDGPU : Fix SAD related instruction LIT tests function attti [...] adds ece2d8b AMDGPU: Remove unused tracking of flat instructions adds f29c37a AMDGPU: Remove custom getSubReg adds 7a1d8e4 Add move ops to satisfy MSVC. adds c986ab2 Fix some Clang-tidy modernize and Include What You Use warnings. adds e99815b [AliasSetTracker] Delete dead code adds 9ffb824 AArch64: Assert on analyzeBranch failing adds d751c97 AMDGPU: Fix crashes on memory functions adds f1860b7 Make TwoAddressInstructionPass::rescheduleMIBelowKill subreg-aware adds fbdf373 Improve virtual register handling when computing debug information adds cf9748d [Hexagon] Skip byval arguments when checking parameter attributes adds 2d003b3 Add a new method to create SimpleInliner instance and make pr [...] adds 2f5689f Target independent codesize heuristics for Loop Idiom Recognition adds 847ddff Test commit adds 3c99845 If-conversion incorrectly calculates liveness of redefined registers adds 158f898 Remove the restriction that MachineSinking is now stopped by [...] adds dcedd3b WholeProgramDevirt: generate more detailed and accurate remarks. adds 50f0fc5 [Hexagon] Standardize "select" pseudo-instructions adds 44cd439 AMDGPU: Prune includes adds eeb1d4f CodeGen: Avoid dereferencing end() in MachineScheduler adds 4c26d96 [ADT] Add relation operators for Optional adds 828990c Fix PR 28933 adds da956b9 Revert rL278384 which caused several buildbot failures (like [...] adds 2daf966 AMDGPU : Add intrinsic for instruction v_cvt_pk_u8_f32 adds c9f97fc Move GVNHoist tests into their own directory since it is a se [...] adds fe3eab2 Fix type truncation warnings adds 94c692e GlobalISel: support zext & sext during translation phase. adds 814d8b3 GlobalISel: add translation support for shift operations. adds 789ee9f Remove empty file left by partial reversion. adds 510ec20 [SCEV] Update interface to handle SCEVExpander insert point motion. adds 2e8e1e6 AMDGPU: Remove unused tablegen utilities adds 4df8156 [vim] Add more attributes to llvm.vim adds 4110644 [Hexagon] Allow non-returning calls in hardware loops adds dc9c737 Use range algorithms instead of unpacking begin/end adds 417fcec [MSSA] Use is_contained adds f11cae6 Extend trip count instead of truncating IV in LFTR, when legal adds d4a60d0 GlobalISel: support 'null' constant in translation. adds 837032f Re-commit r278066: Do not ignore SizeOfOptionalHeader in COFF [...] adds 5747888 X86-FMA3: Implemented commute transformation for EVEX/AVX512 [...] adds fb2a7f9 Don't import variadic functions adds 975248e Use the range variant of find instead of unpacking begin/end adds ae48001 Remove unnecessary extra version of isValidAssumeForContext. NFC. adds 124c0a4 Fix typos /NFC adds 161e82b [ADT] Migrate DepthFirstIterator to use NodeRef adds b9ecebc Add comment /NFC adds 88add6b WholeProgramDevirt: fix access to a non-initialized field. adds b0353c6 Use the range variant of find_if instead of unpacking begin/end adds 2d34392 Refactor isValidAssumeForContext to reduce duplication and in [...] adds 35ff6f0 [DSE] Don't remove stores made live by a call which unwinds. adds d79f1f1 WholeProgramDevirt: initialize WasDevirt in all constructors. adds df403b3 [BranchFolding] Restrict tail merging loop blocks after MBP adds 31333a7 Recommit 'Remove the restriction that MachineSinking is now s [...] adds 369a632 ADT: Add ilist_iterator conversions to/from ilist_node adds 2d62ce6 Use the range variant of find/find_if instead of unpacking begin/end adds 33ebfce Use the range variant of count_if instead of unpacking begin/end adds 5d08e37 Use the range variant of remove_if instead of unpacking begin/end adds ac0eb3d Use the range variant of transform instead of unpacking begin/end adds 7e45eb5 Use the range variant of transform instead of unpacking begin/end adds 21bcd75 ADT: Remove all ilist_iterator => pointer casts, NFC adds b6ae34d [Coroutines]: Part6b: Add coro.id intrinsic. adds 2790d23 Revert "[BranchFolding] Restrict tail merging loop blocks after MBP" adds 94e4f70 [Coroutines] Move class into anonymous namespace. adds 85f3311 [Sparc][Leon] Errata fixes for various errata in different ve [...] adds 6af6409 [Sparc][Leon] Missed resetting option flags from check-in 278489. adds a6da8aa [LVI] Handle any predicate in comparisons like icmp <pred> (a [...] adds f811c0f [X86][SSE] Fixed PALIGNR target shuffle decode adds a4d5334 [Webassembly] disable unstable test. adds 38a5bdc [LVI] Take range metadata into account while calculating icmp [...] adds a8e8317 [Hexagon] Treat non-returning indirect calls as scheduling bo [...] adds 4502b2e [Hexagon] Standardize pseudo-instructions for calls and returns adds 3951c48 [X86][SSE] Add support for combining target shuffles to PSLLD [...] adds 3143f33 [PM] Port ModuleSummaryIndex analysis to new pass manager adds 7be1759 [PM] Port NameAnonFunction pass to new pass manager adds 396941b Revert "[Sparc] Leon errata fix passes." ...and the two follo [...] adds 18ff139 Fix type to avoid problems on 32-bit builds adds 3e97be2 ADT: Share code for embedded sentinel traits, NFC adds e18f64c [LVI] Fix potential memory corruption in getValueFromCondition adds 67a14c0 [AArch64] Re-factor code shared by AArch64LoadStoreOpt and AA [...] adds c6f72e4 Add move ops to satisfy MSVC. adds e5ae839 [LVI] Take guards into account adds a3c0803 [BasicAA] Avoid calling GetUnderlyingObject, when the result [...] adds 0ac09cb [x86] X86ISelLowering zext(add_nuw(x, C)) --> add(zext(x), C_zext) adds 126e4c2 Fine tuning of sample profile propagation algorithm. adds a6bfa5e constify InstCombine::foldAllocaCmp. NFC. adds 69f0407 [PM] Port LowerInvoke to the new pass manager adds 6394023 ADT: Remove the ilist_nextprev_traits customization point adds fa2e422 Remove whitespace adds a33b92e Try to appease win7 bots after r278532 by cleaning up type trait adds f74d382 Hide type trait from r278532 from MSVC adds 3d3a4a4 ADT: Remove stale header comments about next/prev after r278532 adds a3e4fd5 [LibFuzzer] Fix `-jobs=<N>` where <N> > 1 and the number of w [...] adds c94acb0 [WebAssembly] Plug MachineMemOperand leaks. adds ea5bf34 [PPC] Memoize getValueBits. NFC. adds fd3780b [sancov] MachO indirect symbols support. adds f5a4670 [sancov] test file cleanup adds 296471b Next set of additional error checks for invalid Mach-O files. adds 718ae23 Remove autoconf references from LICENSE.TXT adds 12a703d [AArch64LoadStoreOpt] Handle offsets correctly for post-index [...] adds a7eb97f [AArch64] Registering default MCInstrAnalysis adds 7c00a88 [AArch64LoadStoreOptimizer] Check aliasing correctly when cre [...] adds 45edca1 [libFuzzer] fix typo in docs adds 9d016ef [Hexagon] Cleanup and standardize vector load/store pseudo in [...] adds 43fb293 Fixed typo. adds 5385053 [PM] BitcodeWriterPass should derive from PassInfoMixin adds d20e86c gold: add a cast to appease std::max NFC adds e10646b [NVPTX] Use untyped (.b) integer registers in PTX. adds e657d43 [ADT] Add filter_iterator for filtering elements adds fe45d14 Add support to paternmatch for simple const Value cases. adds 2a23370 [Inliner] Don't treat inalloca allocas as static adds 2b6735e X86: Stop dereferencing end() in X86FrameLowering::emitEpilogue adds 9e8ae09 [LoopVectorize] Detect loops in the innermost loop before cre [...] adds 5122298 Avoid accessing LLVM/DWARF register mappings if undefined adds 881b0b2 Reapply [BranchFolding] Restrict tail merging loop blocks after MBP adds e96662e [WebAssembly] Re-enable disabled debug value test adds be1a4e1 X86: Fix another dereferenced end() iterator after r278532 adds 18c3af1 Minor comment fix ("generate" --> "generates"). adds 50724be [LSV] Use OrderedBasicBlock instead of rolling it ourselves. NFC adds 06c1127 [LSV] Use a set rather than an ArraySlice at the end of getVe [...] adds afcd057 [libFuzzer] mention one more trophie in LLVM adds 82d16ec Fix some Clang-tidy modernize-use-using and Include What You [...] adds 5b64093 [IndVars] Ignore (s|z)exts that don't extend the induction variable adds 1231164 Constify ValueTracking. NFC. adds 46b81ba Fix more dereferenced end() iterators after r278532 adds 129b27a AMDGPU/R600: Remove macros adds b24aaff AMDGPU: Fix missing test for addressing mode with odd offsets adds e8fc9abe AMDGPU: Fix not estimating MBB operand sizes correctly adds f970c6e [PM] Port LoopDataPrefetch to new pass manager adds e95ebf5 [AVX-512] Add patterns to support VZEXT_MOVL from 512-bit vec [...] adds 7efbb99 [AVX-512] Remove an AddedComplexity that was prioritizing bas [...] adds 1e8f440 [X86] Remove patterns for (vzmovl (insert_subvector undef, (s [...] adds c078bbe [AVX-512] Add commutable flags to 132 form FMA3 instructions. adds 780d202 [AVX-512] Add isCommutable to scalar FMA3 instructions. adds c819da3 [X86] Add a check of isCommutable at the top of X86InstrInfo: [...] adds 3ee4558 Test commit adds b0e01f0 [x86] add tests to show missed 64-bit immediate merging adds 762481d [ADT] Add a reserve method to DenseSet as well as an insert() [...] adds 5ac928f Add missing REQUIRES in sancov/print_coverage_pcs.test: it re [...] adds 663c3ce Limit DenseMap::setNumEntries input to 1<<31, in accordance w [...] adds 80f0510 Revert "[ADT] Add a reserve method to DenseSet as well as an [...] adds 568382f [ADT] Add a reserve() method to DenseSet as well as an insert [...] adds 81232a9 [IRCE] Use range-for; NFC adds d2e55b6 [IRCE] Use dyn_cast instead of explicit isa/cast; NFC adds 2eb84a5 Revert "Invariant start/end intrinsics overloaded for address space" adds 804c815 Revert "Revert "Invariant start/end intrinsics overloaded for [...] adds c5432bd Fix bitcode auto-upgrade when using bitcode lazy loading adds c56bea6 [IRCE] Be resilient in the face of non-simplified loops adds 3e63425 [IRCE] Fix test case; NFC adds 4510860 Revert "Fix bitcode auto-upgrade when using bitcode lazy loading" adds 26d2a23 Fix unsupported relocation type R_HEX_6_X' for symbol .rodata adds 2c1c0b4 Fix bitcode auto-upgrade when using bitcode lazy loading adds abf7d54 [IRCE] Add better DEBUG diagnostic; NFC adds 300cd13 [IRCE] Don't iterate on loops that were cloned out adds 39b5545 [IRCE] Create llvm::Loop instances for cloned out loops adds d330744 [IRCE] Change variable grouping; NFC adds 281da4f Revert "Codegen: Don't tail-duplicate blocks with un-analyzab [...] adds 12fc232 Revert "CodeGen: If Convert blocks that would form a diamond [...] adds 5724bf57 Revert "gold: add a cast to appease std::max NFC" adds bf57b01 [AVX512] Fix insertelement i1 lowering. 1. Use shuffle to ins [...] adds 96cefd6 autogenerate checks adds 1a3669b [AVX512] Fix VFPCLASSSD/VFPCLASSSS intrinsic lowering. The i1 [...] adds 4889469 [AVX-512] Add masked logical operations to memory folding tables. adds 8cbb186 [AVX-512] Add masked commutable floating point max/min instru [...] adds 98df2b1 [AVX-512] Mark VPMADDWD as commutable to match SSE/AVX version. adds 3bf3ce9 [InstCombine] add test for missing vector icmp fold adds 4865e7b [InstCombine] add test for missing vector icmp fold adds 6eea5bd [InstCombine] add tests for missing vector icmp folds adds 9e679db [InstCombine] remove unnecessary function attributes from tests adds 411c4db [InstCombine] add tests for missing vector icmp folds adds bc87c37 [InstCombine] add test for missing vector icmp fold adds aafbbf8 [InstCombine] add test for potentially missing vector icmp fold adds 93591d1 [InstCombine] add tests for vector icmp folds adds b3d14d2 [InstCombine] add test for missing vector icmp fold adds 6bd5c84 [ScopedNoAliasAA] Remove an unneccesary set adds 28873d7 Revert "[ScopedNoAliasAA] Remove an unneccesary set" adds a727375 [ScopedNoAliasAA] Replace !ScopeNodes.size() with ScopeNodes.empty() adds 24f7cd8 [ScopedNoAliasAA] Only collect noalias nodes if we have alias [...] adds 937229d [ScopedNoAliasAA] collectMDInDomain should be a free function adds ed1f4b6 [X86] X86ISD::FANDN is not commutative or associative. adds d1a8c19 [X86] Mark some of the X86 SDNodes as commutative. adds 24088ba [X86] PADDUSB/W instructions should be commutable. adds bd7c3fb [LSR] Don't try and create post-inc expressions on non-rotated loops adds 91c19fb [Thumb] Validate branch target for CBZ/CBNZ instructions. adds 7bc6001 [SimplifyCFG] Rewrite SinkThenElseCodeToEnd adds 47a3de7 MachineLoop: add methods findLoopControlBlock and findLoopPreheader adds 9364829 [AMDGPU] fix failure on printing of non-existing instruction [...] adds 5154970 Revert "[SimplifyCFG] Rewrite SinkThenElseCodeToEnd" adds 8f1b18b AMDGPU: Don't fold subregister extracts into tied operands adds 93a7ad2 AMDGPU: Update AMDGPURuntimeMetadata.h for enums of address s [...] adds e0a314c [InstCombine] add tests for missing vector icmp folds adds 12b2b51 [InstCombine] auto-generate exact checks adds 137c395 [libFuzzer] add InsertRepeatedBytes and EraseBytes. adds f5c5c7d [InstCombine] add tests for missing vector icmp folds adds 1bb8cbf Local variables whose address is taken and passed on to a cal [...] adds 8b850ac [InstCombine] add tests for missing vector icmp folds adds cc96a8c remove unnecessary IR comments about uses adds 3d09ca2 minimize test adds a451d6b [InstCombine] add test for missing vector icmp fold adds 66842c07 [InstCombine] add tests for missing vector icmp folds adds 1741b5a Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions." adds ade7edf Fix WAsm test after LSR change in r278658 adds bb8ab1a update test to use FileCheck and autogenerated checks adds 7016f85 [InstCombine] add tests for missing vector icmp folds adds 0347ebc [libFuzzer] fix the bot adds e286c13 [libFuzzer] print a verbose message after executing inputs in [...] adds 502957c llvm-objdump: Implement source[line numbers] interleaving adds f7714c1 [InstCombine] add tests for vector icmp folds adds fa85d67 [InstCombine] add test for missing vector icmp fold adds 1e230bc Enhance SCEV to compute the trip count for some loops with un [...] adds 3928f27 Fix a test that failed due to: https://llvm.org/svn/llvm-pro [...] adds f9b2472 [InstCombine] add tests for missing vector icmp folds adds d73e134 [ThinLTO] Remove functions resolved to available_externally f [...] adds b4ca813 Revert "[ValueTracking] Improve ValueTracking on left shift w [...] adds 70fd49b update tests to use FileCheck and exact checking adds 889162f Remove unnecessary flag from new test adds b430a4a GlobalISel: support loads and stores of strange types. adds 72159af [InstCombine] add tests for missing vector icmp folds adds 072a33f Really fix the issue with 502957cc9cf805dc6093950e8cdcd0db496 [...] adds fc94e66 AMDGPU/R600: Convert buffer id to VTX_READ input adds 29e5e14 Fix typo in lowering for fp128 ueq. adds caa3105 [InstCombine] add tests for missing vector icmp folds adds 36b7d78 [ADT] Change PostOrderIterator to use NodeRef. NFC. adds eeadbe0 [ADT] Fix DepthFirstIterator's std::iterator base to have nor [...] adds f514d2f [sancov] extracting AArch64 test to a separate file. adds 5912e9a Adding the triple for test comitted with r278703. adds d6a48b1 Linker: Avoid some ridiculous indentation by using a temporary. NFC adds dfacb43 [InstCombine] add tests for missing vector icmp folds adds d7f4d11 Don't use %llc_dwarf with -mtriple, they don't combine adds 3d6b718 [ThinLTO] Fix temp file dumping, enable via llvm-lto and test it adds ca77873 [AMDGPU] Give enum an explicit 64-bit type to fix MSVC 2013 failures adds 8e443cd [InstCombine] add tests for missing vector icmp folds adds cbcae43 [LTO] Rename variables with meaningul names, i.e. more than o [...] adds 8454221 [InstCombine] add tests for missing vector icmp folds adds 055f556 [LTO] Simplify APIs and constify (NFC) adds 22277af FunctionImport: rename ImportsForModule to ImportList for con [...] adds 2a393a5 FunctionImport: missed one occurence of ImportListForModule t [...] adds 0bf24e0 [InstSimplify] Fold gep (gep V, C), (xor V, -1) to C-1 adds 6f26a8e [X86] Add xgetbv/xsetbv intrinsics to non-windows platforms adds 9d30d1b [AVR] Fix compile errors adds a14491a [X86][SSE] Add support for combining target shuffles to PALIG [...] adds 6e45500 [Thumb] Validate branch target for CBZ/CBNZ instructions. adds 7461b8a Correct the upper bound for a CBZ/CBNZ branch target. adds fcc2de8 [X86][AVX512BW] Updated tests to demonstrate AVX512BW's inabi [...] adds 066b7e8 [X86][SSE] Add support for combining v2f64 target shuffles to [...] adds ecd478b [MemorySanitizer] [MIPS] Changed memory mapping to support pi [...] adds 12dc55c [Hexagon] Improve test to check for @PCREL, only run llc, not [...] adds 8cd8a7e [X86][AVX] Fixed typo in zero element insertion adds 349838b [x86] Refactor a PowerPC specific ctlz/srl transformation (NFC). adds 9b17aaa [GlobalISel] Mention pointers in LowLevelType.h. NFC. adds b92cbd8 [AArch64][GlobalISel] Select p0 G_FRAME_INDEX. adds 9e3f48d [AArch64][GlobalISel] Robustize select tests. NFC. adds e2e7ab2 [AArch64][GlobalISel] Select (variable) shifts. adds 89aeadc [Pipeliner] Fix an asssert due to invalid Phi in the epilog adds 7b9ac36 [ADCE] Modify data structures to support removing control flow adds a791148 [AArch64][GlobalISel] Factor out unsupported binop check. NFC. adds c57071e [GlobalISel] Fix G_MUL comment. NFC. adds cefc0d3 [AArch64][GlobalISel] Select G_MUL. adds 0ebd4a8 [Hexagon] Standardize vector predicate load/store pseudo inst [...] adds 0084b42 [InstCombine] use m_APInt in foldICmpWithConstant; NFCI adds fc81921 [Asan] Unpoison red zones even if use-after-scope was disable [...] adds 4bec123 Remove a stale comment from the test, NFC. adds 659db1f When the inline spiller rematerializes an instruction, take t [...] adds 84668a0 [Hexagon] Clean up some miscellaneous V60 intrinsics a bit adds d382882 [mips] Enforce compact branch restrictions adds b4d6119 [libFuzzer] refactoring around PCMap, NFC adds 3127862 [InstCombine] add helper functions for foldICmpWithConstant; NFCI adds 6795b93 [Coroutines] Part 7: Split coroutine into subfunctions adds d179884 [Hexagon] Standardize next batch of pseudo instructions adds 9c50958 Don't passively concatenate MDNodes adds 6628095 Make MDNode::intersect faster than O(n * m) adds b13de88 Remove excessive padding from LineNoCacheTy adds 2e1aa9c [libFuzzer] new experimental feature: value profiling. Profil [...] adds f8505d6 [MBP] do not reorder and move up loop latch block adds 298232b [BranchFolding] Change a test case of r278575. adds 7458542 Fix an instance of -Wmicrosoft-enum-value by making the enum [...] adds 34cb545 AMDGPU: Remove excessive padding from ImmOp and RegOp. adds 6a978fe [AArch64] Adjust the scheduling model for Exynos M1. adds 5fc5a98 [AArch64] Adjust the scheduling model for Exynos M1. adds 27985e0 TailDuplicator: Use range loops adds 8f5027f Revert "Enhance SCEV to compute the trip count for some loops [...] adds 2ed3d81 [LoopUnroll] Don't clear out the AssumptionCache on each loop adds 269bd65 [InstCombine] fix variable names to match formula comments; NFC adds f61ef6c [libFuzzer] minor speed improvement adds b3c0427 [x86] Allow merging multiple instances of an immediate within [...] adds 52a07ee CodeGen: Don't dereference end() in MachineBasicBlock::Correc [...] adds 764b87b [InstCombine] use m_APInt to allow icmp (sub X, Y), C folds f [...] adds 4184eb5 Preserve the assumption cache more often adds 3d3faeb [AMDGPU] Remove duplicate initialization of SIDebuggerInsertN [...] adds 7de6651 [InstCombine] clean up foldICmpAddConstant(); NFCI adds 3f979e7 Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough. adds 96f8a57 [InstCombine] add tests for fold with no coverage and missing [...] adds e24b74a Introduce LLVM_FALLTHROUGH, which expands to the C++17 attribute. adds d75cab6 Write the TPI stream from a PDB to Yaml. adds e3c3e55 CodeGen: Avoid dereferencing end() when unconstifying iterators adds 3cc2cd3 Revert "Write the TPI stream from a PDB to Yaml." adds cbbc1ca SimplifyCFG: Avoid dereferencing end() adds 9e4c8a3 AMDGPU: Avoid looking for the DebugLoc in end() adds 6058aba [Docs] Add initial MemorySSA documentation. adds f623792 Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranch adds d4e0802 CodeGen: Avoid dereferencing end() in OptimizePHIs::OptimizeBB adds 4a3738e ARM: Avoid dereferencing end() in ARMFrameLowering::emitPrologue adds 936a383 ObjCARC: Don't increment or dereference end() when scanning args adds 5780685 Scalar: Avoid dereferencing end() in InductiveRangeCheckElimination adds 370879f IPO: Swap || operands to avoid dereferencing end() adds c494412 [Docs] Fix post-review comments on MemorySSA's docs. adds 3b3dd88 Scalar: Avoid dereferencing end() in IndVarSimplify adds eb6a210 ADT: Add some missing coverage for iplist::splice adds 062c883 Some places that could using TargetParser in LLVM. NFC. adds bc17354 [Inliner] Add a flag to disable manual alloca merging in the [...] adds c6edf8f IfConversion: Improve doxygen comments adds 03d1f52 IfConversion: Use range based for; NFC adds be01ee2 IfConversion: Use references instead of pointers where possible; NFC adds b699f7b [PM] Port the always inliner to the new pass manager in a muc [...] adds 8db1b32 Remove the Triple tests that stressing the TargetParser's behaviour. adds 7177ff5 [ppc64] Don't apply sibling call optimization if callee has a [...] adds 6673ea8 Replace "fallthrough" comments with LLVM_FALLTHROUGH adds 833a10e Fix a use of LLVM_FALLTHROUGH that wasn't even in a switch. adds bba5e18 [LTO] Introduce an Output class to wrap the output stream cre [...] adds 731ba1d Restrict the use of the C++17 attribute to C++17 (at least as [...] adds de2442a First commit (test commit) - Adding empty line. adds ba80e96 [LTO] Fix a use-after-free introduced in r278907 and caught by ASan. adds cbfe590 Fix bug in DAGBuilder for getelementptr with expanded vector. adds 6811218 LiveIntervals: add removeRegUnit adds ae33160 [AMDGPU] llvm-objdump: Skip amd_kernel_code_t only at the beg [...] adds 653bfcb Fixing bug committed in rev. 278321 adds 1b85e47 [LoopStrenghtReduce] Refactoring and addition of a new target [...] adds 291f929 [Reassociate] Avoid iterator invalidation when negating value. adds cab764a Revert "[Reassociate] Avoid iterator invalidation when negati [...] adds 0ca6dc4 [mips] Add l.[sd] and s.[sd] instruction aliases adds e708f8d Clarify the statement on using #if 0 ... #endif in CodingStandards. adds 3b03767 [InstCombine] use m_APInt to allow icmp (add X, Y), C folds f [...] adds a537a2b Revert "Reassociate: Reprocess RedoInsts after each inst". adds 926ddae Support the DW_AT_noreturn DWARF flag. This is used to mark f [...] adds 9bec09d [InstCombine] add tests for missing vector icmp folds adds dae0b11 [InstCombine] clean up foldICmpOrConstant(); NFCI adds 9df3746 [InstCombine] use m_APInt to allow icmp (or X, Y), C folds fo [...] adds d9052e8 Move tests to the appropriate subdirectory. adds 79d1008 [libFuzzer] more mutations adds 83260f2 Fix for PR29010 adds 4221363 [InstCombine] clean up foldICmpXorConstant(); NFCI adds 4633e7e [InstCombine] more clean up of foldICmpXorConstant(); NFCI adds 6eaa7d5 [InstCombine] minimize tests and autogenerate checks adds 1dca602 [GenericDomTree] Change GenericDomTree to use NodeRef in Grap [...] adds 4da2d32 AMDGPU: Remove dead option adds 172174f [GraphWriter] Change GraphWriter to use NodeRef in GraphTraits adds 1d359ed [WebAssembly] Handle debug information and virtual registers [...] adds 3ed44cd GlobalISel: support irtranslation of icmp instructions. adds 7d7a23e Replace a few more "fall through" comments with LLVM_FALLTHROUGH adds 302f15f [docs] Adding "new target" rules to dev policy adds 21e2c00 Revert "[WebAssembly] Handle debug information and virtual re [...] adds b2724ac ADT: Remove UB in ilist (and use a circular linked list) adds 7526feb [libFuzzer] when printing the reproducer input, also print th [...] adds af9bcca TailDuplicator: Use optForSize instead of hasFnAttribute. adds 0a6e4fd Tail Duplication: Accept explicit threshold for duplicating. adds 9744bb4 [libFuzzer] one more mutation: ChangeBinaryInteger; also fix [...] adds 506857f [macho2yaml] Don't write empty linkedit data adds e65e275 [libFuzzer] given 0 and 255 more preference when inserting re [...] adds cebbb5e Fix reverse to work on const rbegin()/rend(). adds 6359c97 [RegionIterator] clang-format some pieces. NFC. adds 915cd42 wordsmith the "new targets" section a bit. adds 1a5ebc4 [InstCombine] add test for missing vector icmp fold adds 87032a5 [LV] Move LoopBodyTraits to a better place, and add comment f [...] adds 50d8d1e [LoopUnroll] Move a simple check earlier. NFC. adds 3a15af3 SCEV: Don't assert about non-SCEV-able value in isSCEVExprNev [...] adds 0f69921 Actually enable new test for const RangeAdapter. Missing fro [...] adds 03c1f4b Make llvm-pdbdump print column info when available adds ac9c0f4 [libFuzzer] force proper popcnt instruction adds 7c34aef [Docs] Update MemorySSA doc to address more feedback. adds 3f5fad8 [WebAssembly] Handle debug information and virtual registers [...] adds 4ab1e66 ADT: Tidy up ilist_traits static asserts, NFC adds a53e50c [LTO] Change addSaveTemps API: do not add dot to the supplied [...] adds 5bc5c47 [RuntimeDyld] Strip leading '_' from symbols on 32-bit window [...] adds 76e81b2 [asan] Add support of lifetime poisoning into ComputeASanStac [...] adds dcd27e4 [LTO] Promote before performing weak resolution adds b1cfb8c TailDuplicator: Fix crash after r278974 adds b798b8c [ThinLTO] Keep common symbols in ThinLTO modules adds b5871f9 Fix bot failure due to new test adds aa4e23e [sanitizer-coverage/libFuzzer] instrument comparisons with _ [...] adds b60f9a2 Revert r279016 -- it breaks win32-elf JIT tests. adds 2b56e93 Testcase for r279022 adds 11eaa16 [Docs] More MemorySSA doc updates! adds f1b025c Revert "ADT: Tidy up ilist_traits static asserts, NFC" adds 9d8d6de Revert "ADT: Remove UB in ilist (and use a circular linked list)" adds bc13f5f Remove trailing whitespace adds 4304bda (Trivial) TargetPassConfig: assert when TargetMachine has no [...] adds c73cfcf [Reassociate] Add test for PR28367. adds 44b9d6a [mips] Correct tail call encoding for MIPSR6 adds 3341243 [X86][SSE] Add SSE1 tests to make sure we don't merge loads o [...] adds 94dd772 [InstCombine] use m_APInt to allow icmp (xor X, Y), C folds f [...] adds 22850ef [Hexagon] Create vcombine in HexagonCopyToCombine adds ce587ac fix typo; NFC adds cec5045 llvm-readobj: handle import libraries with -coff-exports adds dd00c50 [InstCombine] use APInt in isSignTest instead of ConstantInt; NFC adds 3e6c82c [GlobalISel] Add support for DIV/REM. adds c9134ed [AArch64][GlobalISel] Select G_SDIV/G_UDIV. adds 0bc76c7 [WebAssembly] Refactor WebAssemblyLowerEmscriptenException pa [...] adds 1759316 [InstCombine] use m_APInt to allow icmp (mul X, Y), C folds f [...] adds 424d76c [ARM] Correct ARMv8*-A optional extension definitions in Targ [...] adds b6d362a [IRCE] Switch over to LLVM_DUMP_METHOD. NFCI. adds 190b463 [GlobalISel] Add floating-point binary ops. adds 2afbd4c [AArch64][GlobalISel] Select floating-point binary ops. adds 2e26f15 CVP. Turn marking adds as no wrap (introduced by r278107) off [...] adds e32f5ce ADT: Remove references in has_rbegin for reverse() adds 67f2890 Revert "ADT: Remove references in has_rbegin for reverse()" adds 8a83602 llvm-objdump: add coff import library symbol listing support adds 3fe902e Resubmit "Write the TPI stream from a PDB to Yaml." adds cd8d034 Reapply "ADT: Remove references in has_rbegin for reverse()" adds 1197bbf [InstCombine] clean up foldICmpUDivConstant; NFC adds 4446526 Fix -Wpessimizing-move error, NFC adds 7306a61 [Assumptions] Make collecting ephemeral values not quadratic [...] adds bb5b5bc [WebAssembly] Disable the store-results optimization. adds 030db64 [InstCombine] use m_APInt to allow icmp (udiv X, Y), C folds [...] adds 8970377 [LLVM] Fix some Clang-tidy modernize-use-using and Include Wh [...] adds 92e6c94 AArch64: Don't call getIterator() on iterators adds 4f657df Fix SystemZ compilation abort caused by negative AND mask adds bc2ba71 [AMDGPU] add s_incperflevel/s_decperflevel intrinsics. adds 3f7f855 [asan] Extend test adds 21eafc7 [CMake] Silence message on multi-configuration generators adds 86d5f19 [X86][SSE] Missed insertps shuffle patterns adds a13b2e5 Add a version of Intrinsic::getName which is more efficient w [...] adds b1ee91e Branch Folding: Accept explicit threshold for tail merge size. adds f65766d RegScavenging: Add scavengeRegisterBackwards() adds 3989d7e [SLP] Initialize VectorizedValue when gathering adds 443f72b AMDGPU : Fix QSAD and MQSAD instructions' incorrect data type. adds 175a34b [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, [...] adds f17a9b6 [InstCombine] clean up foldICmpTruncConstant(); NFCI adds d87f299 [InstCombine] use m_APInt to allow icmp (trunc X, Y), C folds [...] adds c43ec38 Make cltz and cttz zero undef when the operand cannot be zero [...] adds 2fb9361 [libFuzzer] add more __attribute__((visibility("default"))) adds 2b3323e AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc* adds 56ae20a [lanai] Add ISA document to CompilerWritersInfo adds c5ef0e6 [InstCombine] add helper function for folds of icmp (shl 1, Y [...] adds 1282ae4 [CMake] Support for generating Xcode 8 compatible toolchains adds 3ada6da [CMake] Minor fix to regex in r279152 adds 85a2cff [CMake] Make llvm-config implicit dependency for subprojects adds 0c6f849 [Analysis] Change several Analysis pieces to use NodeRef. NFC. adds 99174eb [SystemZ] Use valid base/index regs for inline asm adds 26b9220 [CMake] Create convenience targets for runtime projects adds f20ce37 llvm-objdump: Add Hexagon printer changes for -S/-l options adds 1eee0ec IfConversion: Handle inclusive ranges more carefully. adds bfd62a4 IfConversion: Rescan diamonds. adds 0fda934 CodeGen: If Convert blocks that would form a diamond when tai [...] adds e4c3ea0 Fix link quotes on AArch64's CompilerWriterInfo section. adds 664ab5e CodeGen: Add/Factor out LiveRegUnits class; NFCI adds 67f56cc [CMake] Add variables for tracking which runtimes are included adds 303a259 AArch64: remove extraneous padding adds 0f27e30 Include X86CallFrameOptimization in the opt-bisect process. adds 0c6c3b2 [asan] Optimize store size in FunctionStackPoisoner::poisonRedZones adds 84c33c6 [RuntimeDyld] Add support for ELF R_ARM_REL32 and R_ARM_GOT_PREL. adds d319716 [ADT] Add the worlds simplest STL extra. Or at least close to it. adds 0e6fefd Revert "RegScavenging: Add scavengeRegisterBackwards()" adds d9176f9 [RuntimeDyld][MCJIT] Un-XFAIL some tests that were fixed by r279182. adds 4c485c3 [XRay] Synthesize a reference to the xray_instr_map adds 7146ad0 [Profile] Simple code refactoring for reuse /NFC adds 6bdf641 [LTO] Add a move to inialize member in ctor initialization li [...] adds 855d81d Constify some path in the bitcode writer (NFC) adds dfdbbee [LTO] Move callback member from base class to the derived whe [...] adds 0842b8d [Profile] Fix edge count read bug adds edd6994 Fix tests in llvm/test/tools/gold/X86 to satisfy r279014. adds fefaef7 [PM] Rework the new PM support for building the ModuleSummary [...] adds 8c3a8f8 [PM] Redesign how the new PM detects whether an analysis resu [...] adds 3644902 [modules] Add missing include. adds 6567bc1 [PM] NFC refactoring: remove the AnalysisManagerBase class, f [...] adds bc8fdf7 [asan] Fix size of shadow incorrectly calculated in r279178 adds 341574b [CodeGen] Fix a trivial type conversion bug dating back to pre-2008 adds ae4f3e5 [PM] Try to work-around what appears to be an MSVC SFINAE iss [...] adds 73e7eb0 [PM] Make the the new pass manager support fully generic extr [...] adds 7fdf9ef [PM] Fix a compile error with GCC. NFC. adds 028b488 [SimplifyCFG] Rewrite SinkThenElseCodeToEnd adds 9962acc [X86][SSE] Add support for matching commuted insertps patterns adds 7d191bb [PM] Revert r279227 and r279228 until I can find someone to h [...] adds 7393ed5 [LoopVectorize] Don't copy std::vector in for-range loop. adds 4307374 [Hexagon] Improvements to handling and generation of FP instructions adds 8fa77e0 [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it in [...] adds b8b1bfc Fix PR27500: on MSP430 the branch destination offset is measu [...] adds 288392e [Hexagon] Rename the HEXAGON_MC namespace to Hexagon_MC, NFC adds 89c1dd3 [Hexagon] Remove unnecessary llvm::, NFC adds b8ce83f [Hexagon] Fix indentation, NFC adds 09091ea [Hexagon] Handle J2_jumptpt and J2_jumpfpt instructions adds 8935d87 Revert r279242 - it's failing the tests adds efe70d2 [Hexagon] Consider zext/sext of a load to i32 to be free adds b6b40cf [Hexagon] Check for empty live interval adds 041a158 [Hexagon] Allow tail-call optimization when mixing C and fast [...] adds 2f2ca67 Unxfail passing tests on Hexagon adds f7fe146 [Hexagon] Add explicit default constructor for HexagonSelecti [...] adds 1e982df [Hexagon] Make p0 an explicit operand in VA1_clr* subinstruct [...] adds 762d2ec [InstCombine] add missing tests for basic icmp folds adds f17d15a [InstCombine] add tests for missing vector icmp folds adds 3287fed [LTO] Remove dead-code: collectUsedGlobalVariables has been m [...] adds ee783de [InstCombine] use m_APInt to allow icmp X, C folds for splat [...] adds 66e1971 [Hexagon] Add missing pattern for C4_cmplte adds 1238f8d [InstCombine] use m_APInt to allow icmp (shl 1, Y), C folds f [...] adds 0ad37f7 [Hexagon] Fix incorrect generation of S4_subi_asl_ri adds c00499c [CloneFunction] Don't remove unrelated nodes from the CGSSC adds 3930987 [Hexagon] Minor updates to register definitions adds 0b2da49 MachineScheduler: Make some GenericScheduler member variables [...] adds baeb19c Fix regression in InstCombine introduced by r278944 adds 1ea0947 [Hexagon] Enforce LLSC packetization rules adds c05f998 [X86][SSE] Generalised combining to VZEXT_MOVL to any vector size adds 15095e4 [AliasSetTracker] Degrade AliasSetTracker when may-alias sets [...] adds 472f1cb [RuntimeDyld] Revert r279182 and 279201 -- they broke some ARM bots. adds 588e241 Revert "[asan] Fix size of shadow incorrectly calculated in r279178" adds 31c625e Revert "[asan] Optimize store size in FunctionStackPoisoner:: [...] adds 2fd227a GlobalISel: support overflow arithmetic intrinsics. adds f5027c2 [InstCombine] rename variables in foldICmpShlConstant(); NFC adds 40f2f0a [Hexagon] Fix a few omissions in HexagonInstrInfo adds 0cb3885 [InstCombine] use local variables to reduce code in foldICmpS [...] adds 50fbf50 [CostModel][X86] Add fdiv + frem cost tests adds 8d29e44 GlobalISel: support translation of extractvalue instructions. adds 4ef1afc [Hexagon] Fixes for new-value jump formation adds 59d0f6c GlobalISel: allow extractvalue to extract an aggregate. adds a242cdc Revert "CodeGen: If Convert blocks that would form a diamond [...] adds 8def210 Revert "IfConversion: Rescan diamonds." adds 07010a7 [CostModel][X86] Added some AVX512 and 512-bit vector cost tests adds 2c69b18 GlobalISel: improve representation of G_SEQUENCE and G_EXTRACT adds 8c28aa1 [PM] Re-instate r279227 and r279228 with a fix to the way the [...] adds 35e408d [Hexagon] Do not cache alloca instructions during isel adds e0de1be Add missing #include found by modules build. adds 5eb5a08 [InstCombine] remove an icmp fold that is already handled by [...] adds 18333ab [CostModel][X86] Added sub, or, and, fadd and fsub costs and [...] adds f9a8e62 [Hexagon] Allow i1 values for 'r' constraint in inline-asm adds 23d2b8b [Hexagon] Fix subesthetic indentation adds 5e464c9 [Hexagon] Add RUN line to test adds 9163bca MachineScheduler: Add constructor functions for the DAGMutations adds 7b7f7a5 GlobalISel: translate insertvalue instructions. adds 046622b GlobalISel: fix stale comment adds 843c638 GlobalISel: fix insert/extract to work on ConstantExprs too. adds d0d4756 GlobalISel: support translating select instructions. adds b8957bd GlobalISel: translate float/int conversion instructions. adds 31b3913 GlobalISel: translate floating-point constants adds 118c004 Reapply "ADT: Tidy up ilist_traits static asserts, NFC" adds b89c2fc Revert "[SimplifyCFG] Rewrite SinkThenElseCodeToEnd" adds 3cef1f9 Reapply "ADT: Remove UB in ilist (and use a circular linked list)" adds 65cdc46 [NVPTX] Switch nvptx-use-infer-addrspace to true. adds b47e6e5 GlobalISel: translate floating-point comparisons adds ff50821 GlobalISel: translate floating-point round/extend adds 47b1943 [libFuzzer] fix the non-debug build warnings adds 878c720 [ADT] add pointer_iterator, the opposite of pointee_iterator adds 48a33fd [Hexagon] Avoid register dependencies on indirect branches in [...] adds 61926b4 [Packetizer] Add debugging code to stop packetization after N [...] adds f6e737e [GraphTraits] Make nodes_iterator dereference to NodeType*/NodeRef adds 85e5e73 [CallGraph] Use decltype instead of pointer_to_unary_function. NFC. adds 36caf71 Convert some depth first traversals to depth_first adds b2ae2ed Revert "[asan] Add support of lifetime poisoning into Compute [...] adds 9e4dd12 Partially revert 279331, as we modify this instruction in the loop adds e52c44e MachineFunction: Make LastProperty an alias of the last property adds 78efd69 MachineFunction: Cleanup/simplify MachineFunctionProperties::print() adds 177fbef [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds f [...] adds 077e6b7 GlobalISel: teach legalizer how to handle integer constants. adds 4e4ac88 GlobalISel: support legalization of G_FCONSTANTs adds fb1ead3 Reset "undef" flag when coalescing subregister into whole register adds 8b3f754 MachineFunction: Add llvm_unreachable for missing properties adds cb9042a [LTO] Add the ability to test -thinlto-emit-imports-files thr [...] adds 746d3be [gold] Fix new gold test to specify emulation mode adds f4b6540 [gold/ThinLTO] Restore ThinLTO file management in gold plugin adds 65b9267 [PM] Introduce an abstraction for all the analyses over a par [...] adds 990c9c0 [Profile] add test with large counts adds 12512d1 [CMake/ASan] Skip using libedit if ASan is enabled -- it leak [...] adds 914b867 Revert "[SLP] Initialize VectorizedValue when gathering" to f [...] adds 4848b39 [SLP] Add command line option for minimum tree size (NFC) adds fcc016a Reapply "[SLP] Initialize VectorizedValue when gathering" adds 250933d Move unittests/Support/IteratorTest.cpp to unittests/ADT/ adds 939300c [asan] Add support of lifetime poisoning into ComputeASanStac [...] adds 2c5977c [X86][SSE] Added vector interleave test (PR21281) adds c662b7e [asan] Cleanup instrumentation of dynamic allocas adds 7b2eb8e [asan] Optimize store size in FunctionStackPoisoner::poisonRedZones adds d66cc57 [asan] Initialize __asan_set_shadow_* callbacks adds 24f7c90 Use SDValue::getOpcode() helper instead of via SDValue::getNode() adds 49a5f5e [asan] Minimize code size by using __asan_set_shadow_* for la [...] adds 3e148ac [X86][XOP] Tweak vpermil2pd test to stop it being combined away adds ac36473 Regenerate test adds 83c785e Regenerate test adds 796c99cb [X86] Regenerate fp truncate tests adds 5ac5ac2 [X86][SSE] Regenerate subvector extraction widening test adds 4a5c030 [X86][SSE] Regenerate 32-bit buildvector test adds 5779415 Fix broken macOS LLDB Xcode build from r279314 adds 68336ac ARM: Avoid dereferencing end() in ARMFrameLowering::emitEpilogue adds 314286f3 [AVX512][FastISel] Do not use K registers in TEST instructions adds e01d057 [InstCombine] use APInt instead of ConstantInt in isSignBitCh [...] adds 3001aca [X86][AVX] Dropped combineShuffle256 - this can now be perfor [...] adds a5d8761 [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds f [...] adds ecce337 [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds f [...] adds 2072482 remove FIXME comment; fixed by previous commit adds a690e12 [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds f [...] adds 4597dd9 [CostModel][X86] Split off float arithmetic cost tests adds 4630834 [CostModel][X86] Added fsqrt and fma costs adds 799c5eb [CostModel][X86] Replaced SSSE3 with SSE2 costs to create a b [...] adds 26eaf4f [CostModel][X86] Added costs for vXi16 and vXi8 vectors for a [...] adds fc26436 [CostModel][X86] Removed shift tests adds 805f0aa Untabify. adds fb2d85d Reformat. adds a32e9b4 [X86] Remove ignoreVEX_L from TSFlags. Only the disassembler [...] adds d8452fe [X86] Merge hasVEX_i8ImmReg into the ImmFormat type which had [...] adds 663b75a [asan] Use 1 byte aligned stores to poison shadow memory adds 1282b19 [LTO] Add a "CodeGenOnly" option. Allows the client to skip t [...] adds 156e0da [LTO] Handles commons in monolithic LTO adds f631b7a Add REQUIRES:X86 to test/tools/llvm-lto2/common.ll adds d30b1a1 [X86] Explicitly list all X86 instruction forms in switch sta [...] adds 6e07b06 [X86] Merge small helper function into the switch that calls [...] adds b663f70 [X86] Space out the encodings of X86 instruction formats. I p [...] adds 91e5e58 [X86] Create a new instruction format to handle MemOp4 encodi [...] adds 08f89d5 [X86] Create a new instruction format to handle 4VOp3 encodin [...] adds 8daa7b7 [ThinLTO][X86] Fix windows build adds 3d64372 [MC] Remove guard(s). NFCI. adds 00748f4 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC ins [...] adds b603350 [X86][SSE] Avoid specifying unused arguments in SHUFPD lowering adds b10dff9 [PM] Port LoopDataPrefetch AArch64 tests to new pass manager adds d8d6388 Revert -r278269 [IndVarSimplify] Eliminate zext of a signed I [...] adds a267310 Revert -r278267 [ValueTracking] An improvement to IR ValueTra [...] adds cd61cee Remove missing file from r279433 reversal adds 82a414c [X86] Only accept SM_SentinelUndef (-1) as an undefined shuff [...] adds b24532b Reset isUndef when removing subreg from a def operand adds 5c13456 [LTO] Constify the Module Hook function (NFC) adds b469a38 [mips][ias] Support .dtprel[d]word and .tprel[d]word directives adds b41bec0 Fix Gold Plugin after API change in the LTO API (constify cal [...] adds 8d91e9a [X86][AVX] Don't use SubVectorBroadcast if there are addition [...] adds e093ba3 [SimplifyCFG] Rewrite SinkThenElseCodeToEnd adds abcbb63 Revert "[SimplifyCFG] Rewrite SinkThenElseCodeToEnd" adds 11ee15b [InstCombine] Allow sinking from unique predecessor with mult [...] adds 06e3fec [SSP] Do not set __guard_local to hidden for OpenBSD SSP adds a4a86e5 [SROA] Remove incorrect assertion adds 6a5d369 [SimplifyCFG] Rewrite SinkThenElseCodeToEnd adds 51dfc8b MSSA: Only rename accesses whose defining access is nullptr adds ce35dd2 MSSA: Factor out phi node placement adds 7517ed2 AMDGPU: Split SILowerControlFlow into two pieces adds 084874b IDFCalculator: Remove unused field. adds 75494aa Add comments and an assert to follow-up on r279113. NFC. adds 00a565c Add ADT headers to the cmake headers directory for LLVMSuppor [...] adds e3ecb56 [InstCombine] use m_APInt to allow icmp (shr exact X, Y), 0 f [...] adds d47df87 ADT: Remove ilist_*sentinel_traits, NFC adds 22fca38 [GraphTraits] Replace all NodeType usage with NodeRef adds 0fd3c95 [InstCombine] change param type from Instruction to BinaryOpe [...] adds 3d515f6 [ADT] Actually mutate the iterator VisitStack.back().second, [...] adds 9ed748e Fix header comment for unittests/ADT/ilistTest.cpp adds fd2abc5 ADT: Separate some list manipulation API into ilist_base, NFC adds 72d647d Fix crash from assert in r279466. adds a28b29b [InstSimplify] add helper function for SimplifyICmpInst(); NFCI adds 9d02a13 [MemorySSA] Remove unused field. NFC. adds ee0313b [lanai] Exit early in Mem Alu combiner if sentinel reach. adds cf0122b [lanai] Make Lanai backend non-experimental adds 5f3b1be BranchRelaxation: Fix handling of blocks with multiple condit [...] adds ded269b CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)Mo [...] adds eb3b739 Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: [...] adds 412e256 GVNHoist: Use the pass version of MemorySSA and preserve it. adds a04e9e4 [ARM] Generate consistent frame records for Thumb2 adds 688daa7 [X86][SSE] Demonstrate inability to recognise that (v)cvtpd2p [...] adds 2d4d290 Change the target's name, s/LanaiMCTargetDesc/LanaiDesc/g. adds d53c5e9 LLVMLanaDesc: Update libdesp. adds 9cbe8af [X86][SSE] Demonstrate inability to recognise that (v)cvtpd2p [...] adds 5bf89a1 [LTOCodeGenerator] Reduce code duplication. NFCI. adds 3804663 Fix SystemZ hang caused by r279105 adds 0b99a8a [lanai] Use const instead of constexpr adds f3f6eb5 [X86][AVX] Add AVX2/AVX512 fp to int conversion tests adds 8479207 [X86][AVX] Add v2i32 fp to int conversion tests adds 66bde5c [X86][AVX] Updated fptosi_2f64_to_4i32 test to show missed op [...] adds 20885de Work around PR29097 to get the module bots going again. This [...] adds ee836b9 [Profile] refactor meta data copying/swapping code adds bda1572 Rename unittests/ADT/ilistTest.cpp to ilistTestTemp.cpp (temp [...] adds d2746ea Fix windows build failure adds 7fd3acf [Hexagon] Packetize return value setup with the return instruction adds a350f5d [X86][SSE] Demonstrate inability to recognise that (v)cvtpd2d [...] adds 0504d91 Fix some more asserts after r279466. adds d09e4ee [InstSimplify] move icmp with constant tests to another file; NFC adds 52a318c [ThinLTO] Make sure the Context used for the ThinLTO backend [...] adds f982483 [InstSimplify] add tests to show missing vector icmp folds adds 9feaa97 Fix some Clang-tidy modernize-use-using and Include What You [...] adds 66abb74 [CodeGen] Convert a loop to a for-each loop. NFC adds 073ec4a [SelectionDAG] Use a union of bitfield structs for SDNode::Su [...] adds 405b046 [InstSimplify] allow icmp with constant folds for splat vecto [...] adds 0303a1a Possible fix of test failures on win bots adds d439a66 [InstSimplify] allow icmp with constant folds for splat vecto [...] adds 29a5291 [CMake] [OCaml] Add -DLLVM_ENABLE_OCAMLDOC switch adds 4e7c4f9 [ThinLTO] Add a llvm-lto2 test to check that ODR type uniquin [...] adds 6df27f9 GlobalISel: legalize 1-bit load/store and mark 8/16 bit varia [...] adds f6f4848 Revert "[ThinLTO] Add a llvm-lto2 test to check that ODR type [...] adds 23194f6 Stop always creating and running an LTO compilation if there [...] adds c016311 [ThinLTO] Add a llvm-lto2 test to check that ODR type uniquin [...] adds 3891c45 GlobalISel: mark pointer casts legal on AArch64. adds 585ed95 GlobalISel: extend legalizer interface to handle multiple types. adds 26bccd6 [LTO] Fix test following r279550 adds f99445f Update coding standards for include style. adds 9e9267d Remove unused translation unit. adds 35b8916 [SLP] Avoid signed integer overflow adds 5896550 [ValueTracking] Use a function_ref to avoid multiple instantiations adds 1bb228f CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)Mo [...] adds 2956257 GlobalISel: legalize conditional branches on AArch64. adds 4f24b7d GlobalISel: legalize integer comparisons on AArch64. adds 2a10560 GlobalISel: make truncate/extend casts uniform adds 4cc20be [InstCombine] remove icmp shr folds that are already handled [...] adds a44dd5e GlobalISel: add forgotten test-case for G_ICMP adds db9ce2f MachineFunction: Introduce NoPHIs property adds 87aa10b [stackmaps] Extract out magic constants [NFCI] adds e9aa7e0 [InstCombine] move foldICmpShrConstConst() contents to foldIC [...] adds 242275b [ThinLTO] Add caching to the new LTO API adds e994d79 [MC] Support .dc directives in assembler parser adds 35f70a7 [InstCombine] use local variables for repeated values; NFCI adds 373a882 GlobalISel: add some G_TRUNCs to make icmp test valid MIR. adds 5a65f77 Revert r279564. It introduces undefined behavior (binding a r [...] adds e45f656 Remove unused data member to unbreak -Werror builds. adds b688511 #ifdef out validation code when asserts are disabled to remov [...] adds 0f97be8 Don't use "return {...}" to initialize a std::tuple. This has [...] adds 7433358 [LoopUnroll] By default disable unrolling when optimizing for size. adds 8751003 [stackmaps] More extraction of common code [NFCI] adds 9404188 [libFuzzer] docs on value profile adds bb66a7d [libFuzzer] collect 64 states for value profile, not 65 adds 5c09136 [libFuzzer] fix link in docs adds 4ecbb91 [stackmaps] Remove an unneeded member variable [NFC] adds 7374d90 [ADCE] Add control dependence computation adds 43f89c5 MachineModuleInfo: Avoid dummy constructor, use INITIALIZE_TM_PASS adds 459280c Increase the size of the sigaltstack used by LLVM signal hand [...] adds 6648973 MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. adds 0c7940e [libFuzzer] use __attribute__((target("popcnt"))) only on x86_64 adds fa5c5c7 CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)Mo [...] adds fb33552 TargetSchedule: Do not consider subregister definitions as reads. adds 517a659 Preserve a pointer to the newly allocated signal stack as wel [...] adds c5f116c [Coroutines] Part 8: Coroutine Frame Building algorithm adds 07ea3b0 [Coroutines] Fix unused var warning in release build adds f151c23 Tentatively fix gold-plugin test: ThinLTO objects start at of [...] adds 377af8d [PM] Introduce basic update capabilities to the new PM's CGSC [...] adds e23f2de [X86][SSE] Add support for 32-bit element vectors to X86ISD:: [...] adds 568c0d2 [Loop Vectorizer] Support predication of div/rem adds dfa8eaa [X86][F16C] Regenerated f16c tests adds e01c44e [X86][AVX2] Ensure on 32-bit targets that we broadcast f64 ty [...] adds 39b3d8a [mips] Preparatory work for a generic scheduler adds 31a5f88 Create subranges for new intervals resulting from live interv [...] adds b403b76 [InstCombine] add assert and explanatory comment for fold rem [...] adds 1461e99 [llvm-cov] Add the project summary to each source file covera [...] adds 25d826e AMDGPU : Add V_SAD_U32 instruction pattern. adds e2aca6b [X86][SSE] Regenerate scalar math load folding tests for 32 a [...] adds 57b248a [ThinLTO/gold] Add caching support to gold-plugin adds 4e85e20 GlobalISel: fix cmp test to be in SSA form adds 96d3445 fix typo 'varaible' in assert adds dff4c00 [Hexagon] Remove the utilization of IMPLICIT_DEFs from expand [...] adds 8f3d1c87 [Hexagon] Enable subregister liveness tracking adds aa06e49 [X86][SSE] Add support for combining VZEXT_MOVL target shuffles adds 09f0b3c [SCCP] Don't delete side-effecting instructions adds 5b97970 [AArch64] Adjust the feature set for Exynos M1. adds 428e79c [LV] Unify vector and scalar maps adds bf471b7 DebugInfo: Add flag to CU to disable emission of inline debug [...] adds 7432a84 [X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load [...] adds bde752e Use isTargetMachO instead of isTargetDarwin. adds fb717b4 AMDGCN/SI: Implement readlane/readfirstlane intrinsics adds b55d189 ARM: don't diagnose cbz/cbnz to Thumb functions. adds b711924 IfConversion: Rescan diamonds. adds 24ff83f CodeGen: If Convert blocks that would form a diamond when tai [...] adds da04ce1 MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness earl [...] adds 66b84cc [InstCombine] use m_APInt to allow icmp eq/ne (shr X, C2), C [...] adds 9d1674f [Hexagon] Change insertion of expand-condsets pass to avoid m [...] adds 6928bc9 Missed a test in my last commit adds 249a315 MIRParser/MIRPrinter: Compute HasInlineAsm instead of printin [...] adds d720b00 [Hexagon] Check for block end when skipping debug instructions adds e3beeb7 MIRYamlMapping cleanup adds a7bda2e [WebAssembly] Change a comment line adds 2af8582 The patch improves ValueTracking on left shift with nsw flag. adds 1b1bb95 [InstCombine] move foldICmpDivConstConst() contents to foldIC [...] adds 4d000ed [libFuzzer] make a test more deterministic adds 7a5b51d Test: Add REQUIRES: asserts to test that now requires stats. adds 1a1f08d [Profile] Propagate branch metadata properly in instcombine adds 3d7ca1c Fix some Clang-tidy modernize-use-using and Include What You [...] adds 3772549 Make some LLVM_CONSTEXPR variables const. NFC. adds cf1269a [libFuzzer] simplify the code, NFC adds 690a3cb MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated [...] adds 816e968 Update a comment. adds 227103b TailDuplication: Save MF and reduce number of parameters. NFC adds 06d37a2 TailDuplication: Don't pass MMI separately from MF. NFC adds 29b947d Make buildbots happy. adds 264e763 [asan] Disable CreateSigAltStack from Unix/Signals.inc for as [...] adds 744b8ba Fixed comment adds b5afdad [X86] Fix indentation per coding standards. NFC adds 6031ab5 [X86] Simplify getOperandBias as a bit. NFC adds 21af1c9 GVN-hoist: fix hoistingFromAllPaths for loops (PR29034) adds 8102979 [X86][AVX] Provide SubVectorBroadcast fallback if load fold f [...] adds 271996d [X86][AVX] Improved AVX512F/AVX512VL SubVectorBroadcast tests adds 142e714 [Hexagon] vector store print tracing. adds 5c843d7 Fix line endings adds 8ce317b [UNROLL] Postpone ScalarEvolution::forgetLoop after TripCount [...] adds 79a4f4e [Hexagon] Remove extraneous debug output from HexagonCopyToCo [...] adds 0913709 [X86][SSE] INSERTPS is only combined on v4f32 types. NFCI. adds 59f7ccf [X86] 512-bit VPAVG requires AVX512BW adds 774da37 Hooking up a check-all target for the runtimes projects adds bbdb9c7 GlobalISel: mark small extends as legal on AArch64 adds 042ca5a GlobalISel: perform multi-step legalization adds faab2fb GlobalISel: mark pointer constants as legal on AArch64. adds 1b03791 GlobalISel: mark simple ops legal even on types < 32-bit. adds a9111c1 GlobalISel: mark overflow bit of overflow ops legal. adds ecd159c GlobalISel: add missing type to G_UADDE instructions adds 543a8c1 Reuse an SDLoc throughout a function. NFC. adds f65deb8 [MemCpy] Check for alias in performMemCpyToMemSetOptzn, inste [...] adds c76060f llvm-objdump: ELF: Handle code and data mix in all scenarios adds 6361cd1 ARM: by default don't set the Thumb bit on MachO relocated values. adds 3e8e88e [CMake] Add support for exposing runtime targets adds fdda55b cmake: Install CheckAtomic.cmake (needed by lldb) adds 943f7f4 [MemCpy] Add comments for r279769 adds 0eddaa0 Revert r274613 because it breaks the test suite with AVX512 adds dffc922 Fix ArrayRef initializer_list Ctor Test adds efd12f4 Revert r279782 due to debug buildbot breakage. adds 7750b38 [libFizzer] rename -print_new_cov_pcs=1 into -print_pcs=1 and [...] adds 5858ccd Revert r274613 because it breaks the test suite with AVX512 adds cf34910 [libFuzzer] make sure we have symbols on fuzzer tests adds be74ea2 [libFuzzer] simplify a test to make it pass on the bot adds 734891c Fix the static_assert added in r279536. adds 7092439 Fix singlton -> singleton typo. adds f9a7ed7 Replace subregister uses when processing tied operands adds f184175 [X86][SSE] Add CMPSS/CMPSD intrinsic scalar load folding support. adds e21267a Implement getRandomBytes() function adds 65eaa0f [X86][SSE4A] The EXTRQ/INSERTQ bit extraction/insertion ops s [...] adds db520df Handle empty functions with debug info in load/store opt pass adds 57accc8 [AArch64] Avoid materializing constant 1 by using csinc, rath [...] adds 84b3a5e [lib/LTO] Add an assertion to catch invalid opt levels. adds dada7d4 [InstCombine] rename variables in foldICmpDivConstant(); NFC adds d138c45 [LoopUnroll] Use OptimizationRemarkEmitter directly not via t [...] adds 2adbfa1 test commit adds f222adf [InstCombine] rename variables in foldICmpAndConstant(); NFC adds 4403f2c FileCheck: Minor cleanup of the class Pattern adds 6deac82 limit the number of instructions per block examined by dead s [...] adds a14798a [InstCombine] add helper function for folding of icmp (and X, [...] adds 85b37dc Add some more detailed debugging information in RegisterCoalescer adds db0c5ed Missed a semicolon in r279835 adds c3dc8a9 [InstCombine] clean up foldICmpAndConstConst(); NFC adds f1f64be GlobalISel: mark float/int conversions legal adds 3c47a67 GlobalISel: mark selects legal adds e7265c7 GlobalISel: legalize under-width divisions. adds b04cf87 GlobalISel: legalize sdiv and srem operations. adds 75d2e48 GlobalISel: simplify G_ICMP legalization regime. adds 9e4ec13 GlobalISel: mark G_FCMP legal on float & double. adds ce55c03 GlobalISel: mark G_FPEXT legal from float to double. adds def731a [MC] Move .cv_loc management logic out of MCContext adds fb0de92 [AsmParser] Placate a -Wmisleading-indentantion warning (GCC7). adds 519119c [AArch64] Avoid materializing constant values when generating [...] adds d96bcc0 [InstCombine] add helper function for icmp (and (sh X, Y), C2 [...] adds 2fd36a5 AArch64: avoid assertion on illegal types in performFDivCombine. adds 55d021c Swift Calling Convetion: add support for AArch64. adds ff19e2b Next set of additional error checks for invalid Mach-O files [...] adds ceaef9f Streamline LTO getComdat invocation (NFC) adds 7921d70 [CMake] Fixing LLVM_INCLUDE_TESTS for runtimes directory adds db440c8 TailDuplication: Record blocks that received the duplicated b [...] adds 9e8a8de Make writeToResolutionFile a static helper. adds c96b33c [Inliner] Report when inlining fails because callee's def is [...] adds cf9a1e3 [CMake] Expose runtime component check targets adds 8de9275 AMDGPU/SI: Use a better method for determining the largest pr [...] adds 96359c1 XXX adds c6ee33f AMDGPU/SI: Canonicalize offset order for merged DS instructions adds 1c4f0f9 [MFProperties][NFC] Rename clear into reset to match BitVecto [...] adds 7e94389 [MFProperties] Introduce a reset method with no argument. adds ea4e88c TableGen: Switch from a std::map to a DenseMap in CodeGenSubR [...] adds ac0c6d3 [MachineFunction] Introduce a reset method. adds aaa2879 [SelectionDAG] Do not run the ISel process on already selected code. adds 65ce6c6 [IRTranslator][NFC] Use DEBUG_TYPE instead of repeating the name. adds be4c110 [TargetPassConfig] Add a target hook to know what GlobalISel [...] adds bc94ace Adding document describing the use of the -opt-bisect-limit option. adds d80408f [ThinLTO] Move loading of cache entry to client adds 6dff9d7 [MFProperties] Introduce a FailedISel property. adds c15079f [IRTranslator] Do not abort when the target wants to fall back. adds b274272 [X86] Add baseline test for "odd" shuffles. NFC. adds 411fc07 [GlobalISel] Teach the core pipeline not to run if ISel failed. adds 1dba46c [AArch64][CallLowering] Do not assert for not implemented part. adds c47e5db [GlobalISel] Add a fallback path to SDISel. adds fd6bad6 [ORC] Fix typo in LogicalDylib, add unit test. adds 4ec9567 [CMake] Only generate Components.cmake if components are specified adds d97fe48 AMDGPU: Improve error reporting for maximum branch distance adds 36a8c3e AMDGPU: Remove register operand from si_mask_branch adds f5dc5ec AMDGPU: Fix sched type for branches adds e52dfc9 AMDGPU: Move cndmask pseudo to be isel pseudo adds 95ec13b AMDGPU: Select mulhi 24-bit instructions adds bbef3e0 [MachineLegalize] Do not abort when the target wants to fall back. adds 16b39f4 [InstructionSelect] Do not abort when the target wants to fall back. adds 529dc06 [RegBankSelect] Do not abort when the target wants to fall back. adds fab5bb8 GVN-hoist: invalidate MD cache (PR29144) adds a59e27b [Orc] Explicitly specify type for assignment. adds 6441d23 AMDGPU: Remove unneeded implicit exec uses/defs adds 8b9a56b AMDGPU: Mark sched model complete adds 2b799fd [LTO] Don't create a new common unless merged has different size adds 9c6419d [AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd. adds ffbe701 [X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted. adds 6399425 [AVX-512] Allow EVEX encoding unordered/ordered/equal/notequa [...] adds a733d39 [X86] Remove stale comment about FixupBWInsts pass being off [...] adds 8b5392f [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Ad [...] adds b70cda8 [X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. [...] adds 7b84fc3 [X86] Keep looping over operands looking for byte registers e [...] adds 53e8717 [X86] Rename predicate function that detects if requires one [...] adds 3ed3938 AMDGPU/R600: Enable Load combine adds 460412a [X86] Rename PABSB/D/W instructions to be consistent with SSE [...] adds 2e47cee [AVX-512] Add tests to show that we don't select masked logic [...] adds 800ba95 [AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when w [...] adds 1b2a850 [Loop Vectorizer] Fixed memory confilict checks. adds afa0d10 [PowerPC] Implement lowering for atomicrmw min/max/umin/umax adds 337ddd9 [X86][AVX512] Only combine EVEX targets shuffles to shuffles [...] adds 2c15995 [InstCombine] use m_APInt to allow icmp (and X, Y), C folds f [...] adds 481aed7 [x86] add tests for <3 x N> vector types (PR29114) adds 297f179 Fix some typos in the doc adds 28dc9c9 [AVX-512] Add testcases showing that we don't emit 512-bit vp [...] adds 4d4300a [AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS i [...] adds 75d5183 [AVX-512] Add support for selecting 512-bit VPABSB/VPABSW whe [...] adds 572aa19 [Orc] Simplify LogicalDylib and move it back inside CompileOn [...] adds 040e63a [AVX-512] Add 512-bit fabs tests with and without AVX512DQ. adds 79711e4 [AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/F [...] adds 51b695a [X86] Don't lower FABS/FNEG masking directly to a ConstantPoo [...] adds f0a2d5f [InstructionSelect] NumBlocks isn't defined in DEBUG build. adds 84cb7f4 [AVX512] In some cases KORTEST instruction may be used instea [...] adds 922af1c Fixed a bug in type legalizer for masked gather. The problem [...] adds 675d699 AMDGPU/SI: Query AA, if available, in areMemAccessesTrivially [...] adds 1801e2f Fix -Wunused-but-set-variable warning. adds 1a56948 Move code only used by codegen out of MC. NFC. adds 5f65d09 Mark test as XFAIL instead of disabling it everywhere. adds 6e61a44 Use the correct ctor/dtor section for dynamic-no-pic. adds a8fa402 AMDGPU/SI: Improve register allocation hints for sopk instructions adds adef5a6 Do not use MRI::getMaxLaneMaskForVReg as a mask covering whol [...] adds bbb2e05 [TargetLowering] remove fdiv and frem from canOpTrap() (PR29114) adds bce16c6 [Coroutines] Part 9: Add cleanup subfunction. adds d003672 [SimplifyCFG] rename test file, regenerate checks, and add test adds ae5557c [Constant] remove fdiv and frem from canTrap() adds f486ff3 [LTO] Remove extraneous output adds 3262806 [StatepointsForGC] Rematerialize in the presence of PHIs adds d05e1fc [AArch64] Adjust the scheduling model for Exynos M1. adds bf8ab3e [gold] Fix test accidentally regressed for newer gold adds e8beddd Make vec_fabs.ll pass with MSVC 2013 adds f94d4a7 [SimplifyCFG] Hoisting invalidates metadata adds 997a485 [asan] Separate calculation of ShadowBytes from calculating A [...] adds b8ae70f Use store operation to poison allocas for lifetime analysis. adds fc5add2 IfConversion: Fix branch predication bug. adds 11b4774 AMDGPU/R600: Fix fixups used for constant arrays adds 755f9da GlobalISel: rework CallLowering so that it can be used for li [...] adds b3b5a54 GlobalISel: legalize frem to a libcall on AArch64. adds 9358435 ASan: remove variable only used in assertions build adds 55792f0 AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the [...] adds da2666c GlobalISel: switch to SmallVector for pending legalizations. adds 6e3f5dd [asan] Enable new stack poisoning with store instruction by default adds 4a5c408 AMDGPU/SI: Implement a custom MachineSchedStrategy adds 94821da [Myriad]: add missing 'mcpu' values adds 5413d61 Propagate TBAA info in SelectionDAG::getIndexedLoad adds 1254de0 [LV] Move insertelement sequence after scalar definitions adds 6aad1fb [CMake] Builtins build needs LLVM_*_OUTPUT_INTDIR variables adds 2946185 ExecutionEngine: fix a bug in the movt/movw relocator adds 702e513 AMDGPU: fix mismatch tags, NFC adds 0d977a1 Fix a thinko in r278189. adds 7c20af7 GlobalISel: use multi-dimensional arrays for legalize actions. adds 684477b [CMake] Make LLVMConfig.cmake variable names match in-tree names adds d6f8e0f [ORC][RPC] Make the future type of an Orc RPC call Error/Expe [...] adds 55a983f [ORC][RPC] Fix typo in RPC comments: call primitives on void [...] adds 79944cc AMDGPU/R600: Remove MergeVectorStores from legalization adds 2f811bd [SLP] Return a boolean value for these static helpers. NFC. adds e060ffb [PowerPC] Fix i8/i16 atomics for little-Endian targets withou [...] adds cf53871 [ThinLTO] Indirect call promotion fixes for promoted local functions adds 1169682 Fix typo in comment. NFC. adds 908f420 [ORC] Fix unit-test breakage from r280016. adds 460ff94 AMDGPU/R600: Cleanup DAGCombine adds 1d79fff ADT: Give ilist<T>::reverse_iterator a handle to the current node adds ba63e29 Rename unittests/ADT/ilistTestTemp.cpp => IListTest.cpp adds 9cb78e2 [PowerPC] Add triple to test/CodeGen/PowerPC/atomic-2.ll for ppc64le adds bad305a NFC: add early exit in ModuleSummaryAnalysis adds 557221a [PowerPC] Add support for -mlongcall adds 8c23b33 [sanitizer-coverage] add two more modes of instrumentation: t [...] adds ff612bc [libFuzzer] use trace-div and trace-gep for guided fuzzing, a [...] adds e86c615 ADT: Explode include/llvm/ADT/{ilist,ilist_node}.h, NFC adds 08f02f5 Fix coding style; NFC adds c1d8a15 [PowerPC] Force entry alignment in .got2 adds 9e15636 [ORC][RPC] Reword 'async' to 'non-blocking' to better reflect [...] adds 23b4641 [RewriteStatepointsForGC] Update comment for same PHI node ch [...] adds c7c6f45 [libFuzzer] use bits instead of bytes for memcmp/strcmp value [...] adds 8f4d66d Replace incorrect "#ifdef DEBUG" with "#ifndef NDEBUG". adds fd61a98 [Support] Add a conditionally defined default constructor (av [...] adds ba87832 [Support][Error] Suppress warning about unused result. adds 696fea9 [llvm-cov] Use the native path in the coverage report. adds eaff23d docs: mention that clobbering output regs in inline asm is illegal. adds 95bbd1e [SimplifyCFG] Properly CSE metadata in SinkThenElseCodeToEnd adds 84ea382 SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused [...] adds 2a7897d [Reassociate] Add additional debug output. NFC. adds 0d8f244 [MC] Move parser helper functions from Asmparser to MCAsmParser adds 773652b [libFuzzer] stop using bits for memcmp's value profile -- see [...] adds 72187d4 [libFuzzer] fix a bug when running a single unit of N bytes w [...] adds db6b577 Revert "[ORC][RPC] Make the future type of an Orc RPC call Er [...] adds 39dbb53 [AMDGPU] Refactor SOP instructions TD files. adds 788dfe5 Fixup r279618, instantiate *AnalysisManagerProxy<*AnalysisMan [...] adds f1f27bb ADT: Split out simple_ilist, a simple intrusive list adds f81c893 ADT: Clean up docs and formatting for ilist_traits, NFC adds 558d668 [InstCombine] clean up foldICmpDivConstant; NFCI adds 298afcc Add StringRef::contains() adds bb0403b Add StringRef::take_front and StringRef::take_back adds f097e13 [InstCombine] replace divide-by-constant checks with asserts; NFC adds b161c80 IR: Appease MSVC after r280107 with an & or two adds b8d741f Appease buildbots after r280114. adds 2f1f35b ADT: Guarantee transferNodesFromList is only called on transfers adds 63347e9 TailDuplication: Extract Indirect-Branch block limit as option. NFC adds b986a76 Rename ArrayRef::keep_front / keep_back to take_front / take_back. adds 9c80b35 ADT: Split ilist_node_traits into alloc and callback, NFC adds e046d5c Fix unit test after function name change. adds a2a31ca Support: add some more ELF constants adds b899d19 llvm-readobj: add support for printing GNU Notes adds 8be91b5 GlobalISel: forbid physical registers on generic MIs. adds a55b262 CodeGen: Fixup for r280128, since GCC isn't as permissive as Clang adds b16d4d3 ELFDumper: Unversioned symbols must not have trailing @ adds 7ebede9 Re-instate recent RPC updates (r280016, r280017, r280027, r28 [...] adds 90f82fc IntrArgMemOnly is only defined (and current AA machinery only [...] adds 99edeba [COFFObjectFile] Ignore broken symbol table adds 67a6032 [LoopVectorizer] Predicate instructions in blocks with severa [...] adds 911b0b8 Revert "ELFDumper: Unversioned symbols must not have trailing @" adds d7a5ad2 [libfuzzer] simplified unit truncation; do not write trunc it [...] adds 605a81a AMDGPU: Relax SGPR asm constraint register class adds 7be2d15 GlobalISel: combine extracts & sequences created for legalization adds deb6ead llvm-readobj: speculative fix for MSVC adds b8c2c1d Next set of additional error checks for invalid Mach-O files [...] adds 3449d54 [CMake] Ensure that compiler-rt is added first adds e9f64d4 [ORC][RPC] Fix some bugs in the callB primitive. adds 4cbb126 Add a test file, macho-invalid-dysymtab-extreloff-nextrel, I [...] adds 0887fc5 [codeview] Remove redundant TypeTable lookup adds ea62cfa [InstCombine] add tests to show type limitations of InsertRan [...] adds 74a597b [LoadStoreVectorizer] Change VectorSet to Vector to match hea [...] adds 751f50e [llvm-cov] Drop redundant "No." suffix in a column title adds 1a31aef [InstCombine] clean up InsertRangeTest; NFCI adds b6a1398 [Coroutines] Part 10: Add coroutine promise support. adds 982b9c9 [PowerPC] Don't spill the frame pointer twice adds 8b6ce01 [Loads] Properly populate the visited set in isDereferenceabl [...] adds 74727ab [XRay] Support multiple return instructions in a single basic block adds bcb836f [X86] Regenerate a test using update_llc_test_checks.py. adds 2699e28 [AVX-512] Add test cases for masked floating point logic oper [...] adds f903ac6 [AVX-512] Add patterns to select masked logical operations if [...] adds da47983 [Coverage] Make sorting criteria for CounterMappingRegions local. adds 0bc610c [X86][SSE] Improve awareness of fptrunc implicit zeroing of u [...] adds 5ae3447 [SimplifyCFG] Tail-merge calls with sideeffects adds d308206 [SimplifyCFG] Change the algorithm in SinkThenElseCodeToEnd adds e786823 [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches adds 87aeaac [SimplifyCFG] Improve FoldValueComparisonIntoPredecessors to [...] adds 1c6ea1a [SimplifyCFG] Add a workaround to fix PR30188 adds 5b50326 AMDGPU/SI: Handle aliases in AMDGPUAlwaysInlinePass adds d5c06d1 [SimplifyCFG] Fix bootstrap failure after r280220 adds aca9e6b Typo fixes. NFC adds 9cbda65 Use abstraction in AArch64AsmPrinter::lowerSTACKMAP. NFCI adds 0ba92ab Revert "[SimplifyCFG] Fix bootstrap failure after r280220" adds 3d40b2a Revert "[SimplifyCFG] Add a workaround to fix PR30188" adds 85dac9a Revert "[SimplifyCFG] Handle tail-sinking of more than 2 inco [...] adds 8f65479 Revert "[SimplifyCFG] Change the algorithm in SinkThenElseCodeToEnd" adds 1012af3 Changing a code block to text because Sphinx does not like it [...] adds 7ae397d Revert "[SimplifyCFG] Improve FoldValueComparisonIntoPredeces [...] adds bafb383 Fix comments about IndirectBrInst in Instructions.h adds 3061990 Fixed spill stack objects are mutable adds 6050932 Clang patch r280064 introduced ways to set the FP exceptions [...] adds da4a9a6 Changing a code block to text because Sphinx does not like it [...] adds 5f960b8 [SLP] Arguments should be camel case, and start with an upper [...] adds acfacb0 [X86][SSE] Improve awareness of (v)cvtpd2ps implicit zeroing [...] adds 327ae58 [statepoints][experimental] Add support for live-in semantics [...] adds 57e1968 [codeview] Emit vtable shape information adds 33f98b3 [LTO] Fix common test to reflect r279911 and move to X86 subd [...] adds b62ba77 s/static inline/static/ for headers I have changed in r279475. NFC. adds c163bf5 [lib/LTO] Factor out logic for running passes. adds 71255df [SLP] Sink debug after checking for matching types/opcode. adds eb8a4ab [LangRef] Clarify !invariant.load semantics. adds 8f1c575 [SLP] Update the debug based on Michael's suggestion. adds 5fc0cc8 [EarlyCSE] Allow forwarding a non-invariant load into an inva [...] adds f2e0338 Next set of additional error checks for invalid Mach-O files [...] adds ae9896f Add an optional parameter with a list of undefs to extendToIndices adds cfe0cf0 Fix indent. NFC. adds aa4eb89 [DiagnosticInfo] Add a diagnostic class for the fallback of ISel. adds 8e21d40 [ResetMachineFunction] Emit the diagnostic isel fallback when asked. adds e41c902 [TargetPassConfig] Add a hook to tell whether GlobalISel shou [...] adds b3ee42e AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is at leas [...] adds 5cedb44 [Hexagon] Deal with undefs when extending live intervals adds 505a214 Actually check for the diagnostic to be emitted! adds aa61209 [EarlyCSE] Optionally use MemorySSA. NFC. adds dbd67f6 [LoopInfo] Add verification by recomputation. adds ebc9efb [InstCombine] change insertRangeTest() to use APInt instead o [...] adds 0d4df2a [WebAssembly] Disable folding of GA+reg into load/store const [...] adds d3b78e0 GlobalISel: use G_TYPE to annotate physregs with a type. adds 4d1149d [codeview] Add TypeVisitorCallbackPipeline. adds 8cf15c6 AMDGPU: Refactor frame lowering adds 6b025a0 AMDGPU: Use copy instead of mov during frame lowering adds f97e3d8 AMDGPU: Fix introducing stack access on unaligned v16i8 adds bfcd22b [InstCombine] allow icmp (div X, Y), C folds for splat consta [...] adds 8aee946 [InstCombine] allow icmp (shr exact X, C2), C fold for splat [...] adds 27e101d Revert "Add an optional parameter with a list of undefs to ex [...] adds 01601df Add asm.js-style setjmp/longjmp handling for wasm adds 4fc126d [CMake] Increase stack size to 16MiB for all mingw executables. adds 9df3fb3 Fix the MSVC 2013 build by using Elf_Word instead of making a [...] adds 0b94abf Add -fprofile-dir= to clang. adds 0ae82de [codeview] Have visitTypeBegin return the record type. adds 46b443d Add cast to appease windows builder. Fixes build break introd [...] adds ba2b231 Support: Avoid errors with LLVM_FALLTHROUGH in clang 3.6 and [...] adds 2a3f18e Revert "Add asm.js-style setjmp/longjmp handling for wasm" adds 31a52c2 [XRay][NFC] Promote isTailCall() as virtual in TargetInstrInfo. adds 501485f [libFuzzer] add -minimize_crash flag (to minimize crashers). [...] adds d17ccfb [XRay] Detect and emit sleds for sibling/tail calls adds 1d15404 [NFC] Remove unnecessary comment adds f4e1029 [SimplifyCFG] Improve FoldValueComparisonIntoPredecessors to [...] adds ee728f8 [LLVM/Support] - Create no-arguments constructor for llvm::Regex adds 5c88a87 Commit of forgotten header for r280339 "[LLVM/Support] - Crea [...] adds 16a76ce [SimplifyCFG] Fix nondeterministic iteration order adds e1ceee0 [Support] Fix a warning introduced in r280339 due to the memb [...] adds f73c9c1 Add a counter-function insertion pass adds 8127683 [AMDGPU] Scalar Memory instructions TD refactoring adds 77579f5 Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, f [...] adds f991e38 [SimplifyCFG] Change the algorithm in SinkThenElseCodeToEnd adds 89ea36c [IR] Properly handle escape characters in Attribute::getAsString() adds e0daa1e Add an optional parameter with a list of undefs to extendToIndices adds f37c8a6 [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches adds cea4c9f Optimized FMA intrinsic + FNEG , like -(a*b+c) adds fc03914 [Hexagon] Deal with undefs when extending live intervals adds 36ff41a [InstCombine] remove fold of an icmp pattern that should neve [...] adds 0f970f8 [CMake] Fix LLVM_ENABLE_EH and LLVM_ENABLE_RTTI on MSVC adds dbc6964 [mips] interAptiv based generic schedule model adds 49aa029 [X86][SSE] Dropped (V)CVTPD2PS intrinsic patterns now that it [...] adds f27163f [mips] Include missed file from previous commit adds 6f45ebf [EarlyCSE] Change C API pass interface for EarlyCSE w/ MemorySSA adds 51d3515 [CMake] Revive LLVM_*_DIRS variables adds 23bc604 [lit] Use multiprocessing by default on Windows adds 97a9f60 AMDGPU/SI: MIMG TD Refactoring. adds 1b35037 [DAGCombine] Don't fold a trunc if it feeds an anyext adds 6ece050 [codeview] Properly propagate the TypeLeafKind through the pipeline. adds 8dabfb7 [LV] Move VectorParts allocation and mapping into PHI widening (NFC) adds add0a5d Rename some variables to have meaningful names. NFC. adds 816c475 [CMake] Connecting check-all and test-depends targets correctly adds a964a28 [lib/LTO] Simplify a bit. NFCI. adds 7f885e7 AMDGPU: Add runtime metadata for pointee alignment of argument. adds fa2569c [X86] Loosen memory folding requirements for cvtdq2pd and cvt [...] adds 78e359c [InstCombine] add tests to show potential shuffle+insert folds adds af1a999 [LV] Use ScalarParts for ad-hoc pointer IV scalarization (NFCI) adds 2ae7de2 Fix the ASan fuse-lld.cc test after LLD r280012 adds 3b19074 GlobalISel: add a G_PHI instruction to give phis a type. adds 1879d5c bugpoint: clang-format and modernize comments in ListReducer. NFC adds d5f9cd9 [WebAssembly] Add asm.js-style setjmp/longjmp handling for wa [...] adds 5cf52da [SelectionDAG] Generate vector_shuffle nodes for undersized r [...] adds 2c8b23f Make the coding standards a bit more clear that we prefer the [...] adds f71b301 [Legalizer] Don't throw away false low half when expanding GT [...] adds 910602a Refactor LICM pass in preparation for LoopSink pass. adds d21744e Refactor replaceDominatedUsesWith to have a flag to control w [...] adds 7bb9af1 Refactor LICM to expose canSinkOrHoistInst to LoopSink pass. adds 79dbe29 [SelectionDAGBuilder] Add const to relevant places adds 7946689 Explicitly require DominatorTreeAnalysis pass for instsimplify pass. adds c426463 [PowerPC] Don't consider fusion in PPC64 address-formation peephole adds 67a060f [PowerPC] Don't apply the PPC64 address-formation peephole fo [...] adds c367442 [CFGPrinter] Display branch weight on the edges adds 6252565 Try to fix some temp file leaks in SupportTests, PR18335 adds b4c86c9 [PM] (NFC) Refactor the CGSCC pass manager tests to use lambd [...] adds 6a70116 Fix a real temp file leak in FileOutputBuffer adds 9d2f1f8 [PM] (NFC) Split the IR parsing into a fixture so that I can [...] adds 291528a [PM] Add a unittest for invalidating module analyses with an [...] adds 5a1da4f IfConversion: Don't count branches in # of duplicates. adds ef63f7a raw_pwrite_stream_test.cpp: _putenv_s() may be assumed as win [...] adds 388e8b9 bugpoint: clang-format all of bugpoint. NFC adds 5aa6c69 llvm/test/Transforms/GCOVProfiling/three-element-mdnode.ll: U [...] adds 6cae2f1 revert r280432: adds fa2c5e7 revert r280429 and r280425: adds 9f423e5 [PowerPC] Add a pattern for a runtime bit check adds f931a64 [lit] Fail testing if a googletest executable crashes during [...] adds b7a37e9 [PowerPC] hasAndNotCompare should return true adds af1f616 Add missing &. NFC. adds 62c102c [ORC] Fix some missing fields in OrcRemoteTargetClient's move [...] adds 8ebfd86 [Docs] Fix a couple of typos in the Error/Expected docs. adds 08f7f18 [Docs] Fix another typo in the Error/Expected docs. adds 8f635c0 [AVX-512] Add NoVLX Predicates to some patterns so they don't [...] adds a3459cf [X86] Strengthen some SDNode type constraints. adds 3409bf2 [AVX-512] Add execution domain fixing for logical operations [...] adds dddb19d [AVX-512] Add more patterns for masked and broadcasted logica [...] adds 5b553d0 [AVX-512] Remove floating point logical operation instrinsics [...] adds a11c5f2 [AVX-512] Move tests for masked floating point logical operat [...] adds 87afa50 [SimplifyCFG] Add a workaround to fix PR30188 adds 677dd5b [llvm-readobj] - Teach readobj to print DT_AUXILIARY dynamic [...] adds e1bd92b [Support] - Fix possible crash in match() of llvm::Regex. adds b1ce3c4 [InstCombine] Add test for insertelementinsts with constants. adds 9d35b5c [PM] Try to fix an MSVC2013 failure due to finding a template [...] adds 0c18303 Fixed a typo (LLVM/Support/CFG.h -> LLVM/IR/CFG.h) adds 997fee1 [DAGcombiner] Fix incorrect sinking of a truncate into the op [...] adds 74f53f3 [instsimplify] Fix incorrect folding of an ordered fcmp with [...] adds 7fb6e6b fix documentation comments; NFC adds 341f684 Simplify code a bit. No functional change intended. adds d768ea4 [LV] Ensure reverse interleaved group GEPs remain uniform adds 4b602e7 [WebAssembly] Update known test failures adds 5dd7b75 [lit] Clean up temporary files created by tests adds b60590f Quick fix to make LIT_PRESERVES_TMP work again adds a92ab03 [lib/LTO] Simplify. No functional change intended. adds ef2c802 [InsttCombine] fold insertelement of constant into shuffle wi [...] adds c306b61 Split the store of a wide value merged from an int-fp pair in [...] adds 7f88dad Fix up comment from r280442, noticed by Justin. adds d5d75c5 IfConversion: Fix bug introduced by rescanning diamonds. adds 482ae0a IfConversion: Add assertions that both sides of a diamond don [...] adds 740c3d2 [codeview] Use the correct max CV record length of 0xFF00 adds f9e0892 AMDGPU: Reorganize store tests adds 1c5de87 AMDGPU/R600: Expand unaligned writes to local and global AS adds 454a60a [SLP] Don't pass a global CL option as an argument. NFC. adds b19628e [InstCombine] auto-generate assertions for tighter checking adds 57c58d3 Do not consider subreg defs as reads when computing subrange [...] adds 3fb8936 Setting fp trapping mode and denormal type: this an improveme [...] adds bf9a94a AMDGPU/R600: EXTRACT_VECT_ELT should only bypass BUILD_VECTOR [...] adds 5bcf846 [Sparc] Mark i128 shift libcalls unavailable in 32-bit mode. adds bcc57c0 [PowerPC] For larger offsets, when possible, fold offset into [...] adds aa13c47 [Profile] handle select instruction in 'expect' lowering adds c8582b7 [codeview] Make FieldList records print as a yaml sequence. adds 0c194fe lit: print process output, if getting the list of google-test [...] adds 18935b9 gitignore: ignore VS Code editor files adds e771670 Make sure to maintain register liveness when generating predi [...] adds 02f4e31 (LLVM part) Implement MASM-flavor intel syntax behavior for i [...] adds fe681a8 [PowerPC] Add support for the extended dcbf form and mnemonics adds 1211eb0 [PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev adds 4ee00f7 ADT: Fix up IListTest.privateNode and get it passing adds 31a5b87 ADT: Remove external uses of ilist_iterator, NFC adds 6807457 ADT: Rename NodeTy to T in iplist/ilist template parameters adds 0bb0bae Fix buildbot error. adds fe32ecc ADT: Split out iplist_impl from iplist, NFC adds 0d65f1d ADT: Do not inherit from std::iterator in ilist_iterator adds f86e7ee [PowerPC] Support asm parsing for bc[l][a][+-] mnemonics adds 87c2d47 ADT: Use std::list in SparseBitVector, NFC adds b210b2b Revert r280549. adds 3be2bb7 Make lit/util.py py3-compatible. adds 1094358 [AVX-512] Add EVEX encoded VPCMPEQ and VPCMPGT to the load fo [...] adds 59ff709 Improve debug error message with register name adds c2c79a1 AMDGPU: Fix spilling of m0 adds 6acb49a AMDGPU: Do basic folding of class intrinsic adds c280d74 AMDGPU: Fix an interaction between WQM and polygon stippling adds f9f3b70 AMDGPU: Reduce the duration of whole-quad-mode adds f611763 [AVX-512] Mark EVEX encoded vpcmpeq as commutable just like i [...] adds 7a46f96 [AVX-512] Add integer ADD/SUB instructions to load folding ta [...] adds d6b6798 AMDGPU: Fix adding duplicate implicit exec uses adds d55f315 AMDGPU: Set sizes of spill pseudos adds 9101366 Strip trailing whitespace adds 1c224c0 Fix ThinLTO crash with debug info adds da48846 [Profile] preserve branch metadata lowering select in CGP adds 1f44212 Cleanup : Use metadata preserving API for branch creation adds 1ce4369 [X86] Combine some of the strings in autoupgrade code. adds 37c54c6 Fix inliner funclet unwind memoization adds d88c98e [AVX-512] Remove masked integer add/sub/mull intrinsics and u [...] adds 204ba88 [PowerPC] Zero-extend constants in FastISel adds e99c574 Test commit. adds c6f214b [ExecutionEngine] Move ObjectCache::anchor from MCJIT to Exec [...] adds cc6b354 [InstCombine] Preserve llvm.mem.parallel_loop_access metadata [...] adds 443069c [LCG] A NFC refactoring to extract the logic for doing a post [...] adds 34a0f7a [LCG] Clean up and make NDEBUG verify calls more rigorous wit [...] adds fcaf12c [PM] Revert r280447: Add a unittest for invalidating module a [...] adds 1d5ab2b Strip trailing whitespace adds e1ae1c8 EOL fixes adds 02eff5c revert r279960. https://llvm.org/bugs/show_bug.cgi?id=30249 adds f21bb8d [PowerPC] During branch relaxation, recompute padding offsets [...] adds e57e8b4 [InstCombine] recode icmp fold in a vector-friendly way; NFC adds 1af5878 [ORC] Fix an unfinished comment. adds 4668efb [X86][SSE] Regenerate fcmp/uitofp combine tests adds fa79def [X86] Regenerate trunc-store legalization test adds b80c630 [ORC] Clone module flags metadata into the globals module in [...] adds 3a32e24 [AVX-512] Remove 128-bit and 256-bit masked floating point ad [...] adds e330ad3 [X86] Regenerate x64 mmx/f64 return value tests adds 2eb4a16 [AVX-512] Add EVEX encoded scalar FMA intrinsic instructions [...] adds 7ae81d5 [InstCombine] allow icmp (and X, C2), C1 folds for splat cons [...] adds 2b9ec08 lit/util.py: Another fix for py3. adds d02e8e5 [CMake] [OCaml] Allow building OCaml bindings out of tree. adds bfa3e95 [X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. D [...] adds 384a721 [X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. adds ac396ea [Coroutines] Part11: Add final suspend handling. adds 481ecf2 [Target] Remove the AvailableRegClasses vector from TargetLow [...] adds bda8c85 [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit [...] adds e888613 [X86] Make some static arrays of opcodes const and shrink to [...] adds 65e0a96 [AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Exp [...] adds af86df2 [Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc} adds b01d8d2 [AMDGPU] Refactor FLAT TD instructions adds 7e3e982 [WebAssembly] Unbreak the build. adds bbe0f05 [SimplifyCFG] Add test for sinking inline asm in if/else adds 70de308 [X86][SSE] Regenerate odd shuffle tests with common prefixes adds 2325326 CODE_OWNERS: bring my entry up to date adds 70794a5 [X86][SSE] Add test cases for PR29079 adds bf482f9 [X86][SSE] Add test cases for PR29078 adds a8cbd72 [AVX-512] Integrate mask register copying more completely int [...] adds 7c60fc0 [lit] Downgrade error to warning on gtest crashes during discovery. adds 6704841 [InstCombine] revert r280637 because it causes test failures [...] adds 47e6904 [InstCombine] don't assert that division-by-constant has been [...] adds 5b6d16c [Coroutines] Part12: Handle alloca address-taken adds ea437ed fix FileCheck variables for test added with r280677 adds e4bd2be [X86] Update fast-isel vector load test to have more 256 and [...] adds d844741 [X86] Update fast-isel store test to have more 256 and 512-bi [...] adds 610e45c [AVX-512] Teach fastisel load/store handling to use EVEX enco [...] adds 7471df8 CodeGen: ensure that libcalls are always AAPCS CC adds a9a5240 [AVX-512] Fix v8i64 shift by immediate lowering on 32-bit targets. adds 8cd45dd Fix DensetSet::insert_as() for MSVC2015 (NFC) adds 454e9fc DebugInfo: use strongly typed enum for debug info flags adds 9a67ec1 [LTO] Constify (NFC) adds c581dfb Revert "DebugInfo: use strongly typed enum for debug info flags" adds 02c3a66 ARM: workaround bundled operation predication adds 3023eeb bugpoint: Stop threading errors through APIs that never fail adds 79a93a6 Revert "bugpoint: Stop threading errors through APIs that nev [...] adds 8f30c1d [X86] Fix indentation. NFC adds 8a2aa54 [X86] Remove unused encoding from IntrinsicType enum. adds def05b4 [AVX-512] Add a test case to show that we don't select masked [...] adds 899add2 [AVX-512] Fix masked VPERMI2PS isel when the index comes from [...] adds 4b1b5a4 [RegisterScavenger] Remove aliasing registers of operands fro [...] adds d9478f8 DebugInfo: use strongly typed enum for debug info flags adds 6ee91ac [PPC] Claim stack frame before storing into it, if no red zon [...] adds 7e4471c [mips] Tighten FastISel restrictions adds c548b68 [Sparc][Leon] Corrected supported atomics size for processors [...] adds 7ba1553 Fix for Bindings/Go/go.test after patch r280700 adds 6050b76 [JumpThreading] Only write back branch-weight MDs for blocks [...] adds 854572d [SelectionDAG] Simplify extract_subvector( insert_subvector ( [...] adds 01dd3d9 Formatting with clang-format patch r280700 adds a68463e [RDF] Ignore undef use operands adds d8090ae bugpoint: Return Errors instead of passing around strings adds 3693f11 Fix comment formatting for DebugInfoFlags.def adds 4b3bd15 [MCTargetDesc] Delete dead code. Found by GCC7 -Wunused-function. adds 99f377b fix formatting; NFC adds ec44cfd Add an c++ itanium demangler to llvm. adds 25c97c0 [AArch64] Adjust the scheduling model for Exynos M1. adds edc04f3 [AArch64] Adjust the scheduling model for Exynos M1. adds 102e8d5 [AArch64] Adjust the scheduling model for Exynos M1. adds f73cd14 [llvm-cov] Add the "Go to first unexecuted line" feature. adds 6b15e98 Fix ItaniumDemangle.cpp build with MSVC 2013 adds 9493fa9 AMDGPU : Add XNACK feature to GPUs that support it. adds 2ec1430 AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immedia [...] adds fe2ae4c Try to fix a circular dependency in the modules build. adds 1f99c41 [AMDGPU] Wave and register controls adds dbbdf44 [CMake] Cleanup LLVM_OPTIMIZED_TABLEGEN adds c87867f [AMDGPU] Wave and register controls adds fec7b48 Avoid using alignas and constexpr. adds 84f34c0 [llvm-cov] Add the project summary to the text coverage repor [...] adds 5431231 Explicitly require DominatorTreeAnalysis pass for instsimplify pass. adds ff7a0df [llvm-cov] Clean up the summary class, delete dead code (NFC) adds 423e0ff [llvm-cov] Use colors consistently in the summary adds 8d0ebe9 [DAGCombine] More fixups to SETCC legality checking (visitAND [...] adds 8eddc0f Re-add "Make FieldList records print as a YAML sequence" adds 19c8b5e [opt] Remove an unused argument to runPassPipeline(). adds 5c494e7 [LTO] Rename variables to be more explicative. adds 36a0b39 Fix typo in comment, NFC adds 4ccc33a Revert "CodeGen: ensure that libcalls are always AAPCS CC" adds 83d6e11 [AVX-512] Add support for commuting masked instructions in fi [...] adds 4cf44f1 [X86] Add hasSideEffects=0 to some instructions. adds 774415b Remove unnecessary call to getAllocatableRegClass adds 1da68f6 AMDGPU: Make some scalar instructions commutable adds 7840500 AVX512F: FMA intrinsic + FNEG - sequence optimization adds 21c68fa [PowerPC] Fix address-offset folding for plain addi adds 40fa86f [SimplifyCFG] Check PHI uses more accurately adds 1317eef [CMake] Use CMake's default RPATH for the unit tests adds 80fedcb [SimplifyCFG] Update workaround for PR30188 to also include loads adds e50466a [SimplifyCFG] Followup fix to r280790 adds 51cc6bb [EfficiencySanitizer] Adds shadow memory parameters for 40-bi [...] adds c7d7511 [mips] Disable the TImode shift libcalls for 32-bit targets. adds 17c896a Revert "[EfficiencySanitizer] Adds shadow memory parameters f [...] adds fd11478 [InstCombine][SSE4a] Fix assertion failure caused by unsafe d [...] adds 2fdf2bf [InstCombine][SSE4a] Fix assertion failure in the insertq/ins [...] adds ba3ea4d [ARM] Lower UDIV+UREM to UDIV+MLS (and the same for SREM) adds 9313182 [X86][SSE] Added and+or combine tests currently failing with vectors adds b362b6e [X86][SSE] Added and+or+zext combine tests for known bits of vectors adds 56463dd [X86][SSE] Added or combine tests for known bits of vectors adds 959abb8 Regenerate vector bitcast folding tests using update_test_checks.py. adds 0639c00 Fix typo in test - it should be masking bits0-15 not bit16 adds 05601b4 [x86] move combines of 'select of 2 constants' to its own fun [...] adds 600740b [LSV] Use the original loads' names for the extractelement in [...] adds e760d89 [LoopInterchange] Improve debug output. NFC. adds 452b6b2 [LoopInterchange] Improve debug output. NFC. adds eadc14f [codeview] Add new directives to record inlined call site line info adds 6874fa8 AMDGPU: Add hidden kernel arguments to runtime metadata adds fab897d [lib/LTO] Add a way to run a custom pipeline adds 4a83266 X86: Fold tail calls into conditional branches where possible [...] adds c4c2318 CodeGen: ensure that libcalls are always AAPCS CC adds 371bac0 Typo. NFC. adds 9107e64 Add more triple to conditional-tailcall.ll test adds ebe55c6 Don't reduce the width of vector mul if the target doesn't su [...] adds 145ae71 AMDGPU: Remove a useless variable which caused build failure [...] adds a804c5a Rename test pr30298.ll to shrink_vmul_sse.ll, to make the nam [...] adds 78e95fa [CUDA] Expand upon --cuda-gpu-arch flag in CompileCudaWithLLVM doc. adds 188c78b [CUDA] Call it "CUDA", not "CUDA C/C++" in our docs. adds f1708bc [CUDA] Simplify build/install instructions in CompileCudaWith [...] adds 80708af [RDF] Introduce "undef" flag for ref nodes adds 9c0826c Don't reuse a variable name in a nested scope. NFC. adds 4ecf8b9 [RDF] Fix liveness analysis for phi nodes with shadow uses adds e61b182 [CUDA] Move AXPY example into gist. adds 5b033da [CUDA] Fix typo in link in CompileCudaWithLLVM. adds 350a7a4 [InstCombine] allow icmp (and X, C2), C1 folds for splat cons [...] adds 22c45e1 Shift-left (ISD::SHL) operation crashes on "DAG Legalization" [...] adds 16d3f88 [LoopUnroll] Correct a debug message. NFC. adds 9e7800b [SimplifyCFG] Don't try to create metadata-valued PHIs adds 70425af [CUDA] Further reformat "invoking clang" section of CompileCu [...] adds 6676095 [CUDA] Clarify that -l and -L only need to be passed when lin [...] adds f0bb43f [CUDA] Rework "optimizations" and "publication" section in Co [...] adds 774d87e [InstCombine] use m_APInt to allow icmp (and (sh X, Y), C2), [...] adds f8002f1 [asan] Avoid lifetime analysis for allocas with can be in amb [...] adds a7ad004 [thinlto] Deleted unused test file adds f555e26 Revert "[asan] Avoid lifetime analysis for allocas with can b [...] adds 1c13d2b IR: Remove Value::intersectOptionalDataWith, replace all call [...] adds 6037ae7 Revert "[thinlto] Deleted unused test file" adds 1d54212 Deleted right file adds 339ade7 [XRay] ARM 32-bit no-Thumb support in LLVM adds 0b559dd [XRay] Remove unused variable adds 6d2157d [AA] Fix typo in comment (s/hase/has). adds 2a93bda [CGP] Be less conservative about tail-duplicating a ret to al [...] adds a57be10 [llvm-cov] Drop the longest common filename prefix from summaries adds d2e36ca [llvm-cov] Use less space to describe source names adds 837c30f [llvm-cov] Disable zlib compression in a test input, unbreaks bots adds d9fa490 [LoopUnroll] Properly update loop-info when cloning prologues [...] adds e53b49a Revert "[LoopUnroll] Properly update loop-info when cloning p [...] adds 52bc7ab [asan] Avoid lifetime analysis for allocas with can be in amb [...] adds 09e9256 [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add [...] adds ad84cf4 Revert "[ARM] Lower UDIV+UREM to UDIV+MLS (and the same for SREM)" adds 707719e [DAGCombiner] Enable AND combines of splatted constant vectors adds d88990b [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits a [...] adds 210e77b [Thumb1] Fix cost calculation for complemented immediates adds ac84ac0 [Thumb1] AND with a constant operand can be converted into BIC adds 7442ca4 [SDAGBuilder] Don't create a binary tree for switches in mins [...] adds 08450b5 [ARM XRay] Try to fix Thumb-only failure adds 035ff49 revert r280427 adds 1a53e07 Give an x86 assembler test a triple adds 88e07a9 Remove restriction that 'sret' must be on the first parameter adds e3aa0d9 [TableGen] AsmMatcher: Add AsmVariantName to Instruction class. adds c87eb16 [Coverage] Delete some dead code (NFC) adds 0cd49c0 [InstCombine][X86] Regenerate insertps combine tests adds 2a7d3fa [InstCombine][X86] Regenerate vperm2f128/vperm2i128 combine tests adds f3c6524 [InstCombine][X86] Regenerate masked memory op combine tests adds fcc57ae Add unittest for r280760 adds e0563b1 [InstCombine] return a vector-safe true/false constant adds b91e524 [LoopDataPrefetch] Use range based for loop; NFCI adds 86159cb Revert "[XRay] ARM 32-bit no-Thumb support in LLVM" adds d764af3 AMDGPU: Support commuting with immediate in src0 adds a50ca9f AArch64 .arch directive - Include default arch attributes wit [...] adds c0196eb AMDGPU: Try to commute when selecting s_addk_i32/s_mulk_i32 adds 3358dc4 [Hexagon] Expand sext- and zextloads of vector types, not jus [...] adds 1bc1003 AMDGPU: Sign extend constants when splitting them adds 684da72 [YAMLIO] Add the ability to map with context. adds 3d9234a [pdb] Make YamlTypeDumperCallbacks reuse *this. adds 99a1cd6 [LV] Don't mark pointers used by scalarized memory accesses uniform adds 111f4fb [llvm-cov] Fix issues with segment highlighting in the html view adds 01b876d [RDF] Further improve handling of multiple phis reached from shadows adds 92544c4 [InstCombine] regenerate checks adds 97ea58e [LV] Ensure proper handling of multi-use case when collecting [...] adds 53d514f [InstCombine] regenerate checks adds 539e8b4 Remove debug info when hoisting instruction from then/else branch. adds 10c8c3c [libFuzzer] add missing docs adds 8aad291 llvm-objdump: add missing ) in help output, NFC adds e0cbb68 .clang-tidy: parameters and members should be CamelCased. adds d837ce2 Win64: Don't use REX prefix for direct tail calls adds 74990a5 [X86] Add more baseline tests for "irregular" shuffles. NFC. adds 0f6a0eb [X86] Tighten up a comment which confused x64 ABI terminology. adds 05e1dea [libFuzzer] remove use_traces=1 since use_value_profile seems [...] adds f539109 [llvm-cov] Speculate fix for a Windows-only test (NFC) adds 006e320 [llvm-cov] Add an API to prepare file reports (NFC) adds 85e096d [llvm-cov] Constify some methods (NFC) adds 84dc751 [llvm-cov] Emit a summary in the report directory's index adds beb8233 [AVX-512] Add more integer vector comparison tests with loads [...] adds a122378 [AVX-512] Add VPCMP instructions to the load folding tables a [...] adds ddc2d44 [libFuzzer] remove unneeded call adds 4475d67 [libFuzzer] improve -print_pcs to not print new PCs coming fr [...] adds 7f692c7 Rationalise the attribute getter/setter methods on Function a [...] adds 6ff9c19 [Coroutines] Part13: Handle single edge PHINodes across suspends adds 847743b [Sparc][LEON] Unit test for CASA instruction supported by som [...] adds 43cc6f8 [mips] Fix c.<cc>.<fmt> instruction definition. adds 93211d9 [AMDGPU] Assembler: match e32 VOP instructions before e64. adds c682994 [Thumb1] Teach optimizeCompareInstr about thumb1 compares adds 442deaa [AMDGPU] Assembler: rename amd_kernel_code_t asm names accord [...] adds 80f518b Revert "[mips] Fix c.<cc>.<fmt> instruction definition." adds 59282d3 GlobalISel: move type information to MachineRegisterInfo. adds bc6470c GlobalISel: fix comments and add assertions for valid instructions. adds 3c6f3f0 GlobalISel: remove G_TYPE and G_PHI adds 5349caf [Thumb] Select (CMPZ X, -C) -> (CMPZ (ADDS X, C), 0) adds 31bcc1e [SelectionDAG] Ensure DAG::getZeroExtendInReg is called with [...] adds f53c395 [ARM] icmp %x, -C can be lowered to a simple ADDS or CMN adds b2500d2 [ARM] ADD with a negative offset can become SUB for free adds b68584d [Sparc][LEON] Removed the parts of the errata fixes implement [...] adds 03d3176 AMDGPU] Assembler: better support for immediate literals in a [...] adds a71022e [SelectionDAG] Fix two issues with SDNode::getRawSubclassData(). adds bb15e0c Attempt to fix static_asserts in SelectionDAGNodes.h that MSV [...] adds 6128d7f [InstCombine] add tests to show pattern matching failures due [...] adds a8f2db5 [Bitcode] Add compatibility test for the 3.9 release adds a8b8839 [codeview] Don't assert if the array element type is incomplete adds 0a2fb4a Move the ocaml_all target into the Misc folder for cleanliness; NFC. adds 3beac7c [llvm-cov] Handle native paths correctly in the text index adds be73fbc [pdb] Write PDB TPI Stream from Yaml. adds 9af2b5e [libFuzzer] one more puzzle, value_profile cracks it in a second adds 27d122c [pdb] Pass CVRecord's through the visitor as non-const references. adds 8b2faaa Fix -Wunused-variable for non-assert build. adds 892ff5d [pdb] Add command line options for dumping individual streams [...] adds 5e2e757 [llvm-cov] Try to fix the native_separators.c test some more adds 18f2ff8 Fix another -Wunused-variable for non-assert build. adds 961ef79 Do not widen load for different variable in GVN. adds 07e4072 [llvm-cov] Remove some asserts in the html renderer (NFC) adds 6ad7067 [pdb] Print out some more info when dumping a raw stream. adds 6ecd500 AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte [...] adds 8dae05a AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type. adds d87d83d Add a lower level zlib::uncompress. adds 1f4e68f [cmake] Export gtest/gtest_main and its dependencies via a sp [...] adds 7deb7e7 [cmake] Fix a stale comment from an earlier version of r281085. NFC. adds a757788 ARM: move the builtins libcall CC setup adds 8458ab1 [NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc. adds 65ddbec Create phi nodes for swifterror values at the end of the phi [...] adds d9c5bfb Enable in-tree builds of parallel-libs. adds b0cab11 [X86] Regenerate test. NFC. adds 60719d6 [Hexagon] Fix disassembler crash after r279255 adds 6bca1ae [X86][XOP] Fix VPERMIL2PD mask creation on 32-bit targets adds fb49daf [libFuzzer] one more puzzle for value profile adds 1a60ab8 [InstCombine] use m_APInt to allow icmp ult X, C folds for sp [...] adds 586b777 [gold] Test that we handle invalid directory correctly. adds 7474f82 LSV: Fix incorrectly increasing alignment adds 2c9e9a6 [libFuzzer] use sizeof() in tests instead of 4 and 8 adds d5a5e90 AMDGPU: Run LoadStoreVectorizer pass by default adds b6bf353 X86: Fold tail calls into conditional branches also for 64-bi [...] adds 8ad92ff Inliner: Don't mark swifterror allocas with lifetime markers adds 3843a13 AMDGPU: Fix immediate folding logic when shrinking instructions adds 1c3a1e2 Remove dead code in the SelectionDAG headers (NFC) adds 7942244 [libFuzzer] print a visible message if merge fails due to a crash adds 74ad0cf [libFuzzer] don't print help for internal flags adds e7555f0 [CodeGen] Rename MachineInstr::isInvariantLoad to isDereferen [...] adds c4644d2 [asan] Add flag to allow lifetime analysis of problematic allocas adds da28e63 AMDGPU: Fix scheduling info for spill pseudos adds 10eb5d5 AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndex adds 05082bd [libFuzzer] print a failed-merge warning only in the merge mode adds b7ef200 [WebAssembly] Fix typos in comments adds 2752a28 [LTO] Handle null GV in Symbol object adds 68d7a57 [gold/LTO] Add test case for r281134 adds c220fde [AMDGPU] Refactor MUBUF/MTBUF instructions adds 14e6992 We also need to pass swifterror in R12 under swiftcc not only [...] adds 792a8ea [InstCombine] rename and reorganize some icmp folding functions; NFC adds e117e50 [InstCombine] clean up foldICmpBinOpEqualityWithConstant / fo [...] adds 631d14e ADT: Use typedefs for ilist_base and ilist_node_base, NFC adds 2b4de80 ADT: Move ilist_node_access to ilist_detail::NodeAccess... adds df708a5 Add an isSwiftError predicate to Value adds 17648b3 InstCombine: Don't combine loads/stores from swifterror to a [...] adds ce19c1c [llvm-cov] Minor visual tweaks for html reports adds a8edd76 [llvm-cov] Move the 'jump to first unexecuted line' link adds 10c97f0 It should also be legal to pass a swifterror parameter to a c [...] adds d9a1d02 MCInstrDesc: Flags (uint64_t) was checked using (1 << MCID::X [...] adds c71d5b4 [CodeGen] Split out the notions of MI invariance and MI deref [...] adds 877859e [NVPTX] Use ldg for explicitly invariant loads. adds 362611f Add handling of !invariant.load to PropagateMetadata. adds a3215a2 [X86] Make a helper method into a static function local to th [...] adds 88c0b88 [X86] Side effecting asm in AVX512 integer stack folding test [...] adds 3679bfe [AVX-512] Add VPTERNLOG to load folding tables. adds d3eebe7 [AVX-512] Add test cases to demonstrate opportunities for com [...] adds 2628aff [CodeGen] Make the TwoAddressInstructionPass check if the ins [...] adds 3daf6c8 [SimplifyCFG] Harden up the profitability heuristic for block [...] adds 16d9e13 [AArch64] Fixup test after r281160 adds 05bbcbd [SimplifyCFG] Be even more conservative in SinkThenElseCodeToEnd adds d650689 Fixup failing debuginfo test for change in SimplifyCFG. adds 990fea5 [AVX512] Fix pattern for vgetmantsd and all other instruction [...] adds b4bd34e ADT: Add sentinel tracking and custom tags to ilists adds 6037e19 CodeGen: Turn on sentinel tracking for MachineInstr iterators adds 025e19e Fix the modules build after r281167 adds 00530c8 CodeGen: Assert that bundle iterators are valid adds ce85c7e [ORC] Rename RPCChannel to RPCByteChannel. NFC. adds d546df8 CodeGen: Give MachineBasicBlock::reverse_iterator a handle to [...] adds 1735568 [ORC] Fix the RPC unit test for header changes in r281171. adds bc1fa10 ADT: Remove ilist_iterator::reset(), NFC adds 6b6d496 ScalarOpts: Sort includes, NFC adds c2fec44 ScalarOpts: Use std::list for Candidates, NFC adds dd7c4ea [ORC] Update examples for header changes in r281171. adds 661e8f4 [TwoAddressInstruction] When commuting an instruction don't a [...] adds 97e83d0 Analysis: Only allow the move-constructor for IVUsers adds 5de5554 ADT: Add AllocatorList, and use it for yaml::Token adds 8650ea1 ADT: Fix build after r281182 adds a66f054 ADT: Never allocate nodes in iplist<> and ilist<> adds c7f39d7 [InstCombine] regenerate checks adds 278eb07 [InstCombine] regenerate checks adds 52fed49 [InstCombine] add helper function for folding {and,or,xor} (c [...] adds afe5d3d MC: Move MCSection::begin/end to header, NFC adds 56e56fb llvm/test/CodeGen/AMDGPU/infinite-loop-evergreen.ll REQUIRES [...] adds d186dd4 AVX-512: Added a test case that should be optimized in the fu [...] adds 217343a Fix WebAssembly broken build related to interface change in r281172. adds 7a92e73 GlobalISel: disambiguate types when printing MIR adds 39f340d GlobalISel: translate GEP instructions. adds 5d592ae GlobalISel: support translation of global addresses. adds 9c7d316 Define a dummy zlib::uncompress when zlib is not available. adds ccaa95d Fix the Thumb test for vfloat intrinsics adds 0c54a06 [LoopInterchange] Improve debug output. NFC. adds 30cc1de [ARM] Promote small global constants to constant pools adds c04a5a1 fix formatting/typos; NFC adds 91db09d [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently adds 724e567 [AMDGPU] Assembler: Move disabled SDWA and DPP instruction in [...] adds 29b1dcd [InstCombine] add helper function for foldICmpUsingKnownBits; NFCI adds 97c0650 add select i1 test, reproduser pr30249. adds 3e9ba2b [InstCombine] add tests to show missing vector folds adds 7e05343 fix formatting; NFC adds 5db0b90 [FunctionAttrs] Don't try to infer returned if it is already [...] adds 8faa07b [X86] Copy imp-uses when folding tailcall into conditional branch. adds 59a2759 [BranchFolding] Unique added live-ins after hoisting code. adds 0aa0c7d Revert "[ARM] Promote small global constants to constant pools" adds ce3adfd [GlobalISel] Fix mismatched "<..)" in intrinsic MO printing. NFC. adds 01a133c AMDGPU: Do not clobber SCC in SIWholeQuadMode adds bb4b1d9 [InstCombine] use m_APInt to allow icmp X, C folds for splat [...] adds 11981cd llvm-objdump: Add --start-address and --stop-address options adds 7ee8317 llvm-size: Add --totals option adds c123237 [MCJIT] Fix some inconsistent handling of name mangling insid [...] adds f4ef2f7 Fix test failure in r281232 adds 2917125 AVX-512: Simplified masked_gather_scatter test. NFC. adds 1f6cc3c AVX-512: Added a test for -O0 mode. NFC. adds 6979660 [InstCombine] regenerate checks adds 06b5f13 [InstCombine] add test for PR30327 adds a50faba [MC] Defer asm errors to post-statement failure adds 8c8aa02 Lower consecutive select instructions correctly. adds 77ad092 Fix the bug introduced in r281252. adds b57c915 [ORC] Replace the serialize/deserialize function pair with a [...] adds 08170c3 [ORC] Add missing <thread> header to RPCSerialization.h. adds 6e9445d attempt to unbreak build after r281254 adds eebb0bc Revert r281215, it caused PR30358. adds 8efea57 [LVI] Abstract out the actual cache logic [NFCI] adds ac22fbe [LVI] Sink a couple more cache manipulation routines into the [...] adds 0f44027 [ORC] Add some more documentation to RPCSerialization.h. adds d87460f [ORC] Clang-format RPCSerialization.h. adds 0df9c0a add more tests for PR30273 adds 3551718 [LVI] Complete the abstract of the cache layer [NFCI] adds 29e20b9 [OptDiag] Add getHotness accessor adds f016a03 Temporarily Revert "[MC] Defer asm errors to post-statement f [...] adds 45564d9 X86: Conditional tail calls should not have isBarrier = 1 adds 8d684ca [DAG] Refactor BUILD_VECTOR combine to make it easier to exte [...] adds 5420de3 DebugInfo: New metadata representation for global variables. adds 2cee504 [lib/LTO] Expose getModule() in lto::InputFile. adds 5021054 [Support][CommandLine] Add cl::getRegisteredSubcommands() adds 95da214 Revert "[Support][CommandLine] Add cl::getRegisteredSubcommands()" adds 9a5abd0 [LTO] Only expose the dataLayout string instead of the whole module. adds 6a92b76 [Docs] Fix a broken link in the Kaleidoscope tutorial. adds 7e9a83f [X86] Remove some dead intrinsics. They aren't implemented an [...] adds 5db4eb4 [X86] Remove masked shufpd/shufps intrinsics and autoupgrade [...] adds 8da7897 [AArch64] Support stackmap/patchpoint in getInstSizeInBytes adds 9cb541b AVX-512: Fix for PR28175 - Scalar code optimization. adds 0298251 This adds a new field isAdd to MCInstrDesc. The ARM and Hexag [...] adds 48f6957 Revert of r281304 as it is causing build bot failures in hexa [...] adds 7dc5b7e Remove MVT:i1 xor instruction before SELECT. (Performance imp [...] adds ea8e2d3 [WebAssembly] Trying to fix broken tests in CodeGen/WebAssemb [...] adds 2e1f810 [ARM] Promote small global constants to constant pools adds d0c0b62 [ARM] Support ldr.w in pseudo instruction ldr rd,=immediate adds 503f462 [llvm-cov] - Included footer "Generated by llvm-cov -- llvm v [...] adds 7d76437 Enable simplify libcalls for ARM PCS adds e81b6f3 [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently adds c8b398c [ARM] Add ".code 32" to functions in the ARM instruction set adds d2d2efe Remove InstCombine test file adds 283b1c0 Revert "[ARM] Promote small global constants to constant pools" adds bcfa2b1 [LoopInterchange] Tidy up and remove unnecessary dyn_casts. NFC. adds 7849052 Typo. NFC. adds c732159 Don't use else if after return. Tidy comments. NFC. adds 93627d9 [InstSimplify] Add tests to show missed bitcast folding oppor [...] adds f565d64 [LoopInterchange] Minor refactor. NFC. adds be08d6e Defer asm errors to post-statement failure adds 09d676e Apply Clang-format to MCAsmParser.cpp NFC. adds 70a4ffa [Hexagon] Clear the flow queue after visiting a single instruction adds befcbd1 [modules] Re-enable some previously excluded files. adds 7724253 [X86] Regenerated shift combine tests. adds d9dffbd [ConstantFold] Improve the bitcast folding logic for constant [...] adds 21409db Fix misleading comment for getOrEnforceKnownAlignment adds 45e3537 [DAGCombiner] Use APInt directly in (shl (ext (shl x, c1)), c [...] adds 76b613f [X86][SSE] Added AVX512F and additional vector truncate test cases adds e353f57 [Myriad]: set LeonCASA processor feature adds 9a0a97c Revert r281336 (and r281337), it caused PR30372. adds 8288ccf [DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C [...] adds f5f2db2 Fix MSVC 2013 build by using our <thread> wrapper header adds 9330005 [LTO] Don't pass SF_Undefined symbols to the IRmover. adds 470b8e4 [LV] Clean up uniform induction variable analysis (NFC) adds ec4f2a0 AMDGPU: Support commuting a FrameIndex operand adds a3d7c71 .clang-tidy: correct style name is 'camelBack' not 'lowerCase'. adds 1defb8f AMDGPU: Remove code I think is dead adds f461e09 AArch64: Cleanup tailcall CC check, enable swiftcc. adds 9e6badc Reapply "InstCombine: Reduce trunc (shl x, K) width." adds 9f45ab5 add tests for PR28672 adds 60fc58a [Hexagon] Better handling of HVX vector lowering adds 7402add Next set of additional error checks for invalid Mach-O files [...] adds 3389341 [DAG] Allow build-to-shuffle combine to combine builds from t [...] adds c3d0d35 [CodeGen] Fix invalid shift in mul expansion adds d78e421 [AArch64] Simplify patchpoint/stackmap size test (r281301). NFC. adds e7f7e18 [llvm-cov] Just emit the version number in the index file adds 90a2aec [ObjCARC] Traverse chain downwards to replace uses of argumen [...] adds 3cb3e3c Address Pete's review comment and define OrigArg on its own line. adds 8ea4234 [sanitizer-coverage] add yet another flavour of coverage inst [...] adds a4826c1 [libFuzzer] start using trace-pc-guard as an alternative sour [...] adds 6f025c1 gold: Simplify. Do not unnecessarily enumerate Obj's symbols. adds e6c628f Ensure Polly linking works without BUILD_SHARED_LIBS adds 81a2b89 Create a getelementptr instead of sub expr for ValueOffsetPai [...] adds cb2901c [X86] Remove the VCVTSI2SD32 with rounding intrinsic. It's no [...] adds 3ef99c9 [AVX512BW] Change truncStore action (v16i16->v16i18). It can [...] adds ad1b22c AVX-512: Fixed a bug in kortest.z intrinsic adds 82d457b This reapplies r281304. The issue was that I had missed to co [...] adds d40a562 GlobalISel: mark pointer stores as legal on AArch64. adds 76c5395 Missing includes. adds 9502e5b Revert "[Thumb] Teach ISel how to lower compares of AND bitma [...] adds 62660f0 [asan] Enable -asan-use-private-alias on Darwin/Mach-O, add t [...] adds 9320a12 [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directl [...] adds 3477191 Adding missing directive for Power9. There is currently no co [...] adds f64fd37 [StackProtector] Use INITIALIZE_TM_PASS instead of INITIALIZE [...] adds 707666e [InstCombine] Merged two test files and regenerated checks us [...] adds 7328eb7 Fix code-gen crash on Power9 for insert_vector_elt with varia [...] adds 1c82089 [X86] Added i128 lshr+shl -> mask combine test adds 3824319 [X86][SSE] Removed unused getTargetShuffleNode function adds 2ecc1fc MCInstrDesc: this fixes an issue setting/getting member Flags [...] adds b50cea7 [ARM] Promote small global constants to constant pools adds be3fec6 [LV] Process pointer IVs with PHINodes in collectLoopUniforms adds 8bc95d0 AMDGPU: Improve splitting 64-bit bit ops by constants adds f4559b5 getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI adds 04e0167 getValueType().getScalarSizeInBits() -> getScalarValueSizeInB [...] adds 0f71258 AMDGPU: Support folding FrameIndex operands adds e9c64c5 Fix typo in comment [NFC] adds a7c48cc getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI adds c0a42ff getVectorElementType().getSizeInBits() -> getScalarSizeInBits [...] adds fb1804b [LoopInterchange] Cleanup debug whitespace. NFC. adds 47eb9d5 getValueType().getScalarSizeInBits() -> getScalarValueSizeInB [...] adds e65dbf0 [X86][SSE] Don't use PSHUFD directly - lower with generic shuffle adds 1e694f0 [LoopInterchange] Add CL option to override cost threshold. adds 1e06f6c [LoopInterchange] Typo. NFC. adds c348bc4 [X86][SSE] Improve recognition of i64 sitofp conversions that [...] adds 2462473 [compiler-rt] Avoid instrumenting sanitizer functions adds b4dbf03 [x86] fix formatting; NFC adds ab302cd AArch64: Use TTI branch functions in branch relaxation adds b1a710d Make analyzeBranch family of instruction names consistent adds 50aa910 Verifier: Mark orphaned DICompileUnits as a debug info failur [...] adds fff5113 AMDGPU: Use SOPK compare instructions adds aceeb33 Revert "AMDGPU: Use SOPK compare instructions" adds d41f227 [lib/LTO] Fix a typo. NFC. adds 4e8d86c [x86] regenerate checks adds eb967fb Revert "[ARM] Promote small global constants to constant pools" adds 421442e [x86] regenerate checks adds 0890bf3 [x86] regenerate checks adds 9becdee [Stackmap] Added callsite counts to emitted function information. adds 93e6e54 Finish renaming remaining analyzeBranch functions adds e038466 [ThinLTO] Add an option to llvm-lto to print some basic stati [...] adds bdf517a [LTO] Fix commons handling adds fd7afc4 [LTO] Move tests from test/tools to test/LTO, as they're test [...] adds 86a6238 Fix indentation in codeview code adds a364825 Fix auto-upgrade of TBAA tags in Bitcode Reader adds a984fc7 [MC] Handle discardable COFF sections in assembly adds a9d16c9 [pdb] Write TPI hash values to the TPI stream. adds b5689e7 [pdb] Get rid of Data and RawData in CVType. adds a18aa4c [InstCombine] add vector tests for foldICmpUsingKnownBits() adds f5898c1 [pdb] Fix unit test compilation. adds 0ebfb4e [InstCombine] refactor eq/ne cases in foldICmpUsingKnownBits( [...] adds 26586a8 [libFuzzer] add 8-bit counters to trace-pc-guard handler adds 8159863 [LangRef] Add a clarifying example for undef adds 4574c11 [doc] [CUDA] Add sections about STL support and differences b [...] adds f09ca2f Add a C++ unittest to test the fix for PR30213. adds f0b5dd7 [libFuzzer] implement print_pcs with trace-pc-guard. Change t [...] adds 5d97808 [llvm-cov] Fix tests that aren't checking anything (NFC) adds 90562cd [llvm-cov] Don't print a verbose title when looking at one file adds 7e2d153 [libFuzzer] fix print_pcs test adds 7551d48 [llvm-cov] Make a method name more accurate (NFC) adds 3f6d675 [libFuzzer] move the AFL driver build rule test into the unin [...] adds 577674b [libFuzzer] disable test that requires debug info -- it fails [...] adds f158709 [CMake] Fixing lit for runtimes directory adds 0bcb8fb Add some shortcuts in LazyValueInfo to reduce compile time of [...] adds 2fcbfcf [llvm-cov] Don't create 'jump to ...' links in nested views adds 61f5694 [llvm-cov] Hide instantiation views for unexecuted functions adds 4cb3509 [llvm-cov] Move some layout logic to the right spot (NFC) adds cdce758 GlobalISel: cache pointer sizes in LLT adds ccc7ec7 llvm/test/Transforms/CorrelatedValuePropagation/alloca.ll REQ [...] adds 3d94178 GlobalISel: remove "unsized" LLT adds 3d658a6 GlobalISel: relax type constraints on G_ICMP to allow pointers. adds 8c9a9af GlobalISel: legalize GEP instructions with small offsets. adds 095eb00 [ARM] Promote small global constants to constant pools adds c2c0b27 [mips][ias] Enable IAS by default for N64 on Debian mips64el. adds 0ee1696 [InstCombine] use m_APInt to allow icmp folds using known bit [...] adds 8055438 [InstCombine] add helper function for foldICmpWithConstant; NFC adds 964ae1d [InstCombine] clean up foldICmpWithConstant(); NFC 1. Early e [...] adds 0863eca Document our extension to the COFF .section directive flags adds 28f64ff address comments from: https://reviews.llvm.org/D24566 using [...] adds 51832f7 Fix silly mistake introduced here : https://reviews.llvm.org/ [...] adds d40500c [compiler-rt] Changing function prototype returning unused value adds c0fdffb [InstCombine] auto-generate checks adds b794567 [InstCombine] add vector tests for icmp sgt smin adds f71deb6 [InstCombine] allow (icmp sgt smin(PosA, B), 0) fold for vectors adds d2bd71f [InstCombine] remove duplicated fold ; NFCI adds 72499e5 Take ownership of libLTO as discussed on llvm-dev. adds 8471051 [IRObjectFile] Handle undefined weak symbols in RecordStreamer. adds ba1d7c6 [InstCombine] add vector tests for icmp (sub nsw) adds 2473bf0 [InstCombine] allow icmp (sub nsw) folds for vectors adds d52d051 [libFuzzer] fix the build for AFLDriverTest adds 6baec2e [pdb] Fix the TPI stream size computation. adds d6d0906 fix function names; NFC adds 5fa3c52 [pdb] Write the IPI stream. adds f31e663 [PM] Port CFGViewer and CFGPrinter to the new Pass Manager Di [...] adds 71d3c34 [InstCombine] simplify code; NFCI adds 745df32 Revert "[ARM] Promote small global constants to constant pools" adds a5437a6 [AArch64] Support for FP FMA when -ffp-contract=fast adds 26eccc1 [InstCombine] Do not RAUW a constant GEP adds 12be25f [GlobalOpt] Dead Eliminate declarations adds 539a656 regenerate checks adds ea88605 [InstCombine] allow icmp (shr/shl) folds for vectors adds 8f94ffd [codeview] Optimize the size of defranges with gaps adds 31daa34 [sanitizer-coverage] make trace-pc-guard and indirect-call wo [...] adds dcc5ba2 [libFuzzer] make caller-callee feedback work with trace-pc-guard adds f094f62 [InstCombine] move folds for icmp (sh C2, Y), C1 in with othe [...] adds 837806b build_llvm_package.bat: Update to VS2015 and include LLDB adds ff48266 Fix autoupgrade logic for Objective-C class properties module flag adds 1354d58 Revert "[asan] Add flag to allow lifetime analysis of problem [...] adds d26bf22 Revert "[asan] Avoid lifetime analysis for allocas with can b [...] adds 281351c Add a test for r280191 adds c53e384 [CUDA] [doc] Note that you can use std::min/max from device c [...] adds 2ce67fb Remove unused function getMang(). adds 88a23b6 Move the Mangler from the AsmPrinter down to TLOF and clean u [...] adds d95bdda [ARM] Promote small global constants to constant pools adds 793f008 [LCG] Redesign the lazy post-order iteration mechanism for th [...] adds 6c1574b Trying to fix Mangler memory leak in TargetLoweringObjectFile. adds f9c0a77 This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM [...] adds 89f7a48 [AArch64][GlobalISel] Use the generic DefaultMapping as the default. adds ea7e0cd Reverting r281719, this is causing buildbot failures and time [...] adds e38b67f [mips] Fix aui/daui/dahi/dati for MIPSR6 adds 8ab74ba [LTO] Fix handling of mixed (regular and thin) mode LTO adds ffabbc5 Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6" adds 7435b28 Place the lowered phi instruction(s) before the DEBUG_VALUE entry adds 0057769 [mips] Fix previous revert r281726. adds cd01b58 Reapplying r278731 after fixing the problem that caused it to [...] adds ac10524 [AArch64][GlobalISel] Add tests for default RegBank mappings. NFC. adds c3852f5 [AArch64][GlobalISel] Add default regbank mappings for mixed- [...] adds 07ca84e [AArch64][GlobalISel] Test default regbank mapping for G_ICMP. adds 16527fa [AArch64][GlobalISel] Add default regbank mapping for FP ops. adds d705c9f [AArch64][GlobalISel] Add default regbank mapping for G_FCMP. adds c49f5e8 [AArch64][GlobalISel] Add default regbank mapping for int<>FP. adds 3284f27 [LTO] Prevent asm references to be dropped from the output. adds ad63f23 [IRObjectFile] Turn llvm_unreachable("foo") into something mo [...] adds 1af8186 [InstCombine] add helper functions for visitICmpInst(); NFCI adds 4dbfcbb Fix NameAnonFunctions pass: for ThinLTO we need to rename glo [...] adds 8dff0d8 Rename NameAnonFunctions to NameAnonGlobals to match what it [...] adds 7bbc777 Fix a hidden use of grabbing the Mangler from the AsmPrinter [...] adds d964ea8 Actually remove the Mangler from the AsmPrinter and clean up [...] adds 1832d7b [LTO] Use llvm-nm instead of nm in new tests adds f15b3af Fix test after renaming -name-anon-functions pass to -name-an [...] adds 9fd0ad8 auto-generate checks adds 58071c9 auto-generate checks adds 3383e2c LoopLoadElimination should preserve GlobalsAA. adds 0d3cd48 LoopDistribute should preserve GlobalsAA. adds 6dc8c1a Make test slightly more explicit. NFC. adds 4746214 Change extractProfMetadata and extractProfTotalWeight to cons [...] adds db393b8 Defer asm errors to post-statement failure adds 7add7dd Install libLLVM if needed with LLVM_INSTALL_TOOLCHAIN_ONLY adds b2c2d1f [X86][SSE] Added vector add combine tests adds 839ecc8 [X86][SSE] Added vector sub combine tests adds 740da34 [WebAssembly] Fix function types of CFGStackify tests adds 463cfe4 [LTO] Add ability to parse AA pipelines. adds 59183b9 [InstCombine] allow vector types for constant folding / compu [...] adds 1961591 AMDGPU/SI: Add support for triples with the mesa3d operating system adds 3a74bac AMDGPU: Use SOPK compare instructions adds 77361ae AMDGPU: Refactor kernel argument lowering adds 12bac3e [RegAllocGreedy] Fix an assertion and condition when last cha [...] adds 005bfb8 [RegAllocGreedy] Fix the list of NewVRegs for last chance rec [...] adds df9dcaf [safestack] Fix assertion failure in stack coloring. adds 8f824fe AMDGPU: Allow some control flow intrinsics to be CSEd adds 16150b3 [InstCombine] canonicalize vector select with constant vector [...] adds 78279ce [CMake] Support symlinks with the same name as the binary adds 019f4de AMDGPU/SI: Fix kernel argument ABI for HSA adds 982faf2 AMDGPU: Use i64 scalar compare instructions adds e3e722b Don't create a SymbolTable in Function when the LLVMContext d [...] adds 977635d Revert "Don't create a SymbolTable in Function when the LLVMC [...] adds 16197d8 [sanitizer-coverage] change trace-pc to use 8-byte guards adds b9cc2c4 [libFuzzer] change trace-pc to use 8-byte guards adds 5f16c76 MIR Parser: issue an error when the Context discard value names. adds f3f34d6 [MIR Parser] Fix Build! adds d1e3c5a Don't create a SymbolTable in Function when the LLVMContext d [...] adds 338f974 [libFuzzer] properly reset the guards when reseting the cover [...] adds 077ab85 AMDGPU: Push bitcasts through build_vector adds 28d0522 AMDGPU: Rename spill operands to match real instruction adds de82da5 AMDGPU: Fix broken FrameIndex handling adds 973dd0e [Hexagon] segv while processing SUnit with nullNodePtr adds 05c5270 [X86][SSSE3] Add target shuffle constant folding tests adds aa105ad [X86][XOP] Add target shuffle constant folding tests adds 679cf95 [X86][AVX] Add target shuffle constant folding tests adds db0c416 [X86][AVX2] Add target shuffle constant folding tests adds 83d088f [X86][AVX] Test target shuffle combining on 32 and 64-bit targets adds cbaa900 [X86][SSE] Improve target shuffle mask extraction adds 1982c8e [X86][SSE] Added vector mul combine tests adds b6d6773 [ThinLTO] Ensure anonymous globals renamed even at -O0 adds 063b327 [X86][SSE] Added vector fcopysign combine tests adds 52c60ce [X86][SSE] Added vector udiv combine tests adds a64fbcf [lib/LTO] Try harder to reduce code duplication. NFCI. adds 4b868ad [llvm-objump] Simplify the code. NFCI. adds 2bed903 [libFuzzer] use 'if guard' instead of 'if guard >= 0' with tr [...] adds f54e133 Change the order of the splitted store from high - low to low [...] adds 868c6d1 [Loop vectorizer] Simplified GEP cloning. NFC. adds 428ba8e [X86][SSE] Improve recognition of uitofp conversions that can [...] adds 305b3f3 [Loop Vectorizer] Consecutive memory access - fixed and simplified adds ab43022 [Profile] Implement select instruction instrumentation in IR PGO adds 760a2d0 Fix built bot failure adds 4153ca5 [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that al [...] adds 0486347 [AVX-512] Add memory load patterns for the legacy SSE scalar [...] adds 45d1e6d [X86] Fix typo in comment. NFC adds 04a2b34 Rename tests adds 08a3649 [CostModel][X86] Added scalar float op costs adds b9ae8b0 Fix covered-switch-default warning adds 304a0b4 [libFuzzer] add -print_coverage=1 flag to print coverage dire [...] adds ae55aa0 [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FS [...] adds 1b68ca9 [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND wi [...] adds 178b58d Extend title underline adds 60489f4 Handle Invoke during sample profiler annotation: make it inlinable. adds 7b1bb28 [utils] Delete the 'check-coverage-regressions' script adds c063c43 [llvm-cov] Drop another redundant 'No.' suffix adds 6360ab9 [llvm-cov] Make 'adjustColumnWidths' do less work adds 40817d8 [llvm-cov] Don't recompute the 'Covered' field from *Coverage [...] adds e17f26f [llvm-cov] Track function and instantiation coverage separately adds a830753 [llvm-cov] Make a helper method static for re-use (NFC) adds 70b43c3 [llvm-cov] Teach the coverage exporter about instantiation coverage adds 916b366 [XRay] ARM 32-bit no-Thumb support in LLVM adds 1b70b5d [llvm-cov] Delete the NonCodeLines field, it was always dead adds 764028e [llvm-cov] Emit a link to some documentation adds d5369d3 [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp wh [...] adds d854787 [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when [...] adds 1a9f29f [SimplifyCFG] Update (AND) IR flags when CSE'ing instructions adds 0173661 [X86 Codegen Test] Divided masked_memop into several files. NFC. adds ab6de7f ARM: check alignment before transforming ldr -> ldm (or similar). adds 8d46442 [Thumb] Set correct initial mapping symbol for big-endian thumb adds 383922d Add @llvm.dbg.value entries for the phi node created by -mem2reg adds 21fcdfd [AMDGPU] Fix s_branch with -1 offset adds 1494db6 [AArch64] Fix encoding for lsl #12 in add/sub immediates adds d1be85d [AMDGPU] Refactor VOPC instruction TD definitions adds ebd2807 Revert r281841, it does not work on Windows (PR30443). adds 781fb6e [Support] Add StringRef::withNullAsEmpty() adds b87b0d3 [asan] Support dynamic shadow address instrumentation adds 625183d Use call target count to derive the call instruction weight adds ba3d957 Only set branch weight during sample pgo annotation when max_ [...] adds b073196 LiveRangeCalc: Fix reporting of invalid vreg usage in livenes [...] adds d809745 [RegisterBankInfo] Avoid heap allocation in most cases. adds ddeacc7 Handle early inline for hot callsites that reside in the same [...] adds b3d4112 [libFuzzer] use sleep() instead of std::this_thread::sleep_f [...] adds 4f6fc26 [X86][SSE] Updated vector abs tests adds 050e903 Misleading comments of SplitBlockAndInsertIfThenElse in Basic [...] adds a2d3e03 BitcodeWriter: fix emission of invoke when calling a var-arg [...] adds f1212b9 Move the armv8.1-a ras test to a negative with noras test as [...] adds 10b68a3 [x86] use getSignBit() to simplify code; NFCI adds 4cd6605 [Kaleidoscope] Make Chapter 2 use llvm::make_unique, rather t [...] adds 15afb79 Merge branch 'ADCE5' adds 3d21d84 [RegisterBankInfo] Adapt call to std::fill due to use of Smal [...] adds 67197ee [LCSSA] Cache LoopExits to avoid wasted work adds f8408ab [x86] auto-generate checks adds 18f63e4 [sanitizer-coverage] add comdat to coverage guards if needed adds ef83519 [x86] fix variable names; NFC adds 879da28 [RegisterBankInfo] Avoid heap allocation in InstructionMapping. adds 34c557c Machine{Instr|Operand}: Clarify some isIdenticalTo() subtleties. adds b72235f BranchFolder: Fix invalid undef flags after merge. adds fd8c733 [AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_ [...] adds 0acae1f [AVX-512] Teach X86InstrInfo::copyPhysReg to use a 512-bit mo [...] adds 8e81726 [SROA] Preserve llvm.mem.parallel_loop_access metadata. adds 42ea17a Reverting revision 281960 due to test failures. adds 2a3c739 AMDGPU: Improve documentation. adds 4aaf90e Make llvm::ConvertDebugDeclareToDebugValue() be a void functi [...] adds 9101685 [AMDGPU] Refactor VOP3 instruction TD definitions adds 8e5c84a AVX-512: Fixed a bug in lowering saturated operations on KNL. adds 412e71b [AMDGPU][mc] Add regression tests for Bug 28168 adds c091990 move variables closer to their uses; add FIXMEs; NFC adds e4f1232 [X86][SSE] Regenerate multiple combine tests adds a93f61a GlobalISel: split aggregates for PCS lowering adds 4e09440 Improve the -debug output for Debug Range Extension (NFC) adds a619989 Remove extra argument used once on TargetMachine::getNameWith [...] adds 57ab7e9 Remove a use of subtarget initialization in the X86 backend s [...] adds 663e1b0 Remove more guts of TargetMachine::getNameWithPrefix and migr [...] adds 6530b2f X86: loosen an overly aggressive MachO assertion adds f5f252d Emit S_COMPILE3 CodeView record adds 864e0ff Fix syntactical nit from r281990. adds 3051c6d ASAN: Don't drop debug info attachements for global variables [...] adds ba27f9f Revert "[AArch64] Properly validate the reciprocal estimation." adds 1bacc96 Revert "[AArch64] Use the reciprocal estimation machinery" adds 121f676 Revert part of "AArch64: Do not test for CPUs, use SubtargetF [...] adds 19dfeb0 [Profile] code refactoring: make getStep a method in base class adds ba03c81 [x86] split up tests, regenerate checks adds 7bcdeca Next set of additional error checks for invalid Mach-O files [...] adds f5969f7 [Profile] Do not annotate select insts not covered in profile. adds 38ea316 Mark ELF sections whose name start with .note as note adds 163ac62 [Profile] dump ic value profile value/site-count histogram adds 1390807 [llvm-cov] Demangle names for hidden instantiation views adds 452ae8c [CodeGen] stop short-circuiting the SSP code for sspstrong. adds 61540ac [RS4GC] Refactor code for Rematerializing in presence of phi. NFC adds 768be7b Revert "Remove extra argument used once on TargetMachine::get [...] adds 810e009 Remove the default subtarget from the x86 port as it isn't ne [...] adds 7732977 code cleanup -- commoning IR travsersals adds 7e15c9e [ThinLTO] Always emit a summary when compiling in ThinLTO mode adds 86978b7 [InferAttributes] Don't access parameters that don't exist. adds 40e5ccb Revert "TableGen: Switch from a std::map to a DenseMap in Cod [...] adds 60dd435 [libFuzzer] refactoring: move the Corpus into a separate clas [...] adds 2a54686 [libFuzzer] refactoring: split the large header into many; NFC adds 1d75557 [NVPTX] Check if callsite is defined when computing argument [...] adds dae780f [AVX-512] Don't lower avx512 vcvtps2ph/vcvtph2ps nodes to ISD [...] adds 77ab75a [libFuzzer] more refactoring; NFC adds 860a9f5 [LV] When reporting about a specific instruction without debu [...] adds da9d4eb [libFuzzer] fix libc++ build adds 3170da5 [AVX-512] Simplify handling of INTR_TYPE_1OP_MASK_RM to remov [...] adds 4ba7f94 [AVX-512] Don't add an additional rounding mode operand to th [...] adds bba417d llvm/test/CodeGen/NVPTX/zero-cs.ll: Relax an expression to ma [...] adds 8bb1682 [AVX-512] Split the 3 different usages of the X86ISD::FSETCC [...] adds 437db4f AArch64: Set shift bit of TLSLE HI12 add instruction adds 2c37c77 Revert "AArch64: Set shift bit of TLSLE HI12 add instruction" adds abc7f41 [mips] LLVM PR/30197 - Tail call incorrectly clobbers argumen [...] adds d5fca75 [AMDGPU] Assembler: remove unused AMDGPUMCObjectWriter. adds d79f714 GlobalISel: pass Function to lowerFormalArguments directly (NFC). adds c297159 GlobalISel: produce correct code for signext/zeroext ABI flags. adds cbe1f9e [LoopInterchange] Various cleanup. NFC. adds e9993d5 DeadArgElim: Don't mark swifterror arguments as unused adds f83ecb0 Revert r281715, it caused PR30475 adds a613eb1 Revert r281895 "Add @llvm.dbg.value entries for the phi node [...] adds 3d9ce2b [AVX512] Fix return types on int_x86_avx512_gatherXXX_di intrinsics adds 8f80e9f [LV] Rename "Width" to "Lane" (NFC) adds aa30d2c Change the basic block weight calculation algorithm to use ma [...] adds 4836a1b [AMDGPU][mc] Add support for ds_add_[rtn_]f32. adds 653eafd [LV] Don't emit unused scalars for uniform instructions adds ad6572b Disable tail calls if there is an swifterror argument adds 1ff6b12 fix typo in comment [NFC] adds 5f630a9 revert 281908 because 281909 got reverted adds 648d6ac [MIRParser] Delete dead code. NFCI. adds b81a1e9 [ThinLTO] Emit files for distributed builds for all modules adds 799bfde [LoopInterchange] Track all dependencies, not just anti depen [...] adds e10e0e3 Next set of additional error checks for invalid Mach-O files [...] adds e52f15b [libFuzzer] more refactoring adds a6b3c30 [libFuzzer] more refactoring; don't compute sha1sum every tim [...] adds ecdd589 =delete the StringRef(nullptr_t) constructor. adds e4977b2 [libFuzzer] add stats to the corpus; more refactoring adds 3f3f2cd [libFuzzer] one more test adds e9b850b [libFuzzer] add 'features' to the corpus elements, allow muta [...] adds 22bb41e [RegisterBankInfo] Take advantage of the extra argument of Sm [...] adds e6b78fd [RegisterBankInfo] Move to statically allocated RegisterBank. adds c7cbba0 [AVX-512] Add support for commuting VPTERNLOG instructions. adds f2986e2 Fix revision 281960 adds 5b1a390 [EfficiencySanitizer] Using '$' instead of '#' for struct cou [...] adds a941fe2 [Power9] Add exploitation of non-permuting memory ops adds 11508f0 [PowerPC] Remove LE patterns matching generic stores/loads to [...] adds c228fe8 [AMDGPU][mc] Add support for absolute expressions in DPP modifiers. adds 4bbf4cb [RS4GC] Remat in presence of phi and use live value adds c63e7f7 GlobalISel: handle stack-based parameters on AArch64. adds 523c933 Reapplying r281895 (and follow-up r281964) after fixing pr30468. adds afaf6ad GVN-hoist: only hoist relevant scalar instructions adds 6958050 GVN-hoist: move hoist testcase to GVNHoist dir adds 3abbc4d [compiler-rt] fix typo in option description [NFC] adds fb27f55 [Support] Add StringRef::consumeInteger. adds 3132c38 GVN-hoist: fix typo adds 3e55f3d GVN-hoist: fix store past load dependence analysis (PR30216) adds 20bb032 Speculative fix for build failures due to consumeInteger. adds 7b83fe6 [PPC] Set SP after loading data from stack frame, if no red z [...] adds 7924acd GVN-hoist: do not dereference null pointers adds 489cfe7 [DAG] Fix incorrect alignment of ext load. adds f2f9e2b [PowerPC] Sign extend sub-word values for atomic comparisons adds 0966627 Fix build breakage due to typo in cast. adds ba9e1e6 Win64: Don't emit unwind info for "leaf" functions (PR30337) adds d1714b5 i386 does not support optimized swifterror handling adds 6baa853 [RDF] Use uint32_t for register numbers instead of unsigned adds b505adc [RDF] Print the function name for calls in dumps adds a9c167e [Hexagon] Remove USR_OVF from CtrRegs register class adds 319d69e [RDF] Add initial support for lane masks in the DFG adds 579bab4 Revert r282168 "GVN-hoist: fix store past load dependence ana [...] adds c3e16a5 MachineScheduler: Remove ineffective heuristic; NFC adds a86d297 MachineScheduler: Slightly simplify release node adds ef76be0 [llvm-cov] Add the ability to specify directories of input so [...] adds ae0e243 [llvm-cov] Document some fields in a class (NFC) adds c2ac1a7 [utils] Teach the code coverage prep script about --restrict adds f35fea1 [AsmParser] Remove unused partial template specialization. adds 38d30e5 [InstCombine] fold X urem C -> X < C ? X : X - C when C is bi [...] adds 43896df [libFuzzer] simplify the crash minimizer; split MaxLen into t [...] adds 45c56ae [RegisterBankInfo] Use array instead of SmallVector for BreakDown. adds 04905d7 [RegisterBankInfo] Check that the mapping covers the interest [...] adds 5255015 [AArch64][RegisterBankInfo] Switch to TableGen'ed like Partia [...] adds 28f017d [libFuzzer] change ValueBitMap to remember the number of bits in it adds bdbe64e [MC] Support skip and count for .incbin directive adds 6744636 Triple: Add opencl environment type adds 5a965a6 [libFuzzer] move value profiling logic into TracePC adds 7bb963e [AArch64][RegisterBankInfo] Sanity check TableGen'ed like inputs. adds a750e55 [RegisterBankInfo] Mark the dump methods with LLVM_DUMP_METHOD. adds 73508a3 [libFuzzer] simplify the TracePC logic adds bf101a6 AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_size adds 07016d4 [libFuzzer] fix merging with trace-pc-guard adds fd1fd77 [libFuzzer] be more precise about what we reset in TracePC adds cfb1f68 [AVX-512] Use different ISD opcodes for some of the scalar in [...] adds 27e9902 [AVX-512] Add separate ISD opcodes for each form of CVT instr [...] adds c2a5d16 [AVX-512] Split X86ISD::VFPROUND and X86ISD::VFPEXT into sepa [...] adds 5d11fd5 [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions adds b64f7d8 [llvm-dwarfdump] - Teach dwarfdump to dump gdb-index section. adds b9dfeea [InstCombine] Fix for PR29124: reduce insertelements to shuff [...] adds 53a7de6 Revert r282235 "[llvm-dwarfdump] - Teach dwarfdump to dump gd [...] adds 582d1a1 Revert r282238 "Revert r282235 "[llvm-dwarfdump] - Teach dwar [...] adds 91fdd2b cmake: Support overriding Sphinx HTML doc install directory adds e2c1cbe [ARM] Promote small global constants to constant pools adds a04f901 [Power9] Exploit move and splat instructions for build_vector [...] adds 3b62127 Revert "[ARM] Promote small global constants to constant pools" adds 32ed609 Enhance calcColdCallHeuristics for InvokeInst adds f8d0897 [RegisterBank] Mark the dump method with LLVM_DUMP_METHOD. adds 4151a97 [RegBankSelect] Use DEBUG_TYPE instead of repeating the name [...] adds 5c7b0b1 BitcodeReader: Deduplicate code. NFC. adds abd02b3 ScheduleDAG: Match enum names when printing sdep kinds adds c81278e [RegisterBankInfo] Add statistics for dynamic partial mappings. adds 76cc1a9 [ResetMachineFunction] Add statistic on the number of reset f [...] adds f8e3a51 [ResetMachineFunction] Populate the comments in the header of [...] adds c5ddf50 [TLI] isdigit / isascii / toascii param type should match ret [...] adds c36f315 [llvm-cov] Minor cleanup. NFC. adds fd06635 [llvm-cov] Get rid of all invalid filename references adds daacf3c [llvm-cov] Filter away source files that aren't in the covera [...] adds 85fa818 [MC] Support .dcb directives in assembler parser adds a6754db [libFuzzer] reset Counters (trace-pc-guard) before every run adds 3de4fb3 [llvm-cov] Factor out logic to remove unmapped inputs (NFC) adds 5438741 [Coverage] Clarify a function contract (NFC) adds 468ae9f [gold] Split plugin options controlling ThinLTO and codegen p [...] adds b5dbd9f [libFuzzer] first steps in adding a proper automated test sui [...] adds dc7e3f0 [AMDGPU] Fix for bz30427: wrong MTBUF encoding on VI adds 91d99c6 LTO: Simplify caching interface. adds a92ff23 llc: Add -start-before/-stop-before options adds 2a09485 [MC] Support .ds directives in assembler parser adds 200a529 Add StringSwitch::Cases functions that takes 6 to 10 arguments. adds e86f702 [x86] fix FCOPYSIGN lowering to create constants instead of C [...] adds 9194bd4 Add qualification to fix MSVC build. adds e2e5490 [libFuzzer] simplify HandleTrace again, start re-running inte [...] adds c1ce9ac GlobalStatus: Don't walk use-lists of ConstantData adds ec25365 [libFuzzer] add a standalone build script adds 245edb6 [RegisterBankInfo] Keep valid pointers for PartialMappings. adds 9545266 [RegisterBankInfo] Uniquely generate ValueMapping. adds d1ab103 [RegisterBankInfo] Add statistics for dynamic value mappings. adds ab46f81 [RegisterBankInfo] Document the design choice for the BreakDown. adds 9b47314 [RegisterBankInfo] Constify the member of the XXXMapping maps. adds 2e99ba2 [AVR] Update signature of AVRTargetObjectFile::SelectSectionF [...] adds e31ddb4 Analysis: Return early in isKnownNonNullAt for ConstantData adds 3a296bc Scalar: Ignore ConstantData in processAssumption adds c7ebf69 [x86] don't try to create a vector integer inst for an SSE1 t [...] adds 5cb2954 Analysis: Return early for UndefValue in computeKnownBits adds affe799 ObjCARC: Don't look at users of ConstantData adds 9ca28ec [AVX-512] Remove the patterns for selecting scalar VCOMI/VUCO [...] adds 1e23cc8 [AVX-512] Split scalar version of X86ISD::SELECT into a separ [...] adds 6928dfa [X86] Teach combineShuffle to avoid creating floating point o [...] adds 386ab19 [AVX-512] Don't use two opcodes for INTR_TYPE_SCALAR_MASK_RM. [...] adds 568a8f4 Add some predicated searching functions to StringRef. adds 3ae26e9 Fix signed / unsigned comparison. adds 9f072db Add a comment on StringRef::contains(char) adds 1239ce3 [AVX-512] Remove duplicate instructions for converting intege [...] adds a7c6d16 [AVX-512] Add the scalar unsigned integer to fp conversion in [...] adds d064828 [AVX-512] Add rounding versions of instructions to hasUndefRe [...] adds 7913ebb [AVX-512] Fix some patterns predicates to properly enforce pr [...] adds 444f89a [AVX-512] Replace get512BitSuperRegister with calls to Target [...] adds 277575f [X86] Remove patterns for scalar_to_vector from FR32/FR64 to [...] adds 8ab193a [X86] Remove what appears to be leftover MMX code involving ( [...] adds 0d1cc51 [SCEV] Clang format most of the SCEV header; NFC adds 3b4332c [SCEV] Remove incidental data structure; NFC adds f4f66fe [SCEV] Rename a couple of fields; NFC adds a2d692b [SCEV] Simplify tracking ExitNotTakenInfo instances; NFC adds 347d5b6 [SCEV] Have ExitNotTakenInfo keep a pointer to its predicate; NFC adds bfa3983 [SCEV] Document a gotcha; NFC adds 72ec6f5 [SCEV] Reserve space in SmallVector; NFC adds e6b6f3a Attempt to appease MSVC adds fbc0b21 Appease MSVC adds 475c580 [SCEV] Simplify BackedgeTakenInfo::getMax; NFC adds 643807a [SCEV] Further isolate incidental data structure; NFC adds 98e898c [SCEV] Make it obvious BackedgeTakenInfo's constructor steals [...] adds a80a7d1 [SCEV] Combine two predicates into one; NFC adds efbeb45 [SCEV] Assign LoopPropertiesCache in the move constructor adds 52c8c40 [PM] Add a unittest for invalidating module analyses with an [...] adds d6345b8 [PM] Add a unittest covering the invalidation of a Module ana [...] adds ce297d7 [SCEV] Fix the order of members in the initializer list. adds de3ef8a [X86][avx512] Fix bug in masked compress store. adds 56b0418 [PM] Refactor this unittest a bit to remove duplicated code. [...] adds 9209299 [X86] Optimization for replacing LEA with MOV at frame index [...] adds ba54dc2 [ARM] Promote small global constants to constant pools adds 6c6dbe6 [AMDGPU] Disassembler: print label names in branch instructions adds ecba024 Revert "[AMDGPU] Disassembler: print label names in branch in [...] adds 679be7e [AVR] Add AVRMCExpr adds 56f90d7 [InstCombine] Teach the udiv folding logic how to handle cons [...] adds 23d2e04 Fix typo in comment, NFC adds 3455264 [InstCombine] Fixed bug introduced in r282237 adds 653861f Add support to optionally limit the size of jump tables. adds 51e92d1 [AArch64] Improve add/sub/cmp isel of uxtw forms. adds 8a7cd49 [Coroutines] Part14: Handle coroutines with no suspend points. adds 0749c8e [LV] Scalarize instructions marked scalar after vectorization adds a50e80e Remove pruning of phi nodes in MemorySSA - it makes updating harder adds ccb1190 AMDGPU/SI: Don't crash on anonymous GlobalValues adds c9e7be5 Update MemorySSA unittest to account for non-pruned SSA form adds 64f3b51 [llvm-cov] Silence a warning from the MSVC runtime (NFC) adds 92388ae [AArch64] Fix test triplet adds 4d5121c MachineInstr: Fix comment typo, further refine comment; NFC adds 3911695 Statistic: Only print statistics on exit for -stats adds 786045e Add optimization bisect support to an optional Mips pass adds 134d28b Add support for Code16GCC adds bb748a1 Allow StringRef to be constructed from a null pointer. adds fdf7354 [thinlto] Basic thinlto fdo heuristic adds 07758791 Move computation past early return adds 851d92e Next set of additional error checks for invalid Mach-O files [...] adds 0b13636 [WebAssembly] Use the frame pointer instead of the stack pointer adds b412e01 [CodeGen] Switch test as FreeBSD will support .init_array soon. adds e41f2a1 [CodeGen] Add support for emitting .init_array instead of .ct [...] adds cd04c01 [lit] Add a --max-failures option. adds 5b66e90 LowerTypeTests: Create LowerTypeTestsModule class and move im [...] adds e07092b LowerTypeTests: Remove unused variable. adds 65f5028 [libFuzzer] add -exit_on_src_pos to test libFuzzer itself, ad [...] adds fb4808f [libFuzzer] add a test based on openssl-1.0.1f (finds heartbleed) adds cf66db4 Revert r277556. Add -lowertypetests-bitsets-level to control [...] adds dbadbd7 [sanitizer-coverage] don't emit the CTOR function if nothing [...] adds 30eb923 [sanitizer-coverage] fix a bug in trace-gep adds cb7fbfe [libFuzzer] run re2 test in 8 threads by default adds 02e7181 [X86] Use std::max to calculate alignment instead of assuming [...] adds bdc4313 [X86] Expand all-ones-vector test to cover 256-bit and 512-bi [...] adds 941593b [X86] Add test case for PR30511 and r282341. adds 7a5ffa3 [Power9] Builtins for ELF v.2 API conformance - back end portion adds 6be6db9 Trying to fix lldb build breakage probably caused by rL282452 adds 3a76c9a [docs] Make WritingAnLLVMPass.rst up-to-date with current sta [...] adds e796285 [mips] Add rsqrt, recip for MIPS adds fbff6d5 [mips] Disable tail calls temporarily adds c87be4a [AMDGPU] Enable changing instprinter's behavior based on the [...] adds e9029b1 [docs] Fix naming style in the example adds 3a04627 Add xxhash to llvm. adds 4a0cf28 project_id is from another era in phabricator land and does n [...] adds bf2f7ba Sort headers adds 3ecd753 Output optimization remarks in YAML adds 09e2479 [lit] Fix refacto introduced by rL282479. adds b93468a Add llvm::join_items to StringExtras. adds 2713e77 Revert "Output optimization remarks in YAML" adds 275a9fe Propagate DBG_VALUE entries when there are unvisited predecessors adds 2182c89 [CMake] Use if(... IN_LIST ...) instead of list(FIND...) adds bedf4a9 [SCEV] Make PendingLoopPredicates more frugal; NFCI adds 0618af6 [SCEV] Remove custom RAII wrapper; NFC adds 4ecb8cd [SCEV] Reduce the scope of a struct; NFC adds 9f114d8 [SCEV] Use find instead of find_as; NFC adds e42a387 [SCEV] Replace a struct with a function; NFC adds d3cf9ea Improve CMake output of host and target triple adds 3979119 [RDF] Special treatment of exception handling registers adds 8263469 [RDF] Add "dead" flag to node attributes adds a02ae2b [DebugInfo] Add comments to phi dbg.value tracking code, NFC adds 93aa89c [x86] use isNullFPConstant(); NFCI adds d370d4d [llvm-cxxfilt] Use llvm::outs(). Simplify. adds 97c9e02 [lit] Add instructions to run lit's test suite adds 869a1fc Statistic: Bring back printing on exit by default adds 66a3934 Fix a typo, depricated -> deprecated adds 5b0f4e9 [cmake] Support overriding remaining HTML doc install directories adds 6acd868 Sort headers adds 47c0d49 Output optimization remarks in YAML adds 835827e [LoopSimplify] When simplifying phis in loop-simplify, do it [...] adds 8d5df95 [Inliner] Fold the analysis remark into the missed remark adds dcf371d [TargetRegisterInfo, AArch64] Add target hook for isConstantP [...] adds 0552c8c Shorten DiagnosticInfoOptimizationRemark* to OptimizationRema [...] adds ed06742 [x86] add folds for FP logic with vector zeros adds 420e92f [AArch64][RegisterBankInfo] Fix copy/paste in comments. adds 6eaaf63 [AArch64][RegisterBankInfo] Switch to statically allocated Va [...] adds 6a3e1f4 [LTO] Add an API to check if a symbol is a TLS one. adds c682447 [CMake] Force CMP0057 to NEW adds 4bc0cbd Next set of additional error checks for invalid Mach-O files [...] adds 3f5110a Pass -S to opt in this test to avoid printing binary on mismatch adds 695f82f [Inliner] Port all opt remarks to new streaming API adds e555d1b [LAA] Rename emitAnalysis to recordAnalys. NFC adds d3cf92d [libFuzzer] speedup TracePC::FinalizeTrace adds a5f794f [LTO] Mark member function as const to fix compiler errors. adds db4e01f [DAG] Remove isVectorClearMaskLegal() check from vector_build [...] adds 2db5109 [SystemZ] Implementation of getUnrollingPreferences(). adds 926244f Strip trailing whitespace adds 154ed2a [X86][FastISel] Use a COPY from K register to a GPR instead o [...] adds 62464a3 [AVR] Add assembly parser adds e62cb24 [AVR] Allow llvm-objdump to handle AVR ELF files adds 38e3973 [AVR] Handle AVR relocations when handling ELF files adds 5533629 [AVR] Update the data layout adds 504fa86 [AVR] Merge most recent changes to AVRInstrInfo.td adds c17583a [InstSimplify] allow and-of-icmps folds with vector splat constants adds 656a511 [InstSimplify] add vector splat tests for or-of-icmps adds 435dd3c [InstSimplify] allow or-of-icmps folds with vector splat constants adds fcd2ef9 [AVR] Enable the assembly parser adds 478cda0 [AVR] Update the signature of createAVRAsmBackend adds f66c56c [AVR] Add AVRMCTargetDesc.cpp adds ed9eecc [AVR] Import the LLVM namespace inside AVRMCTargetDesc.cpp adds a6d3e00 In visitSTORE, always use FindBetterChain, rather than only w [...] adds e9067af [x86] Accept 'retn' as an alias to 'ret[lqw]''ret' (At&t\Intel) adds 3cdcff0 [AVR] Rename the builtin calling convention names adds bb15ebf Revert "In visitSTORE, always use FindBetterChain, rather tha [...] adds 2fd72fd [SCEV] Use a SmallPtrSet as a temporary union predicate; NFC adds 2714064 [NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions. adds 89584ae Rewrite loops to use range-based for. (NFC) adds b835e6e Teach LiveDebugValues about lexical scopes. adds 4478320 Don't look through addrspacecast in GetPointerBaseWithConstantOffset adds 77f586a [X86][AVX] Add test showing that VBROADCAST loads don't corre [...] adds bc9cf99 Fix the bug when -compile-twice is specified, the PSI will be [...] adds 27e0165 Fix the bug introduced in r282616. adds 22cd98f [InstCombine] update to use FileCheck adds f9bcd7b [AMDGPU] Promote uniform i16 ops to i32 ops for targets that [...] adds a377afa IfConversion: Add implicit uses for redefined regs with live [...] adds b393d82 Refactor the ProfileSummaryInfo to use doInitialization and d [...] adds a2d2551 Next set of additional error checks for invalid Mach-O files [...] adds 451a26b [sancov] a simple .symcov coverage report server adds 07aadc2 Remove dead code from LiveDebugVariables.cpp (NFC) adds dc72d13 [sancov] introducing symbolized coverage files (.symcov) adds 5c6805e [RegisterBankInfo] Rework the APIs of ValueMapping. adds 1deea86 [RegisterBankInfo] Uniquely generate OperandsMapping. adds dda50f2 Next set of additional error checks for invalid Mach-O files [...] adds 6642664 Wisely choose sext or zext when widening IV. adds 2a49f50 [LTO] Expose getComdatSymbolTable() to linkers. adds 2f99205 [LTO] Add a FIXME, we shouldn't expose getComdat(). adds 846f55c AArch64: Set shift bit of TLSLE HI12 add instruction adds 0b61d07 LTO: Fix use-after-scope error. adds abc1d21 ScheduleDAGInstrs: There is no need to set OrigNode for MI SU [...] adds 0461ece AMDGPU: Partially fix control flow at -O0 adds 2b72738 MachineFunction: Add missing newline in debug print() adds 32b5cf7 Tidy spelling and grammar. adds cfc9fcc Update comment about initializing TLOF with a pointer at the [...] adds b660c90 Remove the default constructor and count variable from the Ma [...] adds 66f2dbf Remove an unnecessary duplicate initialization of TLOF from t [...] adds 8579d6c Add explanatory comment. adds e255157 IR: Rename the tablegen'd Attributes file to .gen adds 4059a77 [X86] Add VBROADCASTF128/VBROADCASTI128 to execution domain f [...] adds 08c71c6 [X86] Add 512-bit VPBROADCASTB and VPBROADCASTW tests. adds 9435177 [X86] Remove AddedComplexity adjustments that don't seem to b [...] adds b54d49d [X86] Add EVEX encoded VBROADCASTSS/SD and VPBROADCASTD/Q to [...] adds db79113 [AVX-512] Replicate pattern from AVX to select VMOVDDUP for ( [...] adds 3395e35 [X86] Remove extra FileCheck lines that got left behind in r282688. adds 37b4149 [AVX-512] Support spills of XMM16-31 and YMM16-31 when VLX is [...] adds 43006cd [AVX-512] Fix a check line from r282690. adds 607b2a3 [X86] Really fix the FileCheck line from r282690. adds 7ff4223 [modules] Centralize the module cache. adds da4f4c9 [AVR] Add instruction selection lowering code adds 22a65ba Revert "[AVR] Add instruction selection lowering code" adds 267c7c0 [docs] Fix typo in 'How to add a builder' adds e9f2c69 Test commit. NFC. adds 2551268 [docs] Fix a broken URL in 'HowToAddABuilder' adds f2d3a89 [X86] Add explicit test triple to make windows/msvc builds happier adds 8f1cd7a [X86][SSE] Added common helper for shuffle mask constant pool [...] adds 7c5de02 [libFuzzer] initialize ValueBitMap::NumBits adds 9155ed9 Remove unnecessary explicit adds 9ecbf48 [LV] Convert emitRemark to new opt remark streaming interface adds bbb8dac [LV] Convert all but one opt remark in Legality to new stream [...] adds 89695c8 [LV] Split most of createMissedAnalysis into a static function. NFC adds 3f9be70 [LV] Convert CostModel to use the new streaming opt remark API adds 8a6fcf9 [LV] Move static createMissedAnalysis from anonymous to globa [...] adds 9ef5172 [X86] Avoid "unused" warnings if no asserts adds 584dba4 [thinlto] Add cold-callsite import heuristic adds efa5482 [sanitizer-coverage/libFuzzer] make the guards for trace-pc 3 [...] adds 9b04a40 Next set of additional error checks for invalid Mach-O files [...] adds a18c5f6 fix formatting; NFC adds c51eaa4 [codeview] Use character types for all byte-sized integer types adds fdd76dc [LV] Convert processLoop to new streaming API for opt remarks adds cb40e05 [LV] Port OptimizationRemarkAnalysisFPCommute and Optimizatio [...] adds 50f86f2 Generalize ArgList::AddAllArgs more adds 97fcd6e [RegisterBankInfo] Change the default mapping for Copy and PHI. adds 07beb3c [LAA, LV] Port to new streaming interface for opt remarks. U [...] adds a9b1465 Revert "[LAA, LV] Port to new streaming interface for opt rem [...] adds 756d8e4 Clamp version number in S_COMPILE3 to avoid overflowing 16-bi [...] adds 087cb77 Add FE_ALL_EXCEPT and FE_INEXACT detection macros forgotten o [...] adds f98f357 Remove LLVM_CONFIGTIME, left-overs from when reproducable bui [...] adds c681bf5 Next set of additional error checks for invalid Mach-O files [...] adds 422655d HAVE_UNWIND_BACKTRACE -> HAVE__UNWIND_BACKTRACE Check for exi [...] adds 5a47084 Make HAVE_DECL_ARC4RANDOM always defined. Sort the entry correctly. adds 248a030 GC HAVE_LIMITS_H. adds fe86503 GC HAVE_UTIME_H. adds 04e8656 GC HAVE_MACH_O_DYLD_H. adds d72397a Check for sysconf(3). adds e7d6d31 Sort futimes correctly. adds b551157 GC HAVE_SETJMP_H and checks for the content of setjmp.h. adds 46cb711 GC opendir/readdir/closedir checks. adds eb7b0d7 GC HAVE_BCOPY. adds 74f466a GC srand48/lrand48/drand48. adds 87632b4 GC HAVE_DLERROR. adds 4f08643 Sort mallctl, fix comment for mallinfo. adds 00d1c96 GC HAVE_DYLD, HAVE_PRELOADED_SYMBOLS and HAVE_SHL_LOAD adds d067fa4 GC HAVE_DLD. adds a9d83e2 Fix comments to match autoconf. adds 3d4be77 Fix HAVE_POSIX_FALLOCATE entry. adds ac9b3d6 Move _chsize_s and _Unwind_Backtrace to the correct position. adds 224b8e4 HAVE_DIA_SDK is directly checked by value, so define it as 0/1. adds 6506cd6 GC HAVE_PRINTF_A, HAVE_STD_ISINF_IN_CMATH and HAVE_STD_ISNAN_ [...] adds 5673d4c GC more left-over libtool defines. adds d4dee42 GC HAVE_STRDUP. adds 8a50db9 [InstCombine] fix function names; NFC adds ab82a45 Add llvm::enumerate() to STLExtras. adds a481451 Revert "Add llvm::enumerate() to STLExtras." adds 381c640 [Diag] Use non-static member initializer for IsVerbose. NFC adds 858cc93 [LAA, LV] Port to new streaming interface for opt remarks. U [...] adds df7724a [AArch64][RegisterBankInfo] Check the statically created Valu [...] adds a7badfe [AArch64][RegisterBankInfo] Add static value mapping for 3-op [...] adds 070df39 [AArch64][RegisterBankInfo] Use static mapping for 3-operands [...] adds 2c3be3c [X86] Don't preserve Win64 SSE CSRs when SSE is disabled adds ec6f155 [LV] Port the last opt remark in Hints to the new streaming i [...] adds 1247d5c [LV] Port the remarks in processLoop to the new streaming API adds 449cdb5 Move UTF functions into namespace llvm. adds 072d6af [LoopDataPrefetch] Port to new streaming API for opt remarks adds ec49d2d [libFuzzer] more the feature set to InputCorpus; on feature u [...] adds 030bfb8 [libFuzzer] remove the code for -print_pcs=1 with the old cov [...] adds 7eba65d AMDGPU: Use unsigned compare for eq/ne adds a6db855 [thinlto] Don't decay threshold for hot callsites adds 4fa3e14 [LoopUnroll] Port to the new streaming interface for opt remarks. adds a466cc0 [AVX-512] Always use the full 32 register vector classes for [...] adds 5635507 [X86] Add AVX-512 VTs to findRepresentativeClass as well as v [...] adds 91f3cae [LDist] Port to new streaming API for opt remarks adds adcfb5a [libfuzzer] test for c-ares CVE-2016-5180 adds fdec3a2 Revert r282835 "[AVX-512] Always use the full 32 register vec [...] adds 2353094 [AVX-512] Add the special stack spilling pseudos for XMM16-31 [...] adds d203a8f [AVX-512] Store address operand should be an input operand fo [...] adds 156ae09 [CMake] Support symlinks even with LLVM_INSTALL_TOOLCHAIN_ONLY adds ea9ff22 [RegAllocGreedy] Attempt to split unspillable live intervals adds cb9627f [AVR] Add the assembly instruction printer adds eabad28 Revert "[RegAllocGreedy] Attempt to split unspillable live in [...] adds 6f7cc38 [AVR] Add the ELF object file writer adds 1f0ef74 [LV] Build all scalar steps for non-uniform induction variables adds f216a86 Resubmit "Add llvm::enumerate() to STLExtras." adds 04c171a CVP. Turn marking adds as no wrap on by default (was turned o [...] adds dc91c2f [AMDGPU] Do not run scalar optimization passes at "-O0" adds 07f122b [AMDGPU] Ask subtarget if waitcnt instruction is needed befor [...] adds 69560a6 [AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based [...] adds 937044f [asan] Support dynamic shadow address instrumentation adds eabc8ab [Object] Define Archive::isEmpty(). adds c61677f [WebAssembly] Make register stackification more conservative adds 976632d [InstCombine] add tests for select X, (ext X), C adds b035d53 [libFuzzer] add a fuzzer test that finds CVE-2015-3193 adds 9faad58 Update loop unroller cost model to make sure debug info does [...] adds a7d748b cmake: Install the OCaml libraries into a more correct path adds baccf61 clean up tests and auto-generate checks adds a7eae48 [Coroutines] Part 15a: Lower coro.subfn.addr in CoroCleanup adds b76c0e4 [Coroutines] Part15b: Fix dbg information handling in coro-split. adds 32d667e [InstCombine] add tests for non-splat select(ext) adds 40fec41 [Coroutines] Part15c: Fix coro-split to correctly handle defi [...] adds f12f0e6 Revert test change in r282894 as it's broken in some platforms. adds 59fe6b0 [InstCombine] allow non-splat folds of select cond (ext X), C adds 189d5c4 Turn LLVM_ENABLE_ABI_BREAKING_CHECKS into a 0/1 definition li [...] adds 9ca7d08 Turn LLVM_USE_INTEL_JITEVENTS into a 0/1 definition. adds 9172a94 Turn LLVM_USE_OPROFILE into a 0/1 definition. adds 8a2343b GC NEED_USCORE. adds f39b9e0 GC STAT_MACROS_BROKEN. adds 2e683f1 GC TIME_WITH_SYS_TIME and TM_IN_SYS_TIME adds 2bf78b4 Convert ENABLE_BACKTRACES into a 0/1 definition. adds d8588ac Turn ENABLE_CRASH_OVERRIDES into a 0/1 definition. adds 68604c2 X86: Allow conditional tail calls in Win64 "leaf" functions ( [...] adds c4ff9fb Sort HAVE_LIBEDIT. adds b540020 GC HAVE_LIBDL, HAVE_LIBM and HAVE_LIBOLE32 adds 4c3dd49 HAVE_LINK_R is not the only reason why this needs config.h. adds f1086ea Retire NEED_DEV_ZERO_FOR_MMAP. It should be needed only on ou [...] adds 593505d Deal with the (historic) MAP_ANONYMOUS vs MAP_ANON directly b [...] adds d851cd5 GC STDC_HEADERS. adds e3674fa Sort LINK_POLLY_INTO_TOOLS. adds 513fcd6 Spell comment consistently with other library comments. adds 051cae6 GC HAVE_MMAP and HAVE_MMAP_FILE adds 93ae5d5 GC HAVE_LINK_EXPORT_DYNAMIC. adds 37e039e Fix expansion of HAVE_SYS_MMAN_H adds 11c0597 Correctly expand HOST_LINK_VERSION. adds dd9e07b GC HAVE___DSO_HANDLE adds be24ede GC ENABLE_PIC adds d79cc3d GC left-over from workarounds for missing pid_t and size_t adds e68f1f1 Sort LLVM_VERSION_INFO adds 9d24c09 Pass a filename instead of a msf::WritableStream to PDBFileBu [...] adds 3f7d165 Do not pass a superblock to PDBFileBuilder. adds 8948c79 NFC fix doxygen comments adds 66c32d5 NFC fix class members initialization adds 05539ce NFC Add const adds e4bd610 [libfuzzer] sancov documentation update adds 9e1ee71 [libFuzzer] move common parts of shell scripts into a separate file adds da69cda [AArch64][RegisterBankInfo] Use the static opds mapping for a [...] adds ce2d317 [AArch64][RegisterBankInfo] Rename getRegBankIdx to getRegBan [...] adds caf04a8 [AArch64][RegisterBankInfo] Refactor the code to access AArch [...] adds e4d60ad [AArch64][RegisterBankInfo] Compress the ValueMapping table a bit. adds 2bd65b5 [AArch64][RegisterBankInfo] Rename getValueMappingIdx to getV [...] adds e71d314 [AArch64][RegisterBankInfo] Use the helper functions for the checks adds 7d8f62d [SEH] Emit the parent frame offset label even if there are no [...] adds 5d78fc6 [libFuzzer] remove unused option adds 7faa446 [libFuzzer] fix openssl fuzzer tests when running on a machin [...] adds a179dcf ScheduleDAGInstrs: Cleanup, use range based for; NFC adds c5efc2c [llvm-objdump] Switch to a range loop. NFCI. adds b6b3db7 [libFuzzer] remove some experimental code adds 090f75d [ASAN] Add the binder globals on Darwin to llvm.compiler.used [...] adds 28901d9 [MC] Prevent out of order HashDirective lexing in AsmLexer. adds f46303a [libFuzzer] implement the -shrink=1 option that tires to make [...] adds fc85882 Use StringRef in Triple API (NFC) adds a5deba0 Use StringRef in LTOModule implementation (NFC) adds 65e620e Use StringRef in LTOCodegenerator (NFC) adds 494146d AMDGPU: Don't use offen if it is 0 adds 76315da Remove TargetTriple from AArch64MCInstLower as it's used in f [...] adds 0c50304 Stop calling getTargetTriple off of the AsmPrinter and constr [...] adds 26e89a7 Remove getTargetTriple and update all uses to use the Triple [...] adds 3e821f8 Revert "AMDGPU: Don't use offen if it is 0" adds 67f335d Use StringRef in Pass/PassManager APIs (NFC) adds 5e07fb3 Use StringRef in TLI instead of raw pointer (NFC) adds 798a8cd Use StringRef instead of raw pointer in MachinePassRegistry (NFC) adds b7d8ee4 Use StringRef in CommandLine Options handling (NFC) adds 6bd185b Use StringRef in Pass Info/Support API (NFC) adds b398ca6 Use StringRef in Datalayout API (NFC) adds 48435b0 Revert "Use StringRef in Datalayout API (NFC)" adds afe556b DIFlags: use StringRef instead of raw pointer (NFC) adds 0efcb40 Use StringRef in Datalayout API (NFC) adds dbe4e45 [AVX-512] Add VLX command lines to 128 and 256-bit shufffle tests. adds 825f7d8 [AVX-512] Add EVEX versions of VPBROADCASTW patterns with tru [...] adds d1fa61b Use StringRef instead of raw pointer in ExecutionEngine adds 876fe65 Use StringRef instead of raw pointer in TargetRegistry API (NFC) adds ec52cde Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInf [...] adds 102077e Revert "Use StringRef instead of raw pointer in TargetRegistr [...] adds b800476 [X86] Cleanup patterns for using VMOVDDUP for broadcasts. adds 1acd70c [libFuzzer] fix a recent bugs (buffer overflow) adds a27efcd Retire bugpoint's -R. hack. adds 83660ff GC HAVE_STRTOQ adds 120924c [libFuzzer] add fuzzer test for libxml2, finds https://bugzil [...] adds 1839f8a Retire LLVM_BINDIR and friends. They haven't been provided wi [...] adds 962713f Split a comment into generic description and note about the s [...] adds bf7d569 [OCaml] Install .mli (interface) files adds 310d306 [cmake] Make LIT_COMMAND configurable and improve fallback support adds c513af9 [cmake] Fix incorrect default for LIT_COMMAND, from r283029 adds 6bc4743 Revert "[MC] Prevent out of order HashDirective lexing in AsmLexer." adds f2993f0 [X86][SSE] Regenerate vselect tests and improve AVX1/AVX2 coverage adds f4f5451 Revert r283029 - [cmake] Make LIT_COMMAND configurable and im [...] adds 1c8d24e [X86][SSE] Enable commutation from MOVSD/MOVSS to BLENDPD/BLE [...] adds 55ce06a [X86][SSE] Always combine target shuffles to MOVSD/MOVSS adds a8904db Use StringRef in Registry API (NFC) adds 20e8247 [X86][SSE] Add support for combining target shuffles to binary BLEND adds fc651f7 Fix signed/unsigned warning adds 089e03e [CostModel][X86] Added fabs costs adds 793d2a4 Use StringRef for MemoryBuffer identifier API (NFC) adds 1df457a [CostModel][X86] Added fcopysign costs adds 4a24b14 [SLPVectorizer][X86] Added fabs tests adds a94243b [SLPVectorizer][X86] Added fcopysign tests adds 065e592 [CostModel][X86] Added tests for current fptosi/fptoui costs adds 1b14831 [SLPVectorizer][X86] Added fptosi/fptoui tests adds ec8ee2a [X86][SSE] Cleaned up shuffle decode assertion messages adds d17dee5 COFF: Fix short import lib import name type bitshift adds ca07d00 [SCEV] Remove commented out code; NFC adds 4e4cf39 [ConstantRange] Make getEquivalentICmp smarter adds afbfbca [SCEV] Rely on ConstantRange instead of custom logic; NFCI adds f6a95d4 Remove duplicated code; NFC adds 4c305be [PowerPC] Refactor soft-float support, and enable PPC64 soft float adds d300098 Revert r283057 and r283058 adds ca641f3 [X86] Fix indentation. NFC adds a8c3c60 [X86] Don't set i64 ADDC/ADDE/SUBC/SUBE as Custom if the targ [...] adds 9d7b8dc [X86][AVX] Ensure broadcast loads respect dependencies adds 7e696f0 [x86] add test to show unnecessary scalarization of copysign [...] adds 892bbf6 [x86] remove 'nan' strings from copysign assertions; NFC adds c36f800 Rangify for loops. adds bb9190f [X86][AVX2] Fix typo in test names adds 630a87a [X86][AVX2] Missed opportunities to combine to VPERMD/VPERMPS adds 53936b8 [ConstantRange] Make getEquivalentICmp smarter adds 4f64dd9 [SCEV] Rely on ConstantRange instead of custom logic; NFCI adds a96fb08 [X86][AVX2] Add support for combining target shuffles to VPER [...] adds 7036cb8 [X86] Mark all sizes of (V)MOVUPD as trivially rematerializable. adds 8fd6969 [AVX-512] Remove isCheapAsAMove flag from VMOVAPSZ128rm_NOVLX [...] adds dd1b9ba [PowerPC] Account for the ELFv2 function prologue during bran [...] adds 4d21682 [AMDGPU] Remove unused variables from SIOptimizeExecMasking adds 47cdc16 [lit] Compare to None using identity, not equality adds 245ab62 [lit] Remove unused imports (NFC) adds 1184da1 [lit] Throw in unimplemented method (NFC) adds 6fd795d [CodeGen] Adding a test showing the current state of poor cod [...] adds ec44dc9 [ARM] Code size optimisation to lower udiv+urem to udiv+mls i [...] adds 9920e54 Add new target hooks for LoadStoreVectorizer adds d89ff9a [X86][SSE] Add PR30371 (shuffle constant folding) test case adds 82f1243 AMDGPU: Fix missing -verify-machineinstrs in test adds 510a4bc AMDGPU: Fix typo adds 3e3a0a0 Prevent out of order HashDirective lexing in AsmLexer. adds 097e033 fix formatting; NFC adds da49ba4 Don't drop the llvm. prefix when renaming. adds 7b05e5c [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector [...] adds d1ed87a [RDF] Replace RegisterAliasInfo with target-independent code [...] adds 420bc56 [RTDyld] Fix a bug in RTDyldMemoryManager::deregisterEHFrames. adds 1c287c0 Use getSize instead of data().size(). NFC. adds 4fbe7c8 [RDF] Further improve readability of the graph adds ee3cdff Revert "Use getSize instead of data().size(). NFC." adds 9326308 Rename Error -> ReportError. adds 61f013c Jump threading: avoid trying to split edge into landingpad bl [...] adds 1e8f5fd [AMDGPU] Sign extend AShr when promoting (instead of zero extending) adds 49e7805 [AMDGPU] Pass optimization level to SelectionDAGISel adds ba1158f Refactor LICM pass in preparation for LoopSink pass. adds aa36ef2 [sancov] using env for better portability adds dd99e95 [PruneEH] Be correct in the face IPO adds f378e27 Add unit tests for StringSwitch. adds 4f52404 X86: Do not produce GOT relocations on windows adds f455558 AArch64Subtarget: Remove unused CPUString field adds 6f4042b [RDF] Fix liveness propagation through shadows adds 0a7ba88 [AArch64][RegisterBankInfo] Add getSameKindofOperandsMapping. adds e0c2ec2 [WebAssembly] Rename OPERAND_FP32IMM to OPERAND_F32IMM. adds e2559a8 [WebAssembly] Fix indentation. NFC. adds 5c1bdf9 [LTO] Fix test to not depend on the exact address of symbols, [...] adds 6b11127 Set some tests to an unknown vendor and OS adds 1596f9b [WebAssembly] Delete an unused function. NFC. adds 3d8b8c8 TargetMachine: Make the win32-macho workaround more specific. adds 6eb10d9 [lit] Use argparse instead of optparse adds bafb9a4 [WebAssemby] Clean up an obsolete comment. adds 3f22f87 [WebAssembly] Update to more stack-machine-oriented terminology. adds e602ff9 [MSSA] Allow unittests to use BasicAA when building. adds ff234ef Codegen: Tail-duplicate during placement. adds aba0070 Make GlobalsAA ignore dead constant expressions. adds 6b3629e [lit] Remove workaround for Python 2.5 adds 7789303 Revert "Codegen: Tail-duplicate during placement." adds dc1ddc0 AMDGPU: Factor SGPR spilling into separate functions adds 548c83d AMDGPU: Refactor indirect vector lowering adds bd79a59 [libFuzzer] change the probabilities so that we choose only t [...] adds e17aeae [X86] Add MOV8rm_NOREX to switch in isReallyTriviallyReMateri [...] adds eedfbe0 [libFuzzer] remove dfsan support and some related stale code. [...] adds 40960f6 [cmake] Use separate doctrees to prevent races between Sphinx [...] adds aeddc35 [cmake] Reintroduce (ldconfig-compatible) SOVERSIONs on share [...] adds d0e875c [Power9] Part-word VSX integer scalar loads/stores and sign e [...] adds 02ede7e Fix a test case failure on Apple PPC. adds a074ac8 Consistent fp denormal mode names. NFC. adds 1390211 [Object/ELF] - Avoid possible crash in getExtendedSymbolTable [...] adds e1a1a52 [SelectionDAG] Fix calling convention in expansion of ?MULO. adds cd988cd [Object/ELF] - Do not crash on invalid sh_offset value of REL [...] adds c072c50 [mips][fastisel] Consider soft-float an unsupported floating [...] adds 94ec1e3 [Power9] Exploit D-Form VSX Scalar memory ops that target ful [...] adds 61e54f8 Fix IntegerType::MAX_INT_BITS value adds 1ca4cdc Remove duplicated typedef. NFC. adds 22b0358 [RS4GC] Handle ShuffleVector instruction in findBasePointer adds cf04e5f [SLPVectorizer] Add a test with non-vectorizable IR. adds 7166679 Allow derived classes of OptimizationRemarkAnalysis in YAML adds 0089805 Serialize remark argument as a mapping to get proper quotatio [...] adds d894e4d [CMake] Exclude intrinsics_gen from LLVM_COMMON_DEPENDS in LL [...] adds b89fc68 Don't filter diagnostics written as YAML to the output file adds a8e8b59 [asan] LLVM: Switch to using dynamic shadow offset on iOS adds 4c9998f [sancov] renamed symcov-report-server to coverage-report-server adds 627f616 AArch64: Macrofusion: Split features, add missing combinations. adds 0030b47 [Support] Add case-insensitive versions of StringSwitch members. adds e8ae223 [cmake] Make LIT_COMMAND configurable and improve fallback support adds ef20529 [safestack] Requires a valid TargetMachine to be passed to th [...] adds ec53f4b Next set of additional error checks for invalid Mach-O files [...] adds b60ab5d [Target] move reciprocal estimate settings from TargetOptions [...] adds 06c72d0 Revert r283248. It caused failures in the hexagon buildbots. adds 296fa89 [cpu-detection] Copy simplified version of get_cpuid_max to r [...] adds 2638e45 Misc improvements to StringTableBuilder. adds 13e0592 Use StringRef in TableGen emitted API for attribute (NFC) adds e1acf77 [C API] Add LLVMConstExactUDiv and LLVMBuildExactUDiv functions. adds d0bf447 Use StringRef in TableGen (NFC) adds 062ace9 Codegen: Tail-duplicate during placement. adds ba4c13c Use StringRef in Support/Darf APIs (NFC) adds e57a377 Use StringRef instead of raw pointers in ARMBuildAttrs (NFC) adds c441cc0 Revert "Use StringRef in Support/Darf APIs (NFC)" adds d277734 [libFuzzer] clear the corpus elements if they are evicted (i. [...] adds a2df9c8 Re-commit "Use StringRef in Support/Darf APIs (NFC)" adds c95d4ff [LoopDistribute] Fix a typo in the pass name. adds 280c2a6 Use StringRef in DarwinAsmParser (NFC) adds 3eff5cd Use StringRef in MCSectionMachO (NFC) adds ef350f2 Revert "Re-commit "Use StringRef in Support/Darf APIs (NFC)"" adds d4d50f6 [libFuzzer] add ShrinkValueProfileTest, move code around, NFC adds ba066c0 Use StringRef in ARCRuntimeEntryPoints APIs (NFC) adds 1455db3 Use StringRef in StringSaver API (NFC) adds bc4286d Use StringRef in FastISel API (NFC) adds d03fefc Revert "Codegen: Tail-duplicate during placement." adds 33a6ab0 Use StringRef in ARMConstantPool APIs (NFC) adds 6f45c30 Blind attempt to fix windows build after r283290 - Use String [...] adds f6b865d [Support][CommandLine] Add cl::getRegisteredSubcommands() adds bad1f71 [AVR] Add the machine code backend adds f9bb6bc Re-commit "Use StringRef in Support/Darf APIs (NFC)" adds 59cb8c3 [AVR] Add definitions for the ATTiny102 and ATtiny104 chips adds fac3438 [AVR] Enable the instruction printer in the target definition adds 83aed69 [AVR] Split all of the AVR device definitions into a separate file adds 3aff1d4 [AVR] Add the AVR frame lowering code adds 27025b7 [AVR] Update return type of dynamic alloca pass adds c29dc70 Fix machine operand traversal in ScheduleDAGInstrs::fixupKills adds 3d6fe50 [AVR] Add AVRRegisterInfo::splitReg function adds 3beccae [AVR] Don't select 'MOVW' instructions when they are not supported adds 464fb84 Test commit permission adds 83acfbf Test commit permission adds 471e290 [X86] Fix some tests that didn't assert anything adds 71beb00 [Thumb] Don't try and emit LDRH/LDRB from the constant pool adds 8bebbdc [X86] Don't randomly encode %rip where illegal adds 20d3d70 Revert "[mips] Add rsqrt, recip for MIPS" adds 8e07f28 Revert r282920 "X86: Allow conditional tail calls in Win64 "l [...] adds e16f30e Recommit: "[mips] Add rsqrt, recip for MIPS" adds b53fb3c Don't pass null to memcpy. Should fix the asan bots. adds 5844b06 Add llvm::enumerate() range adapter. adds e53904e Fix build due to comparison of std::pairs. adds 54f81ef Test commit permission. NFC adds 17676e0 [DAG] Teach computeKnownBits and ComputeNumSignBits in Select [...] adds 92d577b Revert "[asan] LLVM: Switch to using dynamic shadow offset on iOS" adds 1c07569 [LV] Add isScalarWithPredication helper function (NFC) adds 27b0f61 [mips][ias] fix li macro when values are negated with ~ adds a0848c8 [LV] Add helper function for predicated block probability (NFC) adds 4c9fcf5 Improve DEBUG_VALUE assembly comments for spilled bitpieces adds c55049e Allow the caller to pass in the hash. adds 5e827ba fix documentation comments; NFC adds e7491dd [LV] Use getScalarizationOverhead in memory instruction costs (NFC) adds c3d2cc5 [LV] Remove obsolete comment (NFC) adds 81c297e FastISel: Remove unused/un-overridden entry points. NFCI. adds 82f62ff [LV] Pass legality analysis in vectorizer constructor (NFC) adds 29db06c AMDGPU: Do not re-use tmpreg in spill/restore lowering adds f4de15f [RDF] Fix live def propagation through basic block adds 798edac [LV] Pass profitability analysis in vectorizer constructor (NFC) adds 8f952a8 Improve the debug-info test created in r274263. adds e249e2a [asan] Reapply: Switch to using dynamic shadow offset on iOS adds 7326421 [ADT] Add missing const_iterator DenseSet::find() const adds 5366649 [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MU [...] adds 8c96de4 [ARM] Use __rt_div functions for divrem on Windows adds 1911873 [Object] Fix a crash in Archive::child_iterator's default con [...] adds ba129eb [codeview] Translate bitpiece metadata to DEFRANGE_SUBFIELD* records adds 6a6f29c [WebAssembly] Add binary-encoding opcode values to instructio [...] adds 5ea3570 Verifier: Reject any unknown named MD nodes in the llvm.dbg n [...] adds 8be61a8 Modify df_iterator to support post-order actions adds 2a4f206 [DAG] change test to use 'unsafe' function attribute instead [...] adds 87bf019 Fix the build with MSVC 2013, still cannot default move ctors yet adds 81e3914 Remove extra semicolon adds 6af7eec Add an llvm-opt-report tool to generate basic source-annotate [...] adds 5f1ad48 Revert "Verifier: Reject any unknown named MD nodes in the ll [...] adds 3d7360f Verifier: Reject any unknown named MD nodes in the llvm.dbg n [...] adds 0837bf4 [llvm-opt-report] Distinguish inlined contexts when optimizat [...] adds 193dcc8 [codeview] Truncate records to maximum record size near 64KB adds c5aa287 Add missing #include from r283039. Found by modules build. adds 51ab65f Fix tests for Windows adds cc6cbfd [libFuzzer] refactoring to make -shrink=1 work for value prof [...] adds d26d793 [DAG] add tests to show missing checks for SDNode FMF adds aca3411 [libFuzzer] when re-running for lsan, don't look at the coverage adds bb3823e [AMDGPU] Promote uniform i16 bitreverse intrinsic to i32 adds 8926801 [libFuzzer] be more careful with memory usage, print peak rss [...] adds fc05fb6 [Triple] Add triple for Fuchsia adds 3ea0d22 [ARM] Improve testcase for r283323 adds 3747be0 [ARM] Constant pool promotion - fix alignment calculation adds 9f79578 fix build on cygwin Cygwin has dlfcn.h, but no Dl_info adds 45cea08 [EfficiencySanitizer] Adds shadow memory parameters for 40-bi [...] adds c4e191a [ValueTracking] Teach computeKnownBits and ComputeNumSignBits [...] adds c2afd0c Add test-cases which demontrate pr30561 adds 25ec259 AMDGPU: Partially fix reported code size for some instructions adds d4d21fd Test commit access (NFC) adds a172b8d [llvm-opt-report] Print line numbers starting from 1 adds 44f7288 Revert "[ARM] Use __rt_div functions for divrem on Windows" adds 7b08fb4 [llvm-opt-report] Record VF, etc. correctly for multiple opts [...] adds 78f1992 [RDF] Replace potentially unclear autos with real types adds 630fd01 [RDF] Replace some expensive copies with references in range- [...] adds 493d9f9 Use range loop. NFC. adds 7161c1a [RS4GC] Fix comment to show TODO. NFC adds 665e976 [AMDGPU] Disassembler: print label names in branch instructions adds 2d767eb GlobalISel: fix misuse of using declaration in test. adds 605a3d0 Refactor duplicated typedefs. NFC. adds 42b70df Refactor to use getSectionContentsAsArray. adds ddec8ab Centralize sh_entsize checking. adds 54de287 Revert "Use StringRef in LTOModule implementation (NFC)" adds c8f9ada [X86] Fix intel syntax push parsing bug adds 30ab32f AArch64: Move remaining target specific BranchRelaxation bits to TII adds c205b62 Move AArch64BranchRelaxation to generic code adds 38b9b47 BranchRelaxation: Account for function alignment adds 1418f15 [Hexagon] Avoid replacing full regs with subregisters in tied [...] adds ecc6c2b BranchRelaxation: Support expanding unconditional branches adds b3f94cd [docs] Add PR to Lexicon adds 5991ecc AMDGPU: Support using tablegened MC pseudo expansions adds 37a1259 Revert "AMDGPU: Support using tablegened MC pseudo expansions" adds 19f1f66 Reapply "AMDGPU: Support using tablegened MC pseudo expansions" adds de50b32 AMDGPU: Remove leftover implicit operands when folding immediates adds bda4e02 Add -strip-nonlinetable-debuginfo capability adds ba29379 AMDGPU: Remove scheduling info from si_mask_branch adds 5f58f8e AMDGPU: Don't fold undef uses or copies with implicit uses adds 33fe838 Revert "Add -strip-nonlinetable-debuginfo capability" adds 1ac5295 [DAG] Generalize build_vector -> vector_shuffle combine for m [...] adds b3650b5 [X86][SSE] Add f16/f80/f128 vector sitofp test cases adds f978224 [X86] Preserve BasePtr for LEA64_32r adds bb6f9b5 [PGO] Create weak alias for the renamed Comdat function adds e936b22 Handle *_EXTEND_VECTOR_INREG during Integer Legalization adds 65236ec Preserve the debug location when CodeGenPrepare sinks a compa [...] adds a5e77a0 [WebAssembly] Remove the output operand from stores. adds d8d953e [WebAssembly] Remove loop's bottom label. adds 12bd3d1 [WebAssemby] Implement block signatures. adds 4a0edca Delete some dead code in SelectionDAG (NFC) adds 27ab1b8 [Hexagon] NFC. Canonicalizing absolute address instruction names. adds 647e467 Add a static_assert to enforce that parameters to llvm::forma [...] adds 5f95e5b Revert "Add a static_assert to enforce that parameters to llv [...] adds d225df2 [LV] Remove triples from target-independent vectorizer tests. NFC. adds ff22dc3 [Hexagon] NFC Removing 'V4_' prefix from duplex instruction names. adds a425991 Target: Remove unused patterns and transforms. NFC. adds 28b12d7 [llvm-opt-report] Use -no-demangle to disable demangling adds 433ffa6 [SimplifyCFG] Correctly test for unconditional branches in Ge [...] adds 68dd546 [llvm-opt-report] Left justify unrolling counts, etc. adds 837bcf7 [llvm-opt-report] Left justify unrolling counts, etc. adds 0b0321b AMDGPU: Change check prefix in test adds 61fdf5d [AVR] Add the AVRMCInstLower class adds de084c5 [X86] Remove unused PatFrags. NFC adds 0885462 [X86] Fix patterns for VPMULLD and VPCMPEQQ to not require al [...] adds a259671 Revert "Revert "Add a static_assert to enforce that parameter [...] adds a47cbd9 Use StringReg in TargetParser APIs (NFC) adds f3907ed AMDGPU: Fix use-after-free in SIOptimizeExecMasking adds 744a261 Use StringRef in ARMELFStreamer (NFC) adds 9dc8cca [ARM] Don't convert switches to lookup tables of pointers wit [...] adds ccab471 [SLPVectorizer] Fix for PR25748: reduction vectorization afte [...] adds c5606f9 [X86][SSE] Update register class during MOVSD/MOVSS - BLENDPD [...] adds a297939 [ARM]: Add Cortex-R52 target to LLVM adds c3339a5 [ARM] Reapply: Use __rt_div functions for divrem on Windows adds e3eba57 [ARM]: add missing switch case for cortex-r52 adds 674bd2c Remove spurious non-printable character from source file. adds 2d50d3f [AMDGPU] Promote uniform (i1, i16] operations to i32 adds 8b2bb5d [ValueTracking] Fix crash in GetPointerBaseWithConstantOffset() adds fbd12bb [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';' adds 64cb991 [X86][SSE] Tidied up tests - use standard check prefixes adds a7de0c7 [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getN [...] adds 5cbeeed Only track physical registers in LivePhysRegs adds cf5c0d7 [LV] Don't mark multi-use branch conditions uniform adds 588a795 Invoke add-discriminator at -g0 -fsample-profile adds 97a1f76 [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_stor [...] adds 8a6c2f9 [X86][SSE] Reapplied: Add vector fcopysign combine tests adds 9aa8644 AMDGPU/SI: Emit fixups for long branches adds db695f4 New utility to visualize optimization records adds 7a0dadb [InstCombine] fold select X, (ext X), C adds db0b3fa [LoopIdiomRecognize] Merge two if conditions into one. NFCI. adds c16b74e Recommit "Use StringRef in LTOModule implementation (NFC)"" adds 3d9f320 [Hexagon][NFC] Using documented instruction type name V4LDST [...] adds e25a48d [RS4GC] Strengthen coverage: add more tests adds b44dba3 AMDGPU/SI: Add support for 8-byte relocations adds 7e1f502 [DAG] move fold (select C, 0, 1 -> xor C, 1) to a helper func [...] adds b6ae30c [InstCombine] Don't unpack arrays that are too large adds 65f9ae1 [cmake] Treat polly as "in tree" if LLVM_EXTERNAL_POLLY_SOURC [...] adds 254b4d2 Refactor Symbol visitor code. adds 4be86fd Add missing include. adds 6d57e1c [InstCombine] Don't unpack arrays that are too large (part 2). adds 72ac867 [DAG] clean up foldSelectOfConstants(); NFCI adds c4f04d9 swifterror: Don't compute swifterror vregs during instruction [...] adds 71c3126 Codegen: Tail-duplicate during placement. adds 4e0ea1b AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer adds a663737 [AVR] Add the assembly printer adds f267cd7 [docs] Fix indentation bug in LangRef. adds a118449 [coroutines] Store an address of destroy OR cleanup part in t [...] adds 7b70b8a [llvm-opt-report] Don't leave space for opts that never happen adds 8d09276 [AVR] Add missing subdirectories to LLVMBuild adds 713cee5 [AVR] Add dependencies to AVR libraries in AVRCodeGen adds db1d168 [AVR] Set up the instruction printer and the assembly backend adds dc87e8e [AVR] Add the 'SoftFail' field to all instruction formats adds 2884d8d [AVR] Expand MULHS for all types adds 942ffca Allow a maximum of 64 bits to be returned in registers adds 056a448 [AVR] Use references rather than pointers in AVRISelLowering adds ca1844d [AVR] Don't shadow container while iterating in range-based loop adds 8af8e34 [AVR] Don't worry about call frame size when initializing fra [...] adds b57fbc7 Fix incorrect assertion in AVRFrameLowering.cpp adds 2ce5ded [pdb] Dump Module Symbols to Yaml. adds 97c245f [AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txt adds 473ebca Revert "Codegen: Tail-duplicate during placement." adds 7c9eed7 Requires the AVR backend for running test/CodeGen/AVR adds 7fe28f8 ThinLTO: handles modules with empty summaries adds ccef33b ThinLTO: don't perform incremental LTO on module without a hash adds 98a1ca1 [OptRemarks] Remove non-printable chars from function name adds a3cf93a [AArch64] Avoid generating indexed vector instructions for Exynos adds fd33922 [ThinLTO] Record calls to aliases adds 5c5bdd1 [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for m [...] adds ba555e4 [X86][AVX2] Regenerate and add 32-bit tests to core tests adds 1ee8d60 [X86] Apply the Update LLC Test Checks tool on the rotate tests. adds 9230bef [AVX-512] Fix a bug in getLargestLegalSuperClass where we inf [...] adds 7e93344 [AVX-512] Add test case for PR30430 that I should have added [...] adds 49695dd Fix comment typos - full update script path in assertions note adds 3ffe113 Turn cl::values() (for enum) from a vararg function to using [...] adds e5a054e [X86][SSE] Regenerate and add 32-bit tests to widening tests adds 97486b9 Revert "[X86] Apply the Update LLC Test Checks tool on the ro [...] adds bc45733 [X86][SSE] Regenerate select tests adds c628031 [libFuzzer] fix use-after-free in libFuzzer found by ... fuzzing. adds 19e25ec [libFuzzer] control the reload interval by a flag, make it 10 [...] adds e3e8677 ThinLTO: Fix Gold test after caching fix in r283655 adds 1a60ba8 [libFuzzer] when shrinking the corpus, delete evicted files p [...] adds 0600ead [libFuzzer] make a test less flaky adds 3e9af52 [AVX-512] Add the vector down convert instructions to the sto [...] adds 7f2459e [AVX-512] Add avx512dq to the fp stack folding test. adds f1bd24e [AVX-512] Add subvector insert and extract to load/store fold [...] adds 6f158fa Target: Remove unused entities. adds c0eb209 MC: Remove unused entities. adds 993d492 [AVX-512] Fix execution domain for EVEX encoded VINSERTPS. adds 23bd7de DAG: Setting Masked-Expand-Load as a variant of Masked-Load node adds 203696c [X86] Improve the rotate ISel test adds 3dbf19e [X86] Adding the 'nounwind' attribute to test functions for c [...] adds 373988f [llvm-link] Fix description of -disable-lazy-loading option adds dfd8008 [CMake] Correct configuration order of the sub-projects based [...] adds ae5f5d3 Move the global variables representing each Target behind acc [...] adds 59e8dbd [X86] Remove redundant patterns. The same pattern appears a f [...] adds 7cdcbfe [AVX-512] Port 128 and 256-bit memory->register sign/zero ext [...] adds f475fa9 [lit] Remove Python 2.6 and below exec workaround adds ef54187 [lit] Remove unused variable in googletest format adds 4bf8ed1 [lit] Remove semicolons in Python code adds cb351a4 [lit] Fix undefined symbol ArgumentError adds 996fc5b [lit] Remove unused TestingProgressDisplay attr adds 56f40f8 [lit] Remove (or allow specific) unused imports adds 82ef6d6 [AVR] Enable generation of the TableGen assembly writer tables adds a6c37a9 [x86][inline-asm][llvm] accept 'v' constraint adds 115e76c [AVX-512] Add an AVX512VL/BW command line to sse41-pmovxrm.ll [...] adds 21c40c6 [AVX-512] Add test cases for AVX512 sign/zero extend instruct [...] adds a9268c4 [AVX-512] Add missing pattern sext or zext from bytes to quad [...] adds a56b5b5 Fix WebAssembly build after r283702. adds 2bf22e3 This pass, fixing an erratum in some LEON 2 processors ensure [...] adds a281f4e [Object/ELF] - Do not crash on invalid Header->e_shoff value. adds 5d0ca9b Fixed windows stdout/stderr redirection in inline asm constra [...] adds 155a6ef [SLPVectorizer][X86] Fixed alignments of scalar loads in sito [...] adds be507f5 [SLPVectorizer][X86] Add avx512 sitofp/uitofp tests adds 5ba17d7 [SLPVectorizer][X86] Add 512-bit sitofp/uitofp tests adds bca70fa [X86] Prefer rotate by 1 over rotate by imm adds 86a17fd Add return type for checkForValidSection parsing function. NF [...] adds e587b6c [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian [...] adds f086ef8 [ADT] Let MapVector handle non-copyable values. adds a5afae3 [ADT] Add make_pointe{e,r}_iterator. adds a2e3c5a Use unique_ptr in LLVMContextImpl's constant maps. adds bd90bcc Add llvm::apply to STLExtras. adds c02fe89 Update documentation after r283671 ("Turn cl::values() (for e [...] adds f52f4a4 [ADT] Attempt to fix MSVC 2015 ICE via judicious addition of [...] adds 4970f01 Teach llvm::StripDebugInfo() about global variable !dbg attac [...] adds ec2f01d [ADT] Remove make_pointe{e,r}_iterator, because it seems to c [...] adds 15796d2 Use StringRef in TableGen generated Intrinsics.gen file (NFC) adds 58ae36f [ADT] Don't use make_pointee_iterator in IteratorTest. adds 5556ebb [ADT] Use () instead of {} in an attempt to work around MSVC [...] adds 779825d [SelectionDAGBuilder] Support llvm.flt.rounds on targets wher [...] adds 31b90a7 Disallow ArrayRef assignment from temporaries. adds 1793ab4 Rename llvm::apply -> llvm::apply_tuple. adds b260e3a Revert "Disallow ArrayRef assignment from temporaries." adds d9a6f65 Rename isHotFunction/isColdFunction to isFunctionEntryHot/isF [...] adds 4344a28 GlobalISel: support selecting constants on AArch64. adds f3542ee GlobalISel: support selecting G_GEP instructions. adds 138850b GlobalISel: allow G_GLOBAL_VALUEs in AArch64 legalization. adds b725b3c GlobalISel: select G_GLOBAL_VALUE uses on AArch64. adds 1a78cfa [x86] auto-generate checks adds 8e372b2 [x86] auto-generate checks adds d735fd7 Revert r283690, "MC: Remove unused entities." adds cf0683e Fix llvm-lit.in corresponding to r283710. adds 420b9a4 Fix issue which cases lit installed with setup.py to not reso [...] adds 7ca9688 Define DbiStreamBuilder::addDbgStream to add stream. adds 9c78fe6 Fix a bug in DbiStreamBuilder::addDbgStream. adds 51c08b7 Revert r283824 and r283823: Define DbiStreamBuilder::addDbgSt [...] adds 589c5da [AArch64][MachineLegalizer] Mark v2s32 G_LOAD as legal. adds 082e838 [AArch64][InstructionSelector] Teach the selector how to hand [...] adds 7d96c0b [AArch64][InstructionSelector] Teach how to select FP load/store. adds 3656542 [InstCombine] Transform !range metadata to !nonnull when comb [...] adds 25d9f11 [RegAllocGreedy] Attempt to split unspillable live intervals adds a0151b6 [libFuzzer] add switch tests adds bb0318a [libFuzzer] implement value profile for switch, increase the [...] adds be53d7c Codegen: Tail-duplicate during placement. adds 8ee2011 MIRParser: Rewrite register info initialization; mostly NFC adds 48d3354 MIRParser: generic register operands with types adds ddd1430 Fix warning; NFC adds 87ba455 Tune isHotFunction/isColdFunction adds 6a59bc7 Make RandomNumberGenerator compatible with <random> adds c616898 Use LLVM_CONSTEXPR to appease MSVC2013 (fixup for r283854) adds ebc8a28 Revert "Codegen: Tail-duplicate during placement." adds 54bf85d Reverted r283740 [Object/ELF] - Do not crash on invalid Heade [...] adds 33a142a Fix formatting in findRegisterUseOperandIdx. NFC. adds 8d8506a [AArch64] Allow label arithmetic with add/sub/cmp adds f903c00 [ARM] Fix registers clobbered by SjLj EH on soft-float targets adds 3addd05 [Thumb] Save/restore high registers in Thumb1 pro/epilogues adds 188a521 [Support/ELF] - Add OpenBSD PT_OPENBSD_RANDOMIZE, PT_OPENBSD_ [...] adds 5988ab8 [x86] update test to use FileCheck and auto-generate checks adds 00eb3c9 [LCSSA] Implement linear algorithm for the isRecursivelyLCSSAForm adds 4566b7e [DAG] fix formatting; NFC adds b46e570 [X86][SSE] Regenerate vsplit and tests adds ecea8e1 [X86][SSE] Regenerate vector load-trunc test adds 53927c2 [X86][SSE] Regenerate scalar i64 uitofp test adds 8a60c21 [DAG] hoist DL(N) and fix formatting; NFC adds b3c22e4 [DAG] simplify logic; NFC adds ed36d63 [cl] Don't print subcommand help when no subcommands present. adds 2683a2d AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11. adds 7535c84 [x86] add tests to show missed folds for masked bools adds 43573fb [opt-viewer] Convert another HTML output to use a multiline string adds 2b64f4d [opt-viewer] Print hotness as percentage of the maximum hotness adds f4b8d7b [opt-viewer] Remove unnecessary call to demangle adds 809c6df Silence unused warning in non-assert builds. adds 4cc2f1f [DAG] add fold for masked negated extended bool adds 87a2222 Fix test on non-x86 hosts adds e19c4b6 Let test pass for builds that support X86, but do not default to it adds 7d08f7a [x86] add sext variants of tests added with r283894 adds 14c8ab9 [DAG] add fold for masked negated sign-extended bool adds bd4001e Reformat. adds c563fca ARMMachineFunctionInfo.cpp: Add an initializer of ARMFunction [...] adds 749baf3 [AMDGPU] Fix test that was broken by rL283893 adds be78316 [Support] Fix undefined behavior in RandomNumberGenerator. adds d7177be Fix "static initialization order fiasco" for the XCore Target. adds ef587f5 Avoid unnecessary constexpr to appease MSVC 2013 adds 1d2f9bc Allow Switch instruction to have extractProfTotalWeight calle [...] adds c7a23a5 [AMDGPU] Refactor waitcnt encoding adds 86a0c0d [raw_ostream] Raise some helper functions out of raw_ostream. adds 3d30248 Fix build error on LP64 platforms. adds 21fcbeb [sanitizer-coverage] use private linkage for coverage guards, [...] adds a85b243 Re-submit r283823: Define DbiStreamBuilder::addDbgStream to a [...] adds 4ba2b03 Silence -Wunused-but-set-variable warning adds db0c8c6 Avoid braced initialization for default member initializers f [...] adds 6f185f6 [x86] add tests for negate bool adds 2a18018 Codegen: Tail-duplicate during placement. adds 8f3f50a Re-apply "Disallow ArrayRef assignment from temporaries." adds 4c7a4f4 MIRParser: allow types on registers with a RegBank. adds 6a493c6 GlobalISel: support selection of extend operations. adds 63d2a1d Revert "[Thumb] Save/restore high registers in Thumb1 pro/epilogues" adds 9a96669 Next set of additional error checks for invalid Mach-O files [...] adds 7b65cae Re-land "[Thumb] Save/restore high registers in Thumb1 pro/ep [...] adds 61ec54d [libFuzzer] refactoring to speed things up, NFC adds 426fd51 [InstrProf] Add support for dead_strip+live_support functionality adds f8322a8 GlobalISel: support same-size casts on AArch64. adds 13a7e10 [DAG] Fix crash in build_vector -> vector_shuffle combine adds 47b7d1a Fix the stage2 MSVC 2013 build with less constexpr in RNG adds 13774ee [PPCMIPeephole] Fix splat elimination adds d886dc4 GVN-hoist: fix store past load dependence analysis (PR30216, [...] adds e8c434e Memory-SSA cleanup of clobbers interface, NFC adds 53d343b [lit] Run unit tests as part of lit test suite adds 707afd5 [AArch64][MachineLegalizer] Mark more bitcasts as legal. adds 5c48aae [AArch64][InstructionSelector] Fix typos in the related mir f [...] adds 5800485 [AArch64][InstructionSelector] Refactor the handling of copies. adds 4b65f0e [AArch64][InstrustionSelector] Teach the selector about G_BITCAST. adds 77bcac9 [AArch64][InstructionSelector] Fix unintended test changes in [...] adds 6f0cfa7 Revert "[libFuzzer] refactoring to speed things up, NFC" adds 94162a4 [LCG] Add the necessary functionality to the LazyCallGraph to [...] adds 32e2e9a [LCG] Cleanup various places where comments said `SCC` but me [...] adds 126de93 Add AArch64 unit tests adds c45984b [Support/ELF] - Sort PT_OPENBSD_* added previously. NFC. adds 196e704 [Support][CommandLine] Display subcommands in help when there [...] adds 3f978ba [InstCombine] Fix constexpr issue in select combining adds 1a62037 NFC: The Cost Model specialization, by Andrey Tischenko adds 7e18f7d [CVP] Convert an AShr to a LShr if 1st operand is known to be [...] adds b34a186 [DAGCombiner] Do not remove the load of stored values when op [...] adds 58682d3 [DAGCombiner] Update most ADD combines to support general vec [...] adds 597ed35 [MC] Fix Error Location for ParseIdentifier adds 14cd5a9 BranchRelaxation: Unique live ins when creating block adds db1717e [ValueTracking] An improvement to IR ValueTracking on Non-neg [...] adds 6589a4e AMDGPU/SI: Change mimg intrinsic signatures adds f2e490a [X86] Add the v4i32 flavor test-case for pr30371 adds 7e2ade4 AMDGPU: Add instruction definitions for VGPR indexing adds 8ef2e47 [SimplifyCFG] Don't create PHI nodes for constant bundle operands adds 256d6fe [ThinLTO] Don't link module level assembly when importing adds 7b6a558 AMDGPU: Initial implementation of VGPR indexing mode adds 7227e00 [ADT] Zip range adapter adds 7479130 Do not remove implicit defs in BranchFolder adds fed07c1 Revert "[ADT] Zip range adapter" adds e0ace4a [ThinLTO] Fix bot failure due to unused variable with NDEBUG adds d84bb1c LTO: Use the correct mangler function in LTOCodeGenerator::ap [...] adds 6ceda53 [LoopUnroll] Use the upper bound of the loop trip count to fu [...] adds dd572aa Fix testcases failing after r284036 adds 3d05abf Revert "[LoopUnroll] Use the upper bound of the loop trip cou [...] adds b15c258 [MIRParser] Parse lane masks for register live-ins adds b893afb Reapply "[LoopUnroll] Use the upper bound of the loop trip co [...] adds e58533d [lit] Fix FormatError on individual test timeout adds dee2afd [lit] Fix test shtest-timeout.py for modern output adds 6cf9f6d Update _MSC_VER equality checks for msdiaNNN.dll adds 16bf208 Create llvm.addressofreturnaddress intrinsic adds 98f853e [Coverage] Factor out logic to create FunctionRecords (NFC) adds d05e76c [Coverage] Delete some copy constructors (NFC) adds 3d62534 [unittest] Pass a reference instead of making a copy (NFC) adds f466ec4 [unittests] Delete some copy constructors (NFC) adds 7c9f5f9 [unittests] Delete even more copy constructors (NFC) adds 110db83 GlobalISel: mark G_BRCOND on s1 as legal. adds 8e4c061 GlobalISel: select G_BRCOND instructions on AArch64. adds 7bd256d GlobalISel: support selection of G_ICMP on AArch64. adds e205ee4 GlobalISel: select G_FCMP instructions on AArch64. adds 8394d5d GlobalISel: support int <-> float conversions on AArch64. adds 5c4187e GlobalISel: support G_TRUNC selection on AArch64. adds 6dcccf4 Handle lane masks in LivePhysRegs when adding live-ins adds d6afe38 Moving to GitHub - Unified Proposal adds fc61cb5 fix title underline length adds d48e8c6 [GitHubMove Doc] Properly nest a subsection in the proposal adds c0fa9af fix function label name in addressofreturnaddress test adds 910b53f [AArch64][RegisterBankInfo] Provide more realistic copy costs. adds d53b5ad [AArch64][RegisterBankInfo] Use a proper cost for cross regba [...] adds 7d96cfe [AArch64][RegisterBankInfo] Bump the cost of vector loads. adds df3941c [AArch64][MachineLegalizer] Mark more G_BITCAST as legal. adds d8bc7a1 [AArch64][RegisterBankInfo] Use static mapping for same bank [...] adds 342fb3e [AArch64][RegisterBankInfo] Describe cross regbank copies sta [...] adds dd19d1b Revert "GVN-hoist: fix store past load dependence analysis (P [...] adds 6837af0 [AArch64][RegisterBankInfo] Provide alternative mappings for [...] adds db2e326 Correct PrivateLinkage for COFF adds 10c5084 [AArch64][RegisterBankInfo] Provide alternative mappings for [...] adds 0d25a93 commit back "GVN-hoist: fix store past load dependence analys [...] adds 7c621c7 Memory-SSA: strengthen defClobbersUseOrDef interface adds 350bc2e [X86] Simplify the lowering code for extracting and inserting [...] adds bc668c9 Remove a FIXME that I forgot about. NFC. adds c42ce5a [AVX-512] Add tests for basic 512-bit zero extending shuffle [...] adds 6c06855 [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends. adds 1c62059 [AVX-512] Fix v16i32 zero extending shuffle test case so it's [...] adds c678874 Silence unused warning in non-assert builds. adds 4b6c339 [X86] Basic additions to support RegCall Calling Convention. adds 00d9ddd [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1 [...] adds 9f063fb [mips] Add IAS support for dvp, evp adds 3339279 AMDGPU: Fix truncate to bool warnings adds 9dbdf67 [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A folding adds 8517cfc Copy+pasts typo in comment describing combine test adds c31d80d AMDGPU: Assume spilling will occur at -O0 adds 97ca021 [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (s [...] adds 262bc11 [LV] Avoid rounding errors for predicated instruction costs adds 2061c51 [x86] add negate-i1 run for 32-bit target adds a913b4a [LV] Account for predicated stores in instruction costs adds 172d6c0 [ARM]: Assign cost of scaling used in addressing mode for ARM cores adds e0d080d Do not delete leading ../ in remove_dots. adds dc99d00 Fix for PR30687. Avoid dereferencing MBB.end(). adds 53176d2 [libFuzzer] reapply r283946: refactoring to speed things up, [...] adds d942282 [X86][AVX512] Fix sext v32i1 -> v32i8 lowering. Fix PR30600. adds 87963ed [unittests] Remove a redundant test fixture (NFC) adds 6f0e74d Truncate long names in type records adds 26cb3d9 Add interface to compute number of physical cores on host system adds b08e3a6 [safestack] Move X86-targeted tests into the X86 subdirectory. adds 68e8f61 [AArch64][RegisterBankInfo] Switch to fully static opds mappi [...] adds f980fc0 [libFuzzer] add -trace_malloc= flag adds 19dc709 In visitSTORE, always use FindBetterChain, rather than only w [...] adds 154f790 [RAGreedy] Empty live-ranges always succeed in last chance re [...] adds 080559c Revert "In visitSTORE, always use FindBetterChain, rather tha [...] adds fcfb682 New llc option pie-copy-relocations to optimize access to ext [...] adds 120f92e [safestack] Reapply r283248 after moving X86-targeted SafeSta [...] adds e900cee LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE adds 76edd8d [libFuzzer] more detailed message for disabled leak detection adds 52b9988 [DAG] hoist DL(N) and fix formatting; NFC adds b0c1779 CodeGen: adjust floating point operations in Windows itanium adds 6ec5391 CodeGen: use MSVC division on windows itanium adds 0a9d04f Add interface for querying physical hardware concurrency adds ca81740 Timer: Fix doxygen comments, use member initializer; NFC adds 15a3555 Add `llvm::` in clEnumVal macro (NFC) adds aa6ce79 [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative rel [...] adds 84208dd [AMDGPU] Add 32-bit lo/hi got and pc relative variant kinds a [...] adds a91924b [AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds [...] adds c675e31 Tidy up example of getting the pointer size. adds ea40df3 Tidy the calls to getCurrentSection().first -> getCurrentSect [...] adds 172ce59 In preparation for removing getNameWithPrefix off of TargetMa [...] adds cfa4f53 [DAGCombiner] Teach createBuildVecShuffle to handle cases whe [...] adds e0043a3 [x86][ms-inline-asm] use of "jmp short" in asm is not supported adds 5d66203 AMDGPU: Fix use-after-frees adds 5acb9d0 [mips] Fix aui/daui/dahi/dati for MIPSR6 adds 9b21983 Fix use-after-frees adds d1a990d [GlobalISel] Get the AArch64 tests to work on Linux adds 877e3be AMDGPU: Select 64-bit {ADD,SUB}{C,E} nodes adds 7f74dec [x86] add tests to show missing folds for negated shifted sign bit adds 66c0dee [DAG] add folds for negated shifted sign bit adds 9b8425d Define "contiki" OS specifier. adds 1d3aece [InstCombine] sub X, sext(bool Y) -> add X, zext(bool Y) adds e6ec388 [InstCombine] update test to use FileCheck and auto-generate checks adds e2ba2cb [InstCombine] remove redundant test adds a85c77d [InstCombine] auto-generate checks adds 328dede [InstCombine] add tests for missing vector folds adds 3b24221 [docs] Update some obsolete information in BitCodeFormat docs. adds 7aaf99b [InstCombine] use m_APInt to allow sub with constant folds fo [...] adds 4594395 [X86] Take advantage of the lzcnt instruction on btver2 archi [...] adds 7c52e33 Move alignTo computation inside the if. adds 20bdbbe [Coverage] Support loading multiple binaries into a CoverageMapping adds a79c08f Revert "In preparation for removing getNameWithPrefix off of [...] adds a7945e6 [safestack] Use non-thread-local unsafe stack pointer for Contiki OS adds 4869102 [RDF] Switch RegisterRef to be a pair (Register, LaneMask) adds a9c6165 AMDGPU/SI: Don't allow unaligned scratch access adds 4475acb Add a pass to optimize patterns of vectorized interleaved mem [...] adds a22fe3e Workaround to eliminate check-llvm failures after r284255 adds e5a36c1 The real fix for post-r284255 failures adds 2e1f3bb TargetLowering: Add SimplifyDemandedBits() helper to TargetLo [...] adds 18cea77 AMDGPU/SI: Use new SimplifyDemandedBits helper for multi-use [...] adds 1167ade [DAG] avoid creating illegal node when transforming negated s [...] adds 59cf785 vim: add `comdat` keyword adds 775adeb vim: add `norecurse` attribute adds 3af6872 [libFuzzer] add -trace_cmp=1 (guiding mutations based on the [...] adds 58313a9 [libFuzzer] remove subdir fuzzer-test-suite as it is now supe [...] adds 8bb12b9 [PPC] Shorter sequence to load 64bit constant with same hi/lo words adds 65a7ee4 [PowerPC] add tests for PR30661 adds 6262732 [ARM] add tests for PR30660 adds 31164bc PowerPC: specify full triple to avoid different Darwin asm syntax. adds cb11533 hardware_physical_concurrency() should return 1 when LLVM is [...] adds 6a2dc09 Support: Add LLVM_NODISCARD with C++17's [[nodiscard]] semantics adds ee325b9 GlobalISel: rename legalizer components to match others. adds d6dc1be [NFC] Loop Versioning for LICM code clean up adds 0746b2b ADT: Use LLVM_NODISCARD instead of LLVM_ATTRIBUTE_UNUSED_RESU [...] adds 6b339ba AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer adds 75281e6 [libFuzzer] better algorithm for -minimize_crash adds ce61005 [libFuzzer] swap bytes in integers when handling CMP traces adds 6cceb12 [SimplifyCFG] Use the error checking provided by getPrevNode. adds b4458f9 [AVX-512] Rename VPBROADCASTI32X2 and VPBROADCASTF32X2 instru [...] adds 180beb4 [AVX-512] Add shuffle comments for vbroadcast instructions. adds fa081aa [X86] Regenerate known bits test adds edc73e8 Test commit. (NFC) adds f379cd3 [X86][SSE] Added some basic examples of knownbits failing for [...] adds 37bd2b7 [GVN/PRE] Hoist global values outside of loops. adds a7e2c08 [MachineMemOperand] Move synchronization scope and atomic ord [...] adds 078218d [ArmFastISel] Kill dead code. NFCI. adds 91d1efb [AVX-512] Move (v4i64 (X86SubVBroadcast (v2i64))) alternate p [...] adds bc745ca [AVX-512] Correct execution domain for VPERMT2PS and VPERMI2PS. adds 3a558dd [AVX-512] Fix the operand order for vpermi2var_qi intrinsics [...] adds 6ae3d4e PR30711: Fix incorrect profiling of 'long long' in FoldingSet [...] adds 097967f ADT: Use LLVM_NODISCARD instead of LLVM_ATTRIBUTE_UNUSED_RESU [...] adds fcec915 ADT: Prefer the LLVM_NODISCARD spelling adds 9febba8 Support: Prefer the LLVM_NODISCARD spelling adds e1d1c98 SCEV: Prefer the LLVM_NODISCARD spelling adds 215b6d5 MachineModuleInfo: Prefer the LLVM_NODISCARD spelling adds 0f82c94 Support: Return void from Scanner::scan_ns_uri_char, no one u [...] adds 13579ed unittests: Explicitly ignore some return values in crash tests adds 4da8984 [AVX-512] Add support for turning a 256-bit load that goes to [...] adds 11061fd [AVX-512] Add vpermi2var test cases to shuffle combining test [...] adds d56fafd [AVX-512] Add shuffle combining support for vpermi2var shuffl [...] adds 4e1daa7 ADT: Use LLVM_NODISCARD instead of LLVM_ATTRIBUTE_UNUSED_RESU [...] adds 043b10d [X86] Fix shuffle decoding assertions to print the right numb [...] adds 0ebe9c2 Support: Drop LLVM_ATTRIBUTE_UNUSED_RESULT adds b987363 [Object/ELF] - Do not crash on invalid section index. adds a43813b [Object/ELF] - Check that e_shnum is null when e_shoff is. adds 50d445a Revert r284371 "[Object/ELF] - Check that e_shnum is null whe [...] adds 2c7c85d Recommit r284371 "[Object/ELF] - Check that e_shnum is null w [...] adds fe42b01 [CodeGenPrepare] When moving a zext near to its associated lo [...] adds a00e39f [SCEV] Consider delinearization pattern with extension with i [...] adds 7b3797e [SimplifyCFG] Don't lower complex ConstantExprs to lookup tables adds e4c66df [docs] Reduce the number of places 'minimum requirements' is [...] adds 63b1eba [SDAG] Use ABI type alignment for constant pools when optimiz [...] adds 94b3ee4 [Support] remove_dots: Remove .. from absolute paths. adds 573d9cc [Support] remove_dots: Remove windows test. adds 1a38c9c [Object/ELF] - Check Header->e_shoff value earlier and do not crash. adds 6fb063a Rename interface for querying physical hardware concurrency adds e4e17f8 [x86] auto-generate checks adds c595aad [x86] add tests to show missing DAG folds for arithmetic-shift-right adds 6eae33c [DAG] optimize away an arithmetic-right-shift of a 0 or -1 value adds de86453 AMDGPU/SI: Fix LowerParameter() for i16 arguments adds 0d8c32f AMDGPU/SI: LowerParameter() should be computing align based o [...] adds 087ac0b GlobalISel: support wider range of load/store sizes in AArch64. adds 58121fb Return a StringRef instead of a Comdat*. adds f68eeb3 Handle relocations to thumb functions when dynamic linking CO [...] adds 6b54de2 Test commit. adds 303d287 [doc] use double `` to prevent html output of merging double dash adds 29dee96 Delete dead code. adds d0ef044 Ignore debug info when making optimization decisions in SimplifyCFG. adds ac38a64 [opt] Strip coverage if debug info is not present. adds 8a2a445 [DAG] make isConstOrConstSplat and isConstOrConstSplatFP more [...] adds 8cc4b69 [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRA adds 0a7eca8 [Support] Add support for "advanced" number formatting. adds 5a8c8ec remove FIXME comment (fixed with r284424); NFC adds d4bb10c Try to fix build after invalid pointer conversion. adds fdfb1c5 Revert formatting changes. adds 9296e5f Next set of additional error checks for invalid Mach-O files [...] adds 6461aab [ADT] Add SmallDenseSet. adds afb3618 [ADT] Add an initializer_list constructor to {Small,}DenseSet. adds fd7d73f [ADT] Move CachedHashString to its own header in ADT, and ren [...] adds 18560f1e [AMDGPU] Mark .note section SHF_ALLOC so lld creates a segmen [...] adds b3a1851 Resubmit "Add support for advanced number formatting." adds 88bc637 Rename HexStyle -> HexFormatStyle, and remove a constexpr. adds 0480c1b Fix differences in codegen between Linux and Windows toolchains adds d02b253 [AVX-512] Add support for decoding shuffle mask from constant [...] adds a97a64c [AVX-512] Fix DecodeVPERMV3Mask to handle cases where the con [...] adds 3c59fd4 Improve tablegen gen-subtarget diagnostics for missing machin [...] adds 63ae300 [X86] Fix DecodeVPERMVMask to handle cases where the constant [...] adds b3c2bab Object: Add a missing return in ObjectFile::createObjectFile adds 7873b5e [AVX-512] Add test case to check shuffle decoding for masked [...] adds dfab481 [XRay] Support for for tail calls for ARM no-Thumb adds e615ec6 [X86][SSE] Add lowering to cvttpd2dq/cvttps2dq for sitofp v2f [...] adds 7297515 [ARM] Assign cost of scaling for Cortex-R52 adds 1ba4231 [X86][SSE] Added extra (mul x, (1 << c)) -> x << c style vect [...] adds 8bb4ccc Revert "Resubmit "Add support for advanced number formatting."" adds a6faf3a [SCEV] More accurate calculation of max backedge count of som [...] adds f1fdd33 [llvm-readobj] - Teach readobj to print PT_OPENBSD_RANDOMIZE/ [...] adds 289f83a [mips][FastISel] Instantiate the MipsFastISel class only for [...] adds ede8543 Strip trailing whitespace (NFCI) adds d5f902e [x86][inline-asm][avx512] allow swapping of '{k<num>}' & '{z}' marks adds 05fe9f3 [mips] Macro expansion for ld, sd for O32 adds 58be60c DebugInfo: change alignment type from uint64_t to uint32_t to [...] adds 8e2c689 [mips] Fix sync instruction definition adds 4ec176a [mips][ias] Handle more complicated expressions for memory operands adds cad4756 [X86][AVX512] Add mask/maskz writemask support to constant po [...] adds da27c36 Disable fatal errors in the Verifier instantiated by bugpoint [...] adds 08bb504 [DAGCombiner] Add splatted vector support to (udiv x, (shl po [...] adds 5800d6e [Target] remove TargetRecip class; move reciprocal estimate i [...] adds 5618317 [docs] Increase minimum supported GCC version for building LL [...] adds acea2a6 [X86][SSE] Added vector ashr combine tests adds 9d4955c [SCEV] Extract out a helper function; NFC adds de57b39 [SCEV] Make CompareValueComplexity a little bit smarter adds 433154b [ADT] Remove CachedHash<T>. adds 640265d Next set of additional error checks for invalid Mach-O files [...] adds 7439986 [asan] Make -asan-experimental-poisoning the only behavior adds 1914a40 [asan] Combine check-prefixes in stack-poisoning test adds 9161c6d [asan] Rename test file as the poisoning is not "experimental" adds db740ff [libFuzzer] reshuffle the code for -exit_on_src_pos and -exit [...] adds ecd85eb [sancov] add __sanitizer_cov_trace_pc_guard to the supported [...] adds bbcb21d revert r284495: [Target] remove TargetRecip class adds 761c1ff [libFuzzer] detect leaks after every run when executing fixed [...] adds bef7c1f [InterleavedAccessPass] Remove global variable. adds 9bfbc7b [X86][SSE] Added vector lshr/shl combine tests adds 1b1c50f [esan] Remove global variable. adds 6e3c4da Reduce global namespace pollution. NFC. adds 57144cf [Hexagon] Handle block live-ins with lane masks in HexagonBlo [...] adds 1fd8e0a GlobalISel: support floating-point constants on AArch64. adds a30faf0 Remove unused typedef adds 4841e61 GlobalISel: translate memcpy intrinsics. adds 10519cd GlobalISel: select small binary operations on AArch64. adds 55352d9 GlobalISel: translate the @llvm.objectsize intrinsic. adds c6b8aca One more additional error check for invalid Mach-O files for [...] adds d9b0063 [AArch64] Avoid materializing 0.0 when generating FP SELECT adds be23217 [AArch64] Fix test triplet adds 977fc82 Use profile info to set function section prefix to group hot/ [...] adds ada39e9 [GVN] Remove dead code. NFC. adds a31af6a [GVN] Consistently use division instead of shift. NFCI. adds ed57153 Improve ARM lowering for "icmp <2 x i64> eq". adds 69a9e66 dwarfdump: -summarize-types: print a short summary (unqualifi [...] adds 8c8a976 Add target for test to fix regression introduced by r284533. adds d327a37 dwarfdump: Include the name in the unit description, even in [...] adds 9f38b99 dwarfdump: add space missing from the type unit header description adds 6e98f1c Using branch probability to guide critical edge splitting. adds fe89a6b Conditionally eliminate library calls where the result value [...] adds 0084250 revert r284541. adds f2a459b Using branch probability to guide critical edge splitting. adds 298a3d2 [asan] Append line number to variable name if line is availab [...] adds 6b9bef9 [asan] Simplify calculation of stack frame layout extraction [...] adds b3960e8 [libFuzzer] extend -print_coverage to also print uncovered li [...] adds 97cd3dc [asan] Replace std::to_string with llvm::to_string adds 625e9e7 Revert r284545 again as the regression in ppc still exists. T [...] adds 2e4381e Update the section.ll to fix non-x86 failure. adds cdb220a [AVX-512] Teach isel lowering that a subvector broadcast bein [...] adds 8218871 DenseSet: Appease msc18 to define derived constructors explicitly. adds 9a54c88 Checking FP function attribute values and adding more build a [...] adds c9cee26 Revert of r284571 because of failing tests. adds 8f03548 [DAGCombine] Generalize distributeTruncateThroughAnd to work [...] adds 1a8de66 Fix line endings adds 9f4aec5 [DAGCombiner] Just call isConstOrConstSplat directly. NFCI. adds ab4e036 [Thumb-1] Synthesize TBB/TBH instructions to make use of comp [...] adds 7b63453 [cmake] Declare LLVM_CMAKE_PATH for use in subprojects adds a91221a [SystemZ] Add optional argument to some vector string instructions adds bc50ab0 [SystemZ] Add missing vector instructions for the assembler adds a72922e llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \ [...] adds 556bf4b Reapply r284571 (with the new tests fixed). adds bca3cda Add Chrono.h - std::chrono support header adds 4a9c407 [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors i [...] adds 57ea748 Introduce ConstantRange.addWithNoSignedWrap adds dc8499f GlobalISel: support translating volatile loads and stores. adds ef2c5dd TMP adds 4648ae6 Sparc: fix test. adds 96f32a0 Revert r284604. A.K.A. "TMP" adds f02821b [DAGCombiner] Add general constant vector support to (shl (mu [...] adds 057fdd8 [DAGCombiner] Add general constant vector support to (shl (sr [...] adds cac7028 [RDF] Switch RefMap in liveness calculation to use lane masks adds 8b3f7e8 [pdb] Improve error messages when DIA is not found. adds 85745f9 [DAG] optimize negation of bool adds 0c48851 [WinEH] Allow catchpads to reuse the same catch object adds 9f2ab76 [DAGCombiner] Add general constant vector support to (shl (ad [...] adds b40b8e34 Revert "Add Chrono.h - std::chrono support header" adds 440f75c Merged nested ifs. NFCI. adds 740d871 [ThinLTO] Default backend threads to heavyweight_hardware_con [...] adds 735fbf8 [AMDGPU] Stop using MCRegisterClass::getSize() adds 4c50ebb [llvm-cov] Don't spawn a thread unless ThreadCount > 1 adds e66ad1c [ADT] Zip range adapter adds 8ddbe89 Add a macro for prefetching data. adds 0ca2107 [InstSimplify] move one and add more tests for potential nega [...] adds 6d823ec [AliasSetTracker] Return void for add() functions. NFC. adds 6ca75fa [IndVarSimplify] Use control-dependent range information to p [...] adds db638de [AliasSetTracker] Add support for memcpy and memmove. adds f461f21 [LV] Avoid emitting trivially dead instructions adds 86fff1f [IndVarSimplify] Teach calculatePostIncRange to take guards i [...] adds 3fd59c9 [GlobalMerge] Handle non-landingpad EH pads adds d673d6f Typo: nomed struct -> named struct adds b5046ba [BuildingAJIT] Make the chapter 5 server export symbols. adds bac9c43 [InstSimplify] fold negation of sign-bit adds 43fa064 [CMake] Make the runtimes directory work with bootstrap builds adds 599a7aa Remove the JIT EH/small code model tests for now. adds cc8ca50 AMDGPU : Add a function to enable and disable IEEEBit for SC [...] adds 2bd7506 Add computeHostNumPhysicalCores() implementation for Darwin adds 207b6ab [BuildingAJIT] Use the remote target triple to construct the [...] adds c887230 [PGO] Fix bogus warning for merging empty llvm profile file adds dee834c Update docs to reflect new minimum MSVC version requirement adds f4ca0f5 Revert "DenseSet: Appease msc18 to define derived constructor [...] adds fa327ae [PGO] Fix a use-after-move. NFC. adds 6224e33 Update Compiler.h to fail fast when building with MSVC 2013 adds 04e3307 Next set of additional error checks for invalid Mach-O files [...] adds 5b1c9f3 Remove LLVM_NOEXCEPT and replace it with noexcept adds 1c2f240 [WebAssembly] Update extending load test for new i1 behavior adds e69c459 DebugInfo: preparation to implement DW_AT_alignment adds 3a3c5c8 Use __func__ directly now that all supported compilers support it adds 8340aef DebugInfo: remove broken bitcode upgrade test adds bae0043 X86: Deduplicate some lowering code. NFCI. adds f43c9c6 X86: Allow expressions to appear as u8imm operands. adds 3e0be6f [Object/ELF] - Check index argument in getSymbol(). adds a007516 [SystemZ] Post-RA scheduler implementation adds f00b783 [Go bindings] Update for r284678 API changes. adds 67c3574 Fix MSVC bool -> uint64_t promotion warning adds 2c99feb Fix spelling mistake in comment. adds 89d6562 Wdocumentation fix adds b4c99dd [DAGCombiner] Add general constant vector support to (srl (sh [...] adds 911bb94 Reapply "Add Chrono.h - std::chrono support header" adds 06d5a16 Do a sweep over move ctors and remove those that are identica [...] adds 7b259eb [CostModel][X86] Added tests for sdiv/udiv costs for scalar a [...] adds f7463aa [mips][mcjit] Add the majority of N32 support. adds 2913220 [GVN] Use defaulted members. No functional change. adds cb58e1e Retire llvm::alignOf in favor of C++11 alignof. adds cafdc34 [Support] Remove llvm::alignOf now that all uses are gone. adds fd82ba5 [Support] Put back the MSVC hack for AlignedCharArray. adds 446cd5e [AMDGPU] add fcopysign(f64, f32) pattern adds 99edc4f [CostModel][X86] Fixed AVX1/AVX512 sdiv/udiv general costs fo [...] adds c32b596 Put the move ctor for PassManager back for now, it breaks som [...] adds 928f047 [Target] remove TargetRecip class; 2nd try adds ca13ae1 [CostModel][X86] Added tests for sdiv/udiv costs for uniform [...] adds f2b19f9 Fix *_EXTEND_VECTOR_INREG legalization adds e1ac64b [CostModel][X86] Fixed AVX1/AVX512 sdiv/udiv uniformconst cos [...] adds 0872bb2 Using branch probability to guide critical edge splitting. adds e0e811c [AMDGPU] Emit constant address space data in .rodata section [...] adds 37962ab [AMDGPU] Make note record name a static const member of targe [...] adds a459ab9 [CodeView] Refactor serialization to use StreamInterface. adds 838c3a9 Fix case of file include path. adds d6842a6 Another additional error check for invalid Mach-O files for t [...] adds 6d6a5e6 [MSSA] Avoid unnecessary use walks when calling getClobbering [...] adds fe04032 [X86] Enable interleaved memory access by default adds a5f79d9 Fix PREL31 relocation on ARM adds 3c09f0b [SCEV] Add a threshold to restrict number of mul operands to [...] adds a45d706 Fix cross-endianness RuntimeDyld relocation for ARM adds b8c3103 Revert "[GVN/PRE] Hoist global values outside of loops." adds 7413606 [AVX-512] Add tests to show opportunities for commuting vperm [...] adds c2cab9b [Support] Fix AlignOf test on i386-linux. adds 02d2642 Fix WebAssembly test after r284757. adds 46ab1d2 [AArch64] Corrected spill size for DDD register class. NFCI adds 4b5784c [X86][AVX] Add 32-bit target tests for vector lzcnt/tzcnt to [...] adds 9e0c61c [LoopUnroll] Keep the loop test only on the first iteration o [...] adds 01109e8 [X86][AVX512] Add mask/maskz writemask support to subvector b [...] adds aaafc1d Wdocumentation fix adds 06bac82 [X86][AVX2] Begun generalizing lowering to VPERMD/VPERMPS in [...] adds f8de69b [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds adds 3398735 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand [...] adds 73cda08 fix variable names; NFCI adds d193fb5 [LVI] Fix a bug with a guard being the very first instruction [...] adds b03d0d9 Test commit adds 51f1efc [X86][SSE] Regenerated chained pmovsx store tests and added i [...] adds 466e9f4 [MachineMemOperand][AtomicSDNode] Remove getSuccessOrdering() adds ed8dcc8 [X86] Use DAG::getBuildVector helper wrapper where possible. NFCI. adds c2abd3e [X86][SSE] Regenerated sext/zext constant folding tests and a [...] adds 57a3dc5 Fix -Wunused-variable warning in libFuzzer adds 6706bad Set the vectorizer MaxInterleaveFactor for Exynos. adds dc83305 [WebAssembly] Fix for 0xc call_indirect changes adds b77f18e [Hexagon] Handle spills of partially defined double vector registers adds 7ff284e [x86] add tests for potential negation folds adds be29b10 [DAG] fold negation of sign-bit adds bbe3a73 For llvm-objdump for Mach-O files add printing of the ARM_THR [...] adds 79f85df [StripGCRelocates] New pass to remove gc.relocates added by RS4GC adds b96d437 [RDF] Use RegisterId typedef more consistently, NFC adds fcb8cd9 [X86][AVX512] Added support for combining target shuffles to [...] adds 714d9ba [X86][AVX512BWVL] Added support for combining target v16i16 s [...] adds e4fce5a [pdb] added support for dumping globals stream adds b859d6d [X86][AVX512BWVL] Added support for lowering v16i16 shuffles [...] adds 7d77c5c X86: Improve BT instruction selection for 64-bit values. adds 7e2bd34 Analysis: Move llvm::getConstantRangeFromMetadata to IR library. adds aa9584a [libFuzzer] mention one more trophie adds a9abde4 Fix a bug in the code of llvm-cxxdump in dumpArchive() when i [...] adds f0a5715 [SCEV] Memoize visitMulExpr results in SCEVRewriteVisitor. adds dea54d6 [IR] Add DenseMapInfo<CallSite>. adds 228ec7d [ADT] Add CachedHashString. adds 2a98ad5 [ADT] Compare strings' hashes first before comparing their values. adds 8751486 [DAG] enhance computeKnownBits to handle SHL with vector spla [...] adds a0d7657 AMDGPU/SI: Fix crash caused by r284267 adds 600523a [ADT] Get rid of use of LLVM_NOEXCEPT in CachedHashString.h. adds ee11f48 fixed typo in InstrProf.h; NFC adds 13656b4 Support: Annotate Error and Expected<> with LLVM_NODISCARD adds 2c937a1 Switch SmallSetVector to use DenseSet when it overflows its i [...] adds 25a30cd [AMDGPU] Perform uchar to float combine for ISD::SINT_TO_FP adds 902d11d [ADT] Don't rely on string literals not being convertible to [...] adds 1b0519f [x86] add test for missing vector SRA combine via computeKnownBits adds f64117c Fix map insertion that is elided in release build. adds 7430a26 [libFuzzer] add a test for asan's strict_string_checks=1 adds 76857ef [libFuzzer] typo in a test adds 7c81c77 [CtorUtils] Modernize. No functional changes intended. adds e513820 [BasicAA] Fix - missed alias in GEP expressions adds 9b71256 [libFuzzer] mutation: insert the size of the input in bytes a [...] adds 581b279 Now that VS2013 is gone, make a memoryssa structure an anonym [...] adds 231a23a [X86][SSE] Use getConstVector helper for VPERMV mask generati [...] adds c042fa8 [X86] Remove 128-bit lane handling from the main loop of matc [...] adds 799d213 [X86] Remove unnecessary AVX2 check that was already covered [...] adds bffa737 [X86] Add support for lowering v4i64 and v8i64 shuffles direc [...] adds 061426e [X86] Add support for printing shuffle comments for VALIGN in [...] adds 6fa81ba [X86] Apply the Update LLC Test Checks tool on the mmx-bitcast test adds 13608f3 [ARM] Fix crash in ConstantIslands adds 46ea061 [lit] Add more testing instructions to README adds d83c830 [X86][AVX512] Added support for combining target shuffles to [...] adds ae8e401 [X86][AVX512VL] Added support for combining target 256-bit sh [...] adds acce8ee [AVR] Add the machine code disassembler adds a6fc694 Use APInt::isAllOnesValue instead of popcnt. NFCI. adds 743f471 [CostModel][X86] Added tests for current integer trunc costs adds e8a0965 [X86][SSE] Add SSE41/AVX1 costs for vector shifts. adds 27ae3e8 [CostModel][X86] Added tests for current integer signed/unsig [...] adds 6feedc5 Remove LLVM_CONSTEXPR. adds 09116d9 Use SDValue::getConstantOperandVal() helper. NFCI. adds 0800ef1 [DAG] enhance computeKnownBits to handle SRL/SRA with vector [...] adds bc9b41f [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade [...] adds df936e3 [llvm-opt-report] Fix unroll-count reporting adds 7577cb9 [mips] synci microMIPS instruction definition. adds 2864c2a Remove TimeValue usage from llvm/Support adds 39e6b39 Fix windows builds by swapping windows.h and wincrypt.h ordering. adds cfd5008 [JumpThreading] Unfold selects that depend on the same condition adds 1c01a24 [RDF] Add default move constructors/assignment operators adds f215294 AArch64 ILP32 relocations for assembly and ELF adds 6df9562 [Object] Replace TimeValue with std::chrono adds a1f02c4 Remove unused #includes of TimeValue.h. NFC. adds f62fc7a [Chrono] Fix !HAVE_FUTIMENS build adds ebd807a [MC] Fix Various End Of Line Comment checkings adds b265370 Revert 284971. adds e07033a AMDGPU: Fix Two Address problems with v_movreld adds 8376827 [x86] regenerate checks adds 5ba8f14 [PPC] Better codegen for AND, ANY_EXT, SRL sequence adds 335a8e8 [EarlyCSE] Optimize MemoryPhis and reduce memory clobber quer [...] adds a3dec00 [ADT] static_assert that SmallDenseMap is instantiated with a [...] adds 6334b62 [AArch64] Optionally use the Newton series for reciprocal estimation adds fcdb958 Check the number of Args in LibCallsShrinkWrap. adds 9ff4a73 Removed FIXME from include ordering comment adds 05c1074 Revert r284580+r284917. ("Synthesize TBB/TBH instructions") adds e8d4830 ReleaseNotes: mention new compiler requirements adds 300e976 [PPC] Generate positive FP zero using xor insn instead of loa [...] adds b754221 Revert r284972 and remove other defaulted copy/move constructors/= adds 584f664 Clarify that MSVC is not the issue here anymore. adds d848744 add-discriminators: Fix handling of lexical scopes. adds 7fbfd59 CodeGen: Do not add a global's address space to the folding s [...] adds b831a5d [llvm] Remove redundant --check-prefix=CHECK from tests adds ddbec7c [x86] add tests for {-1,0,1} select of constants adds 80e2a2f Target: Change various section classifiers in TargetLoweringO [...] adds 94c3eb8 Merge two if conditions into one. NFCI. adds 1871c0f [WebAssembly] Add an option to make get_local/set_local explicit. adds 8dd4db3 [WebAssembly] Update opcode values according to recent spec changes. adds 777b045 [WebAssembly] Define the `end` opcode value. adds 459c4c4 [WebAssembly] Fix a broken URL. adds 0ca81d1 [pbqp] Delete some dead code, NFC. adds ea1ab92 [pbqp] unique_ptr-ify (Vector|Matrix)::Data, NFC. adds e83b8be Use SDValue::getConstantOperandVal() helper. NFCI. adds aa45092 nother additional error check for an invalid Mach-O file when [...] adds 39e13bb Use MachineInstr::mop_iterator instead of MIOperands; NFC adds 5e86c2a cmake: Make /usr/share/cmake installable with LLVM_DISTRIBUTI [...] adds 8d98044 [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to [...] adds 10310d2 Fix regression from my recent GlobalsAA fix. adds 31637d9 cmake: Rename installhdrs to install-llvm-headers and fix the [...] adds eef5da2 [InstCombine] regenerate some checks adds cc92828 CodeGen/Passes: Pass MachineFunction as functor arg; NFC adds 01b8943 [WebAssembly] Implement more WebAssembly binary encoding. adds 5b5c5e7 [llvm-cov] Do not print out the filename of the object file adds 12e2f72 [WebAssembly] Reorder load/store operands to match binary encoding. adds 5aa57a1 [InstCombine] auto-generate checks adds 8f808de [InstCombine] auto-generate checks adds 5989799 GlobalDCE: Deduplicate code. NFCI. adds d2c91bf [libFuzzer] simplify the code for use_cmp, also use the posit [...] adds 6ff6048 IR: Deduplicate getParent() functions on derived classes of G [...] adds 4e3c65d MachineInstrBundle: Pass iterators to getBundle(Start|End); NFC adds 2c3f1a7 GlobalDCE: Restore a statement accidentally removed in r285048. adds 53bf46f [AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG a [...] adds 797783e Fix an unused warning in WebAssemblyInstPrinter with NDEBUG. adds 050bf6c Make the LTO comdat api more symbol table friendly. adds 3ed32c9 [DAGCombine] Preserve shuffles when one of the vector operand [...] adds 4fd1299 fix warning adds d50540f [InstCombine] add tests for bitcast interference with min/max [...] adds 618621d [InstCombine] fix checks for previous commit (r285069) adds 16ce778 [X86][SSE] Add support for (V)PMOVSX* constant folding adds ce0f082 [InstCombine] add test and code comment to show potentially m [...] adds 2677f9f [SystemZ] Do not use LOC(G) for volatile loads adds 614c32b fix formatting; NFC adds 9511e49 [EarlyCSE] Make MemorySSA memory dependency check more aggressive. adds 515a723 Replace TimeValue by TimePoint in LegacyPassManager. NFC. adds da33b85 [IndVarSimplify][Dwarf] When widening the IV increment, corre [...] adds f4b7593 Move discriminator assignment to where it is used. (NFC) adds d29493d [WebAssembly] Add immediate fields to call_indirect and memor [...] adds 3089ab8 Try removing an MSVC2010 workaround. adds d4998ec [llvm-cov] Add support for loading coverage from multiple objects adds c31e4b5 Revert 285087. adds a69463c [unittests] Remove an MSVC 2013 workaround, NFCI. adds 59b2213 [unittests] STLExtrasTest: Remove an MSVC 2013 workaround, NFCI. adds 0e4bd93 Fix 80-char violations. NFC. adds e05a7ff Remove debug location from common tail when tail-merging adds 5bd98bf Add -strip-nonlinetable-debuginfo capability adds 5a31336 [InstCombine] add tests for missing icmp + shl nuw fold adds da24afa [LV] Sink scalar operands of predicated instructions adds 301f71e Switch lowering: improve partitioning of jump tables adds 1fc13ff [llvm-cov] Don't use colored output until we know it's supported adds 9d6f123 Add option to specify minimum number of entries for jump tables adds 6141ab4 [APFloat] Make APFloat an interface class to the internal IEE [...] adds 41a1a9b [AArch64] Adjust the cost model for Exynos M1. adds 20cfefb [InstCombine] Ensure that truncated int types are legal. adds 0895ad4 [libFuzzer] when mutating based on CMP traces also try adding [...] adds 59a9113 revert: "Remove debug location from common tail when tail-merging" adds 09845fd [X86][SSE] Added vector sdiv combine tests adds 413fdf3 [InstCombine] Resubmit the combine of A->B->A BitCast and fix [...] adds baad275 [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectors adds b4f0b6e [X86][SSE] Added vector urem combine tests adds 4864d89 [X86][SSE] Added vector srem combine tests adds 72b26e6 [docs] Add more Error documentation to the Programmer's Manual. adds b03ba30 [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectors adds 908c768 [X86][SSE] Regenerated known-bits test with srem->urem fix adds 0eba98a [PGO] Fix select instruction annotation adds d9bc309 [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add [...] adds 157b7f5 [codeview] support emitting indirect virtual base class information adds ed5107d [Sparc] Don't overlap variable-sized allocas with other stack [...] adds c468b9c [docs] Fix a couple of typos in the new Error docs. adds 582aee6 [docs] Fix a missing code-block in the new Error docs. adds 98711e2 [libFuzzer] add StandaloneFuzzTargetMain.c and a test for it adds 94e5282 [docs] Fix a few more Error docs formatting issues. adds 41965a8 [docs] Fix yet another Error docs formatting issue... adds 781a2b4 [docs] Use consistent style for "do more stuff" in Error docs [...] adds f8406aa [docs] Avoid repetition of 'considerable' in Error docs. adds cbe5db8 [libFuzzer] simplify the code in TracePC::HandleTrace adds 43122e2 Utility functions for appending to llvm.used/llvm.compiler.used. adds 9c90455 [libFuzzer] simplify the code to print new PCs adds 7f59a4b [libFuzzer] simplify the code in TracePC::HandleTrace a bit more adds 7d084db Use printf instead of "echo -e" or "echo -n". adds 433938a [XRay] Implement `llvm-xray extract`, start of the llvm-xray tool adds e951285 Revert "[XRay] Implement `llvm-xray extract`, start of the ll [...] adds 9513453 [libFuzzer] refresh docs adds 446d7cc Cloning: Also clone global variable attached metadata. adds 5a35548 [XRay] Implement `llvm-xray extract`, start of the llvm-xray tool adds a25c1fd [XRay] Add llvm-xray as a dependency to test/CMakeLists.txt adds 07792fb [XRay] Remove extra `;` to make -wpedantic happy adds dbc97f3 [XRay] Move specialisations into correct namespace adds 1af0e79 [XRay] Remove unnecessary include of <unistd.h> adds 83f97dc [XRay] Remove unnecessary include of <unistd.h> adds 9fc96e5 [AVX-512] Add scalar vfmsub/vfnmsub mask3 intrinsics adds 2a38659 [XRay] Be case-insensitive for error strings adds 6bee13e DebugInfo: add bitcode upgrade test for alignment adds de2f92b DebugInfo: support for DWARFv5 DW_AT_alignment attribute adds 1df4f64 Revert r285181 "DebugInfo: support for DWARFv5 DW_AT_alignmen [...] adds 42dcce5 [IndVarSimplify][DebugLoc] When widening the exit loop condit [...] adds 0ab9364 DebugInfo: support for DWARFv5 DW_AT_alignment attribute adds e131755 [AliasSetTracker] Make AST smarter about intrinsics that don' [...] adds cbb0ce9 [InstCombine] auto-generate better checks; NFC adds 1d3b444 [InstCombine] consolidate zext tests and auto-generate checks; NFC adds a1f05a2 [X86] AVX512 fallback for floating-point scalar selects adds e2f7559 AMDGPU/SI: Remove unnecessary run lines from test adds 1a633d1 AMDGPU/SI: Don't emit multi-dword flat memory ops when they m [...] adds 84b175c LegalizeDAG: Support promoting [US]DIV and [US]REM operations adds d0147e5 [InstCombine] clean up commonCastTransforms; NFC adds f205f3b Fix nondeterministic output in local stack slot alloc pass adds 44de456 AMDGPU: Fix counting si_mask_branch as 4 bytes adds f63894b Reapply "AMDGPU: Don't use offen if it is 0" adds 98ab42a Introduce updateDiscriminator interface to DILocation to make [...] adds c93e472 AMDGPU: Refactor processor definition to use ISA version features adds 72c8379 Reapply: "Remove debug location from common tail when tail-merging" adds a72a0d6 [MC] Fix comma typo in .loc parsing adds 9eeea0a [WebAssembly] Update the README.txt. adds 1d0dc0f [AArch64] Avoid materializing constant 1 when generating cneg [...] adds 39d3967 Fix test from r285217. adds 3c0deb1 [libFuzzer] simplify TracePC::HandleTrace even further. Also, [...] adds 4e7356c [PowerPC] Implement vec_insert_exp builtins - llvm portion adds 5a50eb6 Revert "[AliasSetTracker] Make AST smarter about intrinsics t [...] adds cf6e9a8 Simplify `x >=u x >> y` and `x >=u x udiv y` adds 73235dc Do not assume that FP vector operands are never legalized by [...] adds 1ff4f02 ARM: don't rely on push/pop reglists being in order when fold [...] adds 9434af1 [PPC] Remove testcase from incorrect directory adds 9b4e828 [lit] Work around Windows MSys command line tokenization bug adds 7614f6d DebugInfo: fix incorrect alignment type (NFC) adds 04c77ee [AArch64] Create feature set for Samsung Exynos-M2 adds a8dbdb7 [utils] Add an '--only-merge' option to the code coverage pre [...] adds 1182ed1 [utils] Use print_function in the code coverage prep script, NFC. adds 47e18f4 [utils] Add a '--unified-report' option to the code coverage [...] adds 403d906 llvm-objdump: Make some error messages more consistent adds 5e89a7d [APFloat] Fix APFloat::getExactInverse when the input is null [...] adds cf6a8a6 [IR] Retire unused getGEPReturnType overload. NFCI. adds 0628937 [libFuzzer] speculatively trying to fix the Mac build adds 9df8914 [libFuzzer] revert 285259 -- hit commit too soon adds eb87ccc xray-extract.cc: Quick fix for mingw, to avoid errc::protocol_error. adds 56a90b6 [libFuzzer] speculatively trying to fix the Mac build; second [...] adds e9fdaa1 [PowerPC] - No SExt/ZExt needed for count trailing zeros adds e0d500a [AVR] Add the machine code emitter adds 8b74dfc [AVR] Add AVRISelDAGToDAG.cpp adds 4e78b45 [AVR] Compile the disassembler adds ce0a523 AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged [...] adds c63ef8d [AVR] Generate all of the TableGen files we need adds a6ec572 [ARM] Predicate UMAAL selection on hasDSP. adds 1341f74 [ARM] Add newline char to test. adds 2bbde38 [Object/ELF] - Do not crash if string table sh_size is equal [...] adds 464f0d7 [Object/ELF] - Do not allow overflow when checking section si [...] adds 5e7dda5 [Object/ELF] - Fixed behavior when SectionHeaderTable->sh_siz [...] adds d6d83fe [SLP] Fix for PR30626: Compiler crash inside SLP Vectorizer. adds 2eb8a6d Revert r285285 "[Object/ELF] - Fixed behavior when SectionHea [...] adds d44b990 [InstCombine] auto-generate better checks; NFC adds 5579104 [DAGCombiner] Add vector demanded elements support to compute [...] adds 444277c [Hexagon] Do not expand ISD::SELECT for HVX vectors adds 498c167 Fix memory issue in AttrBuilder::removeAttribute uses. adds df97b25 [InstCombine] add tests for missing folds of vector abs/nabs/min/max adds bf85e05 Remove duplicated default move ctors/move assign. No function [...] adds f662ae7 [ValueTracking] fix matchSelectPattern to allow vector splat [...] adds 0de3e81 [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64 adds 1de0324 [mips] Do not allow -opt-bisect-limit to skip the PIC call op [...] adds 146c52f Add Loop Sink pass to reverse the LICM based of basic block f [...] adds 07e9e1a Switch all DWARF variables for tags, attributes and forms ove [...] adds b5143b0 ARM: ensure that the Windows DBZ check is in range adds 1020d5b [X86][AVX512DQ] Move v2i64 and v4i64 MUL lowering to tablegen adds 74906fa [InstCombine] handle simple vector integer constants in IsFre [...] adds 6c0e6ef [X86][AVX512] Fix MUL v8i64 costs on non-AVX512DQ targets adds 86f0394 [LoopUnroll] Check partial unrolling is enabled before initia [...] adds 34a73b3 [PPC] Adding the removed testcase again adds 245c383 [InstCombine] auto-generate checks for min/max tests adds f8e32dd [libFuzzer] remove large examples from the libFuzzer docs and [...] adds 79758d4 AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer adds 23d90fc [libFuzzer] docs: separate section for fuzz target adds 964532c [InstCombine] add vector tests for foldSPFofSPF to show missi [...] adds 60923f3 Another additional error check for invalid Mach-O files for t [...] adds cbc0087 [libFuzzer] docs: update the examples adds 428b70f [InstCombine] fix foldSPFofSPF() to handle vector splats adds bf97793 CodeGen: Handle missed case of block removal during BlockPlacement. adds 0f84bab BitcodeReader: Require clients to read the block info block a [...] adds 4cdbd20 [APFloat] Add DoubleAPFloat mode to APFloat. NFC. adds 302a19a [libFuzzer] enable use_cmp by default adds 441030d Revert "[APFloat] Add DoubleAPFloat mode to APFloat. NFC." adds e2196c5 Update .debug_line section version information to match DWARF [...] adds f95be0d Reapply r285351 "[APFloat] Add DoubleAPFloat mode to APFloat. [...] adds 5480a24 AMDGPU/SI: Handle hazard with > 8 byte VMEM stores adds d950fb2 [Coverage] Darwin: Move __llvm_covmap from __DATA to __LLVM_COV adds 80b0252 Reverting back r285355: "Update .debug_line section version i [...] adds 0b23373 AMDGPU/SI: Fix unused variable warning on non-debug builds adds d637592 [IR] Reintroduce getGEPReturnType(), it will be used in a lat [...] adds 3058da2 Remove accidentally commited test. adds 8434132 AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,w [...] adds a911f5f AMDGPU/SI: Handle hazard with s_rfe_b64 adds e3433e6 [ConstantFold] Get the correct vector type when folding a get [...] adds bf13e73 [IR] Clang-format my previous commit. NFCI. adds 89aab30 [ThinLTO] Rename HasSection to NoRename (NFC) adds d39de45 [ThinLTO] Create AliasSummary when building index adds 5ecb91b [Reassociate] Removing instructions mutates the IR. adds 67d80b9 Revert "[DAGCombiner] Add vector demanded elements support to [...] adds 22eba5a [LCSSA] Perform LCSSA verification only for the current loop nest. adds f59b437 [SelectionDAG] Increment computeKnownBits recursion depth for [...] adds 7117050 [SelectionDAG] Tidyup UDIV computeKnownBits implementation adds 734d68c [SelectionDAG] computeKnownBits - early-out if any BUILD_VECT [...] adds 889ff7b [LV] Correct misleading comments in test (NFC) adds 749a022 [cmake] Temporarily revert enforcement of minimum GCC version [...] adds d0b25b0 [Loads] Fix crash in is isDereferenceableAndAlignedPointer() adds fe1e3ec [Hexagon] Maintain kill flags through splitting in expand-condsets adds 95d4f2c [lli] Pass command line arguments in to the orc-lazy JIT. adds db3dd81 [InstCombine] move/add tests for smin/smax folds adds a3dd1fe [libFuzzer] a bit more docs adds 05af2b2 More swift calling convention tests adds 9fd3a76 Import/update constants from the DWARF 5 public review draft [...] adds 23ea6d3 TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down. adds 15cdf2c MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC adds f2e1fce Move the DWARF attribute constants into Dwarf.def and delete [...] adds 60699bf [Error] Unify +Asserts/-Asserts behavior for checked flags in [...] adds 3dc20a0 [x86] add tests for missed umin/umax adds 9943293 Make swift calling convention test specific to armv7 adds d7cf4df [MemorySSA] Add const to getClobberingMemoryAccess. adds 4c68e05 [ThinLTO] Use flags from summary when writing variable summary (NFC) adds 0b61b12 Implement vector count leading/trailing bytes with zero lsb a [...] adds 2d7bc6b AMDGPU: Fix using incorrect private resource with no allocation adds 593670b SpeculativeExecution: Allow speculating more inst types adds 1adbd7e Handle non-~0 lane masks on live-in registers in LivePhysRegs adds b3c6b68 [APFloat] Use std::move() in move assignment operator adds 7dcc2cb Remove redundant prefixes from constants and unbreak the LLDB bots. adds 6cabc8f AMDGPU: Diagnose using too many SGPRs adds a654819 Fix a copy&paste error in the macro definition for HANDLE_DW_ [...] adds 0e18bbf AMDGPU: Change check prefix in test adds 10df7e9 cmake: Enable the lto cache when building with -flto=thin on darwin adds 9488f1f Don't claim the udiv created in BypassSlowDivision is exact. adds f644e7b Don't leave unused divs/rems sitting around in BypassSlowDivision. adds 30c499d [NVPTX] Compute 'rem' using the result of 'div', if possible. adds be4e1c4 AMDGPU: Rename glc operand type adds d6028cd AMDGPU: Add definitions for scalar store instructions adds 27d02ea Add missing lit.local.cfg to llvm/test/Transforms/CodeGenPrep [...] adds 51fb510 [libFuzzer] mention one more trophie adds 342cdd8 SDAG: Make sure we use an allocatable reg class when we creat [...] adds 88ccb3e [APFloat] Fix memory bugs revealed by MSan adds b292fb2 Refactor all DW_FORM_* constants into Dwarf.def adds 73525b9 Remove whitespace adds 3807607 Refactor DW_CFA_* into Dwarf.def adds 832e271 Refactor DW_APPLE_PROPERTY_* into Dwarf.def adds 64660bf Refactor DW_LNS_* into Dwarf.def adds 2149107 Refactor DW_LNE_* into Dwarf.def adds 0f0ebbd AMDGPU: Fix instruction flags for s_endpgm adds b15bbca AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Fla [...] adds c576394 [DAGCombiner] Fix a crash visiting `AND` nodes. adds d5b5d46 Do not print out Flags field twice. adds b53c2b0 Resubmit "Add support for advanced number formatting." adds b7f36bc [APFloat] Remove the redundent function body of uninitialized [...] adds 33eabd9 Define calculateDbgStreamSize for consistency. adds d75f7ec AArch64DeadRegisterDefinitionsPass: Cleanup; NFC adds ac5efca AMDGPU: Use 1/2pi inline imm on VI adds 2fd6330 Fixed FMA + FNEG combine. Masked form of FMA should be omitte [...] adds 6722cc3 [DAGCombiner] (REAPPLIED) Add vector demanded elements suppor [...] adds 9978e17 [InstCombine] re-use bitcasted compare operands in selects (PR28001) adds c69fe17 [x86] add tests for smin/smax matchSelPattern (D26091) adds 14ebdf2 [ValueTracking] recognize more variants of smin/smax adds c4589d7 [X86] Use intrinsics table for VPMULHRSW intrincis so that th [...] adds 2203707 IR: Remove a no longer needed assert. adds 8c54a79 [ThinLTO] Use NoPromote flag in summary during promotion adds 8108a04 [ThinLTO] Rename doPromoteLocalToGlobal to shouldPromoteLocal [...] adds 37111b2 NativeFormatting.cpp: Fix build for mingw. Where would writeP [...] adds 0a87051 [X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use mem [...] adds 39970a7 [ThinLTO] Correctly resolve linkonce when importing aliasee adds 9fd0638 [ThinLTO] Use per-summary flag to prevent exporting locals us [...] adds 56c6464 [Polly] Remove the unused POLLY_LINK_LIBS for linking pol [...] adds 648888d [X86] Use intrinsics table for PMADDUBSW and PMADDWD so that [...] adds b10d927 [LoopVectorize] Make interleaved-accesses analysis less conse [...] adds 6d3c9bd Revert r285517 due to build failures. adds 6c05e2a [x86] add tests for basic logic op folds adds 73a78bf [DAG] x & x --> x adds d43c4b8 [DAG] x | x --> x adds abf46ba Clean up test a little bit; NFC adds 641d727 [SCEV] Use auto for consistency with an upcoming change; NFC adds 39fd0bb [SCEV] In CompareValueComplexity, order global values by their name adds 399f721 [SCEV] Reduce boilerplate in unit tests adds 5c51de1 [SCEV] Try to order n-ary expressions in CompareValueComplexity adds 472e478 Make a test case more rigorous; NFC adds ddcef0e [AVX-512] Add missing patterns for selecting masked vector ex [...] adds 951469b Add getOffset to ELFSectionRef adds ef99bbd Delete .s file that did not test anything, and check in test [...] adds 8b9bc3d Add triple to test so it does not fail on windows. adds 7af02fc Improved cost model for FDIV and FSQRT, by Andrew Tischenko adds eeb178c [SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td. adds 3aa3118 Second attempt at r285517. adds b12a0a5 [SystemZ] Fix encoding of MVCK and .insn ss adds 19e305e [SystemZ] Correctly diagnose missing features in AsmParser adds 0d70794 [SystemZ] Guard LEFR/LFER with FeatureVector adds c1487e1 [SystemZ] Rework processor feature definitions and add -mcpu= [...] adds 8043131 Recommit r285285 - [Object/ELF] - Fixed behavior when Section [...] adds abc5ce4 [Hexagon] Don't expand mux instructions with both sources identical adds 86d9395 [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM in [...] adds bff2583 [x86][inline-asm][AVX512][llvm][PART-2] Introducing "k" and " [...] adds d3f04d3 [lli] Don't strip away const qualifier. Unbreak the gcc6 build. adds 1a30f4b Modify DWARFFormValue to remember the DWARFUnit that it was d [...] adds 8d99748 SymbolRef::Type is not a bitfield and must be compared directly adds 09c7eaa Fix an unconditional break in checkMachOAndArchFlags adds c6acb51 SingleLinkedListIterator::operator++(int) shouldn't return a [...] adds 9b10881 Define DbiStreamBuilder::addSectionMap. adds fa8311d GlobalISel: translate stack protector intrinsics adds d9f01d8 GlobalISel: allow truncating pointer casts on AArch64. adds 30e34b0 [MC] Make llvm-mc fail cleanly on invalid output asm variant. adds 588bf7b [asan] Move instrumented null-terminated strings to a special [...] adds 96c7b39 Fix per-processor model scheduler definition completeness check adds b339549 DebugInfo: make DW_TAG_atomic_type valid adds 7e057dc [PPC] add absolute difference altivec instructions and matchi [...] adds e9885e0 More additional error checks for invalid Mach-O files when th [...] adds d80a70a Remove llc -jump-table-type option, it hasn't been functional [...] adds 5956db4 docs: trying to fix the docs bot by removing non-ASCII charac [...] adds 8ddde8c [NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass. adds 485ef16 [ThinLTO] Disable importing and other cross-module optis at -O0 adds f185e91 CodeGen: further loosen -O0 CG for WoA division adds 008e98f Fix a typo. adds 3124bb2 [Hexagon] Garbage collect dead code. adds b983cb0 [DAG] disable nsw/nuw for add/sub/mul when simplifying based [...] adds 783d67d AMDGPU: Whitespace fixes adds caef643 Bitcode: Simplify BitstreamWriter::EnterBlockInfoBlock() interface. adds 2eb16bc [TBAA] Rename accessors to be more idiomatic; NFC adds 710d3bd [TBAA] Use wrapper objects instead of raw getOperand s; NFC adds aa686dd [docs] remove more non-ascii stuff in the hopes to fix the bot adds 038b68a Allow resolving response file names relative to including file adds 3cf18de Attempt to pacify buildbot adds 790687f [PowerPC] Implement vector shift builtins - llvm portion adds a66e032 [AMDGPU] Expand vector mulhu/mulhs adds 9b12d6a [Thumb-1] Synthesize TBB/TBH instructions to make use of comp [...] adds 447ffef [Sparc][LEON] Test for FixFDIVSQRT erratum fix. adds 5d99995 [InstCombine] auto-generate better checks adds cf8d483 [InstCombine] Folding of shifts by the sum of positive values adds caa8396 [InstCombine] fix tests for adjusted min/max adds d6c57ac This is a 1 character fix for an ARM build attribute test (r2 [...] adds 2b70009 AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64 adds 5a675ff [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h adds eee7c89 [InstCombine] move/fix tests for adjusted min/max adds 404c9d5 [RISCV] Recognise riscv32 and riscv64 in triple parsing code adds 49b5e6b [RISCV] Add RISC-V ELF defines adds 8687a64 [RISCV] Add missing RISCV.def adds 5216ee3 AMDGPU: Fix buildbots broken by r285704 adds 0ba26af [RISCV] Add stub backend adds ee817c2 [InstCombine] add vector tests for ext+adjust min/max adds 3a876bd [CMake] Fix rpath construction for out-of-tree builds adds f89a6d6 [InstCombine] add helper function for adjustMinMax(); NFCI adds a2791e7 [AMDGPU] Check if type transforms to i16 (VI+) when getting A [...] adds e7b36ad Test Commit, removed extraneous newline adds cb06b58 [InstCombine] clean up adjustMinMax(); NFCI adds 287bdc4 BranchRelaxation: Expand unconditional branches first adds 92c5c9e [Hexagon] Rename operand/predicate names for unshifted integers adds e7291ef [InstCombine] Fold nuw left-shifts in `ugt`/`ule` comparisons. adds e010191 [RISCV] Add RISCV.def to module.modulemap adds b40f34e [InstCombine] allow splat vector folds in adjustMinMax() adds 388fc0c GC empty subdirectories. adds c36be93 Fix llvm-shlib cmake build adds c24244e Use the existing std::error_code out parameter. adds 5ec7e2e AMDGPU: Workaround for instruction size with literals adds 605b3b8 [ValueTracking] remove TODO comment; NFC adds cc3e7ce Simplify getStringTableIndex. adds fc92168 [MemorySSA] Tighten up types to make our API prettier. NFC. adds cbbdae4 Don't compute DotShstrtab eagerly. adds 506d8a2 AMDGPU: Stop creating unused virtual registers adds 456b262 Fix uninitialized access in MachineBlockPlacement. adds fd64fad Move the initialization of PreferredLoopExit into runOnMachin [...] adds e9a23c4 AMDGPU: Default to using scalar mov to materialize immediate adds f8e2c0a AMDGPU: Use brev for materializing SGPR constants adds ac4d1bb AMDGPU: Handle CopyToReg in getOperandRegClass adds 72d5de4 [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterI [...] adds 5ded6eb [RISCV] Add bare-bones RISC-V MCTargetDesc adds a0a6883 [docs] Fix some typos. NFC. adds e851658 Bitcode: Change reader interface to take memory buffers. adds 4ac35e8 Support: Remove MemoryObject and DataStreamer interfaces. adds 772d912 Bitcode: Check file size before reading bitcode header. adds 465b55b [ilist_node] Add a getReverseIterator() method and a unittest [...] adds c17dedb Disable the use of std::call_once on OpenBSD with libstdc++. adds 7cfe622 Bitcode: Fix short read implementation. adds 701a1ef [CMake] Set default build type correctly adds 0586c7b [AVR] Add instruction selection lowering code adds 4513397 [Reassociate] Skip analysis of dead code to avoid infinite loop. adds d433991 [llvm] FIx if-clause -Wmisleading-indentation issue. adds ef86dbb [SystemZ] Fix compiler warnings introduced by r285574 adds e0263f5 Simplify. adds ecd7bde Simplify getSection. NFC. adds 8407a2e getNumSections should return a uintX_t. NFC. adds 41b84ed Removing a switch statement that contains a default label, bu [...] adds 8ee0ff8 Avoid a report_fatal_error in sections(). adds 4881f1e Inline getSectionStringTableIndex() into only caller. NFC. adds ab5ea55 Create the virtual register for the global base in the inters [...] adds 6973999 [mips] Always run the MipsOptimizePICCall pass. adds 5d4f1c4 Compute the section table lazily. adds dbce068 Inline a version of getSectionStringTable into the only use. adds 8817e15 Simplify typedefs. NFC. adds 6960085 Use !operator to test if APInt is zero/non-zero. NFCI. adds c49511f Emit DW_OP_piece also if the previous value was a constant. T [...] adds 5561f87 Simplify control flow in the the DWARF expression compiler by [...] adds 0a892bb BranchRelaxation: Fix computing indirect branch block size adds 2ebe5eb Improve and cleanup comments in DwarfExpression.h adds 965be18 [ARM][MC] Cleanup ARM Target Assembly Parser adds 4c12732 Fix Clang-tidy readability-redundant-string-cstr warnings adds 08f7b24 AMDGPU: Allow additional implicit operands on MOVRELS instructions adds d773047 Add CodeViewRecordIO for reading and writing. adds 864b18d Fix build due to missing definition. adds 0786e79 AMDGPU: Cleanup some xfailed tests adds 74a715d [lli/COFF] Set the correct alignment for common symbols adds 714be8b [AMDGPU][mc] Improve test of special asm symbols. adds b051050 [Hexagon] Remove registers coalesced in expand-condsets from [...] adds f13ebed [llvm-cov] Turn line numbers in html reports into clickable links adds a7bfb15 DCE math library calls with a constant operand. adds fade6c2 [RuntimeDyld] Move an X86 only test to the correct directory. adds 4b3270e Add the rest of the additional error checks for invalid Mach- [...] adds 3937406 Emit S_COMPILE3 record once per TU rather than once per function adds a9558ab Simplify some typedefs. NFC. adds 2ad749e Revert "[InstCombine] allow splat vector folds in adjustMinMax()" adds 6e15e36 [ThinLTO] Handle distributed backend case when doing renaming adds d1f0655 Split getSection in two. adds 872445f Expandload and Compressstore intrinsics adds ba1655d [AVX-512] Use 'vnot' instead of 'not' in patterns involving v [...] adds 8186cc4 [CMake] Disable rpath for UnitTests adds 47d5d41 [Object/ELF] - Make getSymbol() return Error. adds d647939 [tools/obj2yaml] - Update after LLVM change r285886 adds e03e2fa [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently adds fdc348b Split getSHNDXTable in two. adds 7450907 Split getStringTableForSymtab. adds 77e7778 Replace a report_fatal_error with an ErrorOr. new 3b7d88c Updating branches/google/stable to r285906

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .arcconfig | 1 - .clang-tidy | 6 +- .gitignore | 2 + CMakeLists.txt | 84 +- CODE_OWNERS.TXT | 12 +- CREDITS.TXT | 5 +- LICENSE.TXT | 2 - bindings/go/llvm/DIBuilderBindings.cpp | 49 +- bindings/go/llvm/DIBuilderBindings.h | 20 +- bindings/go/llvm/dibuilder.go | 30 +- bindings/ocaml/README.txt | 29 + bindings/ocaml/backends/CMakeLists.txt | 2 +- bindings/ocaml/backends/META.llvm_backend.in | 2 +- bindings/ocaml/llvm/CMakeLists.txt | 2 +- bindings/ocaml/llvm/META.llvm.in | 2 +- cmake/config-ix.cmake | 46 +- cmake/modules/AddLLVM.cmake | 127 +- cmake/modules/AddOCaml.cmake | 35 +- cmake/modules/AddSphinxTarget.cmake | 13 +- cmake/modules/CMakeLists.txt | 52 +- cmake/modules/CheckCompilerVersion.cmake | 4 +- cmake/modules/GetHostTriple.cmake | 1 - cmake/modules/HandleLLVMOptions.cmake | 25 +- cmake/modules/HandleLLVMStdlib.cmake | 5 - cmake/modules/LLVMConfig.cmake.in | 9 +- cmake/modules/LLVMExternalProjectUtils.cmake | 10 +- cmake/modules/TableGen.cmake | 32 +- docs/AMDGPUUsage.rst | 284 +- docs/AliasAnalysis.rst | 6 + docs/BitCodeFormat.rst | 246 +- docs/CMake.rst | 15 + docs/CMakeLists.txt | 16 +- docs/CodeGenerator.rst | 30 +- docs/CodingStandards.rst | 40 +- docs/CommandGuide/llvm-cov.rst | 27 +- docs/CommandLine.rst | 27 +- docs/CompileCudaWithLLVM.rst | 634 +- docs/CompilerWriterInfo.rst | 16 +- docs/Coroutines.rst | 184 +- docs/DeveloperPolicy.rst | 83 + docs/Extensions.rst | 16 + docs/GarbageCollection.rst | 2 +- docs/GettingStarted.rst | 26 +- docs/GettingStartedVS.rst | 4 +- docs/HowToAddABuilder.rst | 4 +- docs/LangRef.rst | 107 +- docs/Lexicon.rst | 4 + docs/LibFuzzer.rst | 332 +- docs/MemorySSA.rst | 364 + docs/OptBisect.rst | 197 + docs/ProgrammersManual.rst | 420 +- docs/Proposals/GitHubMove.rst | 868 ++ docs/Proposals/GitHubSubMod.rst | 273 - docs/ReleaseNotes.rst | 6 + docs/ScudoHardenedAllocator.rst | 92 +- docs/SourceLevelDebugging.rst | 77 +- docs/StackMaps.rst | 6 +- docs/WritingAnLLVMBackend.rst | 6 +- docs/WritingAnLLVMPass.rst | 262 +- docs/_static/llvm.css | 2 +- docs/conf.py | 2 +- docs/doxygen.cfg.in | 2 +- docs/index.rst | 12 +- docs/tutorial/BuildingAJIT1.rst | 51 +- docs/tutorial/BuildingAJIT2.rst | 4 +- docs/tutorial/BuildingAJIT3.rst | 21 +- docs/tutorial/LangImpl02.rst | 2 +- docs/tutorial/LangImpl06.rst | 2 +- docs/tutorial/OCamlLangImpl6.rst | 2 +- examples/BrainF/BrainF.cpp | 4 +- examples/ExceptionDemo/ExceptionDemo.cpp | 2 +- .../BuildingAJIT/Chapter1/KaleidoscopeJIT.h | 12 +- .../BuildingAJIT/Chapter2/KaleidoscopeJIT.h | 12 +- .../BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 12 +- .../BuildingAJIT/Chapter4/KaleidoscopeJIT.h | 16 +- .../BuildingAJIT/Chapter5/KaleidoscopeJIT.h | 22 +- .../BuildingAJIT/Chapter5/RemoteJITUtils.h | 4 +- .../BuildingAJIT/Chapter5/Server/CMakeLists.txt | 2 + examples/Kaleidoscope/Chapter2/CMakeLists.txt | 4 + examples/Kaleidoscope/Chapter2/toy.cpp | 33 +- examples/Kaleidoscope/include/KaleidoscopeJIT.h | 10 +- include/llvm-c/Core.h | 3 + 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lib/IR/DebugInfoMetadata.cpp | 82 +- lib/IR/DiagnosticInfo.cpp | 117 +- lib/IR/Dominators.cpp | 10 +- lib/IR/Function.cpp | 83 +- lib/IR/GCOV.cpp | 1 - lib/IR/Globals.cpp | 20 +- lib/IR/IRPrintingPasses.cpp | 4 +- lib/IR/InlineAsm.cpp | 2 +- lib/IR/Instruction.cpp | 109 +- lib/IR/Instructions.cpp | 150 +- lib/IR/IntrinsicInst.cpp | 10 + lib/IR/LLVMContext.cpp | 13 + lib/IR/LLVMContextImpl.cpp | 11 +- lib/IR/LLVMContextImpl.h | 96 +- lib/IR/LegacyPassManager.cpp | 61 +- lib/IR/MDBuilder.cpp | 6 + lib/IR/Mangler.cpp | 2 +- lib/IR/Metadata.cpp | 116 +- lib/IR/ModuleSummaryIndex.cpp | 21 +- lib/IR/Pass.cpp | 4 +- lib/IR/PassManager.cpp | 2 + lib/IR/PassRegistry.cpp | 3 +- lib/IR/SymbolTableListTraitsImpl.h | 5 +- lib/IR/Type.cpp | 11 +- lib/IR/User.cpp | 5 +- lib/IR/Value.cpp | 24 +- lib/IR/ValueSymbolTable.cpp | 8 +- lib/IR/ValueTypes.cpp | 2 +- lib/IR/Verifier.cpp | 339 +- lib/LLVMBuild.txt | 1 + lib/LTO/CMakeLists.txt | 4 +- lib/LTO/Caching.cpp | 99 + lib/LTO/LLVMBuild.txt | 3 +- lib/LTO/LTO.cpp | 729 +- lib/LTO/LTOBackend.cpp | 373 + lib/LTO/LTOCodeGenerator.cpp | 76 +- lib/LTO/LTOModule.cpp | 59 +- lib/LTO/ThinLTOCodeGenerator.cpp | 36 +- lib/LTO/UpdateCompilerUsed.cpp | 48 +- lib/Linker/IRMover.cpp | 58 +- lib/Linker/LinkModules.cpp | 3 +- lib/MC/ConstantPools.cpp | 4 +- lib/MC/ELFObjectWriter.cpp | 2 +- lib/MC/MCAsmBackend.cpp | 4 + lib/MC/MCAsmInfo.cpp | 1 - lib/MC/MCAsmInfoDarwin.cpp | 1 - lib/MC/MCAsmStreamer.cpp | 111 +- lib/MC/MCCodeView.cpp | 216 +- lib/MC/MCContext.cpp | 10 +- lib/MC/MCDisassembler/Disassembler.cpp | 31 +- lib/MC/MCDwarf.cpp | 5 +- lib/MC/MCExpr.cpp | 10 +- lib/MC/MCFragment.cpp | 11 +- lib/MC/MCInst.cpp | 4 - lib/MC/MCLabel.cpp | 2 - lib/MC/MCObjectFileInfo.cpp | 49 +- lib/MC/MCObjectStreamer.cpp | 69 +- lib/MC/MCParser/AsmLexer.cpp | 142 +- lib/MC/MCParser/AsmParser.cpp | 1496 ++-- lib/MC/MCParser/COFFAsmParser.cpp | 41 +- lib/MC/MCParser/DarwinAsmParser.cpp | 13 +- lib/MC/MCParser/MCAsmLexer.cpp | 3 +- lib/MC/MCParser/MCAsmParser.cpp | 104 +- lib/MC/MCRegisterInfo.cpp | 4 + lib/MC/MCSection.cpp | 10 - lib/MC/MCSectionCOFF.cpp | 3 + lib/MC/MCSectionMachO.cpp | 30 +- lib/MC/MCStreamer.cpp | 69 +- lib/MC/MCSymbol.cpp | 7 +- lib/MC/MCTargetOptions.cpp | 3 +- lib/MC/MCValue.cpp | 2 - lib/MC/MachObjectWriter.cpp | 6 +- lib/MC/StringTableBuilder.cpp | 159 +- lib/MC/SubtargetFeature.cpp | 2 - lib/MC/WinCOFFObjectWriter.cpp | 3 +- lib/Object/Archive.cpp | 262 +- lib/Object/ArchiveWriter.cpp | 63 +- lib/Object/COFFObjectFile.cpp | 39 +- lib/Object/ELF.cpp | 14 + lib/Object/Error.cpp | 6 +- lib/Object/IRObjectFile.cpp | 9 +- lib/Object/MachOObjectFile.cpp | 1187 ++- lib/Object/MachOUniversal.cpp | 10 +- lib/Object/ObjectFile.cpp | 4 +- lib/Object/RecordStreamer.cpp | 16 +- lib/Object/RecordStreamer.h | 3 +- lib/Object/SymbolicFile.cpp | 2 +- lib/ObjectYAML/ELFYAML.cpp | 4 + lib/ObjectYAML/MachOYAML.cpp | 10 +- lib/ObjectYAML/ObjectYAML.cpp | 2 +- lib/Option/ArgList.cpp | 33 +- lib/Option/OptTable.cpp | 6 +- lib/Passes/PassBuilder.cpp | 598 +- lib/Passes/PassRegistry.def | 14 +- lib/ProfileData/Coverage/CoverageMapping.cpp | 129 +- lib/ProfileData/Coverage/CoverageMappingWriter.cpp | 12 +- lib/ProfileData/InstrProf.cpp | 7 +- lib/ProfileData/InstrProfReader.cpp | 5 +- lib/ProfileData/InstrProfWriter.cpp | 22 +- lib/ProfileData/ProfileSummaryBuilder.cpp | 6 +- lib/ProfileData/SampleProf.cpp | 2 +- lib/Support/APFloat.cpp | 758 +- lib/Support/APInt.cpp | 10 +- lib/Support/ARMBuildAttrs.cpp | 18 +- lib/Support/CMakeLists.txt | 9 +- lib/Support/CachePruning.cpp | 26 +- lib/Support/Chrono.cpp | 47 + lib/Support/CommandLine.cpp | 168 +- lib/Support/Compression.cpp | 23 +- lib/Support/ConvertUTF.c | 708 -- lib/Support/ConvertUTF.cpp | 710 ++ lib/Support/DataStream.cpp | 86 - lib/Support/DeltaAlgorithm.cpp | 1 + lib/Support/Dwarf.cpp | 421 +- lib/Support/Error.cpp | 3 +- lib/Support/FileOutputBuffer.cpp | 3 + lib/Support/FileUtilities.cpp | 8 +- lib/Support/FoldingSet.cpp | 12 +- lib/Support/Host.cpp | 119 +- lib/Support/LLVMBuild.txt | 1 + lib/Support/LockFileManager.cpp | 16 +- lib/Support/MemoryBuffer.cpp | 22 +- lib/Support/MemoryObject.cpp | 14 - lib/Support/NativeFormatting.cpp | 244 + lib/Support/Path.cpp | 10 +- lib/Support/PrettyStackTrace.cpp | 16 +- lib/Support/RandomNumberGenerator.cpp | 44 +- lib/Support/Regex.cpp | 12 + lib/Support/SmallPtrSet.cpp | 3 +- lib/Support/SourceMgr.cpp | 8 +- lib/Support/SpecialCaseList.cpp | 4 - lib/Support/Statistic.cpp | 21 +- lib/Support/StreamingMemoryObject.cpp | 138 - lib/Support/StringMap.cpp | 10 +- lib/Support/StringRef.cpp | 83 +- lib/Support/StringSaver.cpp | 4 +- lib/Support/TargetParser.cpp | 31 +- lib/Support/TargetRegistry.cpp | 5 +- lib/Support/Threading.cpp | 11 + lib/Support/TimeValue.cpp | 17 +- lib/Support/Timer.cpp | 38 +- lib/Support/Triple.cpp | 43 +- lib/Support/Unix/Memory.inc | 20 +- lib/Support/Unix/Path.inc | 23 +- lib/Support/Unix/Process.inc | 29 +- lib/Support/Unix/Signals.inc | 42 +- lib/Support/Unix/TimeValue.inc | 54 - lib/Support/Unix/Unix.h | 40 +- lib/Support/Windows/Path.inc | 34 +- lib/Support/Windows/Process.inc | 22 +- lib/Support/Windows/Signals.inc | 4 +- lib/Support/Windows/TimeValue.inc | 61 - lib/Support/Windows/WindowsSupport.h | 40 +- lib/Support/YAMLParser.cpp | 58 +- lib/Support/raw_ostream.cpp | 187 +- lib/Support/xxhash.cpp | 134 + lib/TableGen/Record.cpp | 23 +- lib/TableGen/TGLexer.cpp | 15 +- lib/TableGen/TGParser.cpp | 33 +- lib/Target/AArch64/AArch64.h | 4 +- lib/Target/AArch64/AArch64.td | 53 +- lib/Target/AArch64/AArch64A53Fix835769.cpp | 4 +- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp | 4 +- lib/Target/AArch64/AArch64AddressTypePromotion.cpp | 4 +- lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp | 4 +- lib/Target/AArch64/AArch64AsmPrinter.cpp | 18 +- lib/Target/AArch64/AArch64BranchRelaxation.cpp | 512 -- lib/Target/AArch64/AArch64CallLowering.cpp | 380 +- lib/Target/AArch64/AArch64CallLowering.h | 73 +- lib/Target/AArch64/AArch64CallingConvention.td | 1 + .../AArch64/AArch64CleanupLocalDynamicTLSPass.cpp | 2 +- lib/Target/AArch64/AArch64CollectLOH.cpp | 32 +- lib/Target/AArch64/AArch64ConditionOptimizer.cpp | 2 +- lib/Target/AArch64/AArch64ConditionalCompares.cpp | 6 +- .../AArch64/AArch64DeadRegisterDefinitionsPass.cpp | 111 +- lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 4 +- lib/Target/AArch64/AArch64FastISel.cpp | 29 +- lib/Target/AArch64/AArch64FrameLowering.cpp | 3 +- lib/Target/AArch64/AArch64GenRegisterBankInfo.def | 152 + lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 19 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 289 +- lib/Target/AArch64/AArch64ISelLowering.h | 31 +- lib/Target/AArch64/AArch64InstrAtomics.td | 14 +- lib/Target/AArch64/AArch64InstrFormats.td | 12 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 230 +- lib/Target/AArch64/AArch64InstrInfo.h | 49 +- lib/Target/AArch64/AArch64InstrInfo.td | 39 +- lib/Target/AArch64/AArch64InstructionSelector.cpp | 921 +- lib/Target/AArch64/AArch64InstructionSelector.h | 6 +- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 204 + lib/Target/AArch64/AArch64LegalizerInfo.h | 30 + lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 61 +- lib/Target/AArch64/AArch64MCInstLower.cpp | 7 +- lib/Target/AArch64/AArch64MachineLegalizer.cpp | 30 - lib/Target/AArch64/AArch64MachineLegalizer.h | 30 - lib/Target/AArch64/AArch64PromoteConstant.cpp | 2 +- .../AArch64/AArch64RedundantCopyElimination.cpp | 10 +- lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 448 +- lib/Target/AArch64/AArch64RegisterBankInfo.h | 14 + lib/Target/AArch64/AArch64RegisterInfo.cpp | 4 + lib/Target/AArch64/AArch64RegisterInfo.h | 3 +- lib/Target/AArch64/AArch64RegisterInfo.td | 2 +- lib/Target/AArch64/AArch64SchedM1.td | 98 +- lib/Target/AArch64/AArch64StorePairSuppress.cpp | 2 +- lib/Target/AArch64/AArch64Subtarget.cpp | 13 +- lib/Target/AArch64/AArch64Subtarget.h | 17 +- lib/Target/AArch64/AArch64TargetMachine.cpp | 66 +- lib/Target/AArch64/AArch64TargetMachine.h | 2 +- lib/Target/AArch64/AArch64TargetObjectFile.cpp | 13 +- lib/Target/AArch64/AArch64TargetObjectFile.h | 4 +- lib/Target/AArch64/AArch64TargetTransformInfo.h | 7 - lib/Target/AArch64/AArch64VectorByElementOpt.cpp | 371 + lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 184 +- lib/Target/AArch64/CMakeLists.txt | 4 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 24 +- .../AArch64/Disassembler/AArch64Disassembler.h | 1 - .../AArch64/MCTargetDesc/AArch64AsmBackend.cpp | 26 +- .../MCTargetDesc/AArch64ELFObjectWriter.cpp | 202 +- .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp | 3 +- .../AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 12 +- .../AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp | 16 +- .../AArch64/MCTargetDesc/AArch64MCTargetDesc.h | 9 +- .../MCTargetDesc/AArch64MachObjectWriter.cpp | 2 +- .../AArch64/TargetInfo/AArch64TargetInfo.cpp | 25 +- lib/Target/AMDGPU/AMDGPU.h | 29 +- lib/Target/AMDGPU/AMDGPU.td | 146 +- lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp | 14 +- lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp | 5 +- lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp | 4 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 323 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 27 +- lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 6 +- lib/Target/AMDGPU/AMDGPUCallLowering.h | 6 +- lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 299 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 188 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 549 +- lib/Target/AMDGPU/AMDGPUISelLowering.h | 52 +- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 1 - lib/Target/AMDGPU/AMDGPUInstrInfo.h | 16 +- lib/Target/AMDGPU/AMDGPUInstrInfo.td | 15 +- lib/Target/AMDGPU/AMDGPUInstructions.td | 56 +- lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 131 +- lib/Target/AMDGPU/AMDGPUMCInstLower.h | 15 +- .../AMDGPU/AMDGPUOpenCLImageTypeLoweringPass.cpp | 2 +- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 15 +- lib/Target/AMDGPU/AMDGPURuntimeMetadata.h | 47 +- lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 154 +- lib/Target/AMDGPU/AMDGPUSubtarget.h | 187 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 94 +- lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp | 13 +- lib/Target/AMDGPU/AMDGPUTargetObjectFile.h | 3 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 2 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 9 +- lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 49 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 899 +- lib/Target/AMDGPU/BUFInstructions.td | 1313 +++ lib/Target/AMDGPU/CIInstructions.td | 336 +- lib/Target/AMDGPU/CMakeLists.txt | 4 + lib/Target/AMDGPU/CaymanInstructions.td | 139 +- lib/Target/AMDGPU/DSInstructions.td | 900 ++ .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 62 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 163 +- lib/Target/AMDGPU/EvergreenInstructions.td | 139 +- lib/Target/AMDGPU/FLATInstructions.td | 524 ++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 254 +- lib/Target/AMDGPU/GCNHazardRecognizer.h | 9 + lib/Target/AMDGPU/GCNSchedStrategy.cpp | 312 + lib/Target/AMDGPU/GCNSchedStrategy.h | 54 + .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 300 +- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 172 +- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 132 +- .../AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp | 25 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 13 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 7 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 200 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h | 1 + lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 48 +- lib/Target/AMDGPU/MIMGInstructions.td | 755 ++ lib/Target/AMDGPU/Processors.td | 70 +- lib/Target/AMDGPU/R600ClauseMergePass.cpp | 4 +- lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 36 +- lib/Target/AMDGPU/R600EmitClauseMarkers.cpp | 4 +- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 2 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 74 +- lib/Target/AMDGPU/R600InstrFormats.td | 4 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 46 +- lib/Target/AMDGPU/R600InstrInfo.h | 27 +- lib/Target/AMDGPU/R600Instructions.td | 51 +- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 12 +- lib/Target/AMDGPU/R600Packetizer.cpp | 4 +- lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 9 +- lib/Target/AMDGPU/SIDebuggerInsertNops.cpp | 2 +- lib/Target/AMDGPU/SIDefines.h | 73 +- .../AMDGPU/SIFixControlFlowLiveIntervals.cpp | 4 +- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 228 +- lib/Target/AMDGPU/SIFrameLowering.cpp | 399 +- lib/Target/AMDGPU/SIFrameLowering.h | 23 + lib/Target/AMDGPU/SIISelLowering.cpp | 841 +- lib/Target/AMDGPU/SIISelLowering.h | 20 +- lib/Target/AMDGPU/SIInsertSkips.cpp | 330 + lib/Target/AMDGPU/SIInsertWaits.cpp | 52 +- lib/Target/AMDGPU/SIInstrFormats.td | 582 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 784 +- lib/Target/AMDGPU/SIInstrInfo.h | 119 +- lib/Target/AMDGPU/SIInstrInfo.td | 3171 +------ lib/Target/AMDGPU/SIInstructions.td | 3255 +------ lib/Target/AMDGPU/SIIntrinsics.td | 14 +- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 286 +- lib/Target/AMDGPU/SILowerControlFlow.cpp | 564 +- lib/Target/AMDGPU/SILowerI1Copies.cpp | 6 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 21 +- lib/Target/AMDGPU/SIMachineFunctionInfo.h | 56 +- lib/Target/AMDGPU/SIMachineScheduler.cpp | 11 +- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 304 + lib/Target/AMDGPU/SIRegisterInfo.cpp | 836 +- lib/Target/AMDGPU/SIRegisterInfo.h | 122 +- lib/Target/AMDGPU/SIRegisterInfo.td | 86 +- lib/Target/AMDGPU/SISchedule.td | 6 +- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 156 +- lib/Target/AMDGPU/SITypeRewriter.cpp | 4 +- lib/Target/AMDGPU/SIWholeQuadMode.cpp | 450 +- lib/Target/AMDGPU/SMInstructions.td | 517 ++ lib/Target/AMDGPU/SOPInstructions.td | 1190 +++ lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp | 17 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 254 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 112 +- lib/Target/AMDGPU/Utils/AMDKernelCodeTInfo.h | 131 +- lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp | 29 +- lib/Target/AMDGPU/VIInstrFormats.td | 277 - lib/Target/AMDGPU/VIInstructions.td | 148 - lib/Target/AMDGPU/VOP1Instructions.td | 570 ++ lib/Target/AMDGPU/VOP2Instructions.td | 609 ++ lib/Target/AMDGPU/VOP3Instructions.td | 404 + lib/Target/AMDGPU/VOPCInstructions.td | 956 ++ lib/Target/AMDGPU/VOPInstructions.td | 296 + lib/Target/ARM/A15SDOptimizer.cpp | 4 +- lib/Target/ARM/ARM.td | 32 +- lib/Target/ARM/ARMAsmPrinter.cpp | 237 +- lib/Target/ARM/ARMAsmPrinter.h | 28 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 83 +- lib/Target/ARM/ARMBaseInstrInfo.h | 14 +- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 21 +- lib/Target/ARM/ARMBaseRegisterInfo.h | 3 +- lib/Target/ARM/ARMCallingConv.td | 1 + lib/Target/ARM/ARMConstantIslandPass.cpp | 129 +- lib/Target/ARM/ARMConstantPoolValue.cpp | 33 +- lib/Target/ARM/ARMConstantPoolValue.h | 31 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 5 +- lib/Target/ARM/ARMFastISel.cpp | 45 +- lib/Target/ARM/ARMFrameLowering.cpp | 193 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 232 +- lib/Target/ARM/ARMISelLowering.cpp | 615 +- lib/Target/ARM/ARMISelLowering.h | 10 + lib/Target/ARM/ARMInstrFormats.td | 9 + lib/Target/ARM/ARMInstrInfo.cpp | 4 +- lib/Target/ARM/ARMInstrInfo.td | 63 +- lib/Target/ARM/ARMInstrNEON.td | 14 +- lib/Target/ARM/ARMInstrThumb.td | 105 +- lib/Target/ARM/ARMInstrThumb2.td | 59 +- lib/Target/ARM/ARMInstrVFP.td | 8 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 12 +- lib/Target/ARM/ARMMCInstLower.cpp | 99 + lib/Target/ARM/ARMMachineFunctionInfo.cpp | 12 +- lib/Target/ARM/ARMMachineFunctionInfo.h | 25 +- lib/Target/ARM/ARMOptimizeBarriersPass.cpp | 6 +- lib/Target/ARM/ARMSubtarget.cpp | 29 +- lib/Target/ARM/ARMSubtarget.h | 26 +- lib/Target/ARM/ARMTargetMachine.cpp | 25 +- lib/Target/ARM/ARMTargetObjectFile.cpp | 9 +- lib/Target/ARM/ARMTargetObjectFile.h | 10 +- lib/Target/ARM/ARMTargetTransformInfo.cpp | 21 +- lib/Target/ARM/ARMTargetTransformInfo.h | 17 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 1026 +-- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 14 +- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 37 +- lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 26 +- lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 4 +- lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 2 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 21 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h | 6 +- .../ARM/MCTargetDesc/ARMMachObjectWriter.cpp | 2 +- lib/Target/ARM/MLxExpansionPass.cpp | 13 +- lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp | 34 +- lib/Target/ARM/Thumb1FrameLowering.cpp | 275 +- lib/Target/ARM/Thumb2ITBlockPass.cpp | 4 +- lib/Target/ARM/Thumb2SizeReduction.cpp | 10 +- lib/Target/AVR/AVR.td | 526 +- lib/Target/AVR/AVRAsmPrinter.cpp | 182 + lib/Target/AVR/AVRCallingConv.td | 6 +- lib/Target/AVR/AVRDevices.td | 491 ++ lib/Target/AVR/AVRFrameLowering.cpp | 539 ++ lib/Target/AVR/AVRISelDAGToDAG.cpp | 562 ++ lib/Target/AVR/AVRISelLowering.cpp | 1937 +++++ lib/Target/AVR/AVRISelLowering.h | 15 +- lib/Target/AVR/AVRInstrFormats.td | 2 + lib/Target/AVR/AVRInstrInfo.cpp | 78 +- lib/Target/AVR/AVRInstrInfo.h | 12 +- lib/Target/AVR/AVRInstrInfo.td | 106 +- lib/Target/AVR/AVRMCInstLower.cpp | 100 + lib/Target/AVR/AVRMCInstLower.h | 43 + lib/Target/AVR/AVRRegisterInfo.cpp | 12 +- lib/Target/AVR/AVRRegisterInfo.h | 6 +- lib/Target/AVR/AVRTargetMachine.cpp | 6 +- lib/Target/AVR/AVRTargetObjectFile.cpp | 9 +- lib/Target/AVR/AVRTargetObjectFile.h | 3 +- lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 631 ++ lib/Target/AVR/AsmParser/CMakeLists.txt | 3 + lib/Target/AVR/AsmParser/LLVMBuild.txt | 23 + lib/Target/AVR/CMakeLists.txt | 19 +- lib/Target/AVR/Disassembler/AVRDisassembler.cpp | 156 + lib/Target/AVR/Disassembler/CMakeLists.txt | 4 + lib/Target/AVR/Disassembler/LLVMBuild.txt | 23 + lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp | 172 + lib/Target/AVR/InstPrinter/AVRInstPrinter.h | 54 + lib/Target/AVR/InstPrinter/CMakeLists.txt | 8 + lib/Target/AVR/InstPrinter/LLVMBuild.txt | 23 + lib/Target/AVR/LLVMBuild.txt | 10 +- lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp | 473 + lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h | 78 + lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp | 127 + lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h | 149 + lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp | 304 + lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h | 115 + lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp | 189 + lib/Target/AVR/MCTargetDesc/AVRMCExpr.h | 88 + lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp | 121 + lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h | 6 +- lib/Target/AVR/MCTargetDesc/CMakeLists.txt | 5 + lib/Target/AVR/MCTargetDesc/LLVMBuild.txt | 2 +- lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp | 14 +- lib/Target/BPF/BPFAsmPrinter.cpp | 8 +- lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- lib/Target/BPF/BPFInstrInfo.cpp | 14 +- lib/Target/BPF/BPFInstrInfo.h | 8 +- lib/Target/BPF/BPFTargetMachine.cpp | 6 +- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp | 27 +- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h | 6 +- lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp | 26 +- lib/Target/CMakeLists.txt | 1 - lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 213 +- lib/Target/Hexagon/BitTracker.cpp | 20 +- lib/Target/Hexagon/BitTracker.h | 2 + lib/Target/Hexagon/CMakeLists.txt | 3 +- .../Hexagon/Disassembler/HexagonDisassembler.cpp | 626 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 33 +- lib/Target/Hexagon/HexagonAsmPrinter.h | 2 +- lib/Target/Hexagon/HexagonBitSimplify.cpp | 145 +- lib/Target/Hexagon/HexagonBitTracker.cpp | 32 +- lib/Target/Hexagon/HexagonBlockRanges.cpp | 44 +- lib/Target/Hexagon/HexagonBlockRanges.h | 3 +- lib/Target/Hexagon/HexagonBranchRelaxation.cpp | 2 +- lib/Target/Hexagon/HexagonCFGOptimizer.cpp | 20 +- lib/Target/Hexagon/HexagonCommonGEP.cpp | 8 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 32 +- lib/Target/Hexagon/HexagonCopyToCombine.cpp | 86 +- lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 52 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 301 +- lib/Target/Hexagon/HexagonFixupHwLoops.cpp | 4 +- lib/Target/Hexagon/HexagonFrameLowering.cpp | 191 +- lib/Target/Hexagon/HexagonFrameLowering.h | 3 +- lib/Target/Hexagon/HexagonGenExtract.cpp | 4 +- lib/Target/Hexagon/HexagonGenInsert.cpp | 14 +- lib/Target/Hexagon/HexagonGenMux.cpp | 12 +- lib/Target/Hexagon/HexagonGenPredicate.cpp | 16 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 99 +- lib/Target/Hexagon/HexagonHazardRecognizer.cpp | 6 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 233 +- lib/Target/Hexagon/HexagonISelLowering.cpp | 435 +- lib/Target/Hexagon/HexagonISelLowering.h | 22 +- lib/Target/Hexagon/HexagonInstrAlias.td | 64 +- lib/Target/Hexagon/HexagonInstrFormats.td | 3 + lib/Target/Hexagon/HexagonInstrFormatsV4.td | 4 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 460 +- lib/Target/Hexagon/HexagonInstrInfo.h | 24 +- lib/Target/Hexagon/HexagonInstrInfo.td | 423 +- lib/Target/Hexagon/HexagonInstrInfoV3.td | 34 +- lib/Target/Hexagon/HexagonInstrInfoV4.td | 524 +- lib/Target/Hexagon/HexagonInstrInfoV5.td | 364 +- lib/Target/Hexagon/HexagonInstrInfoV60.td | 352 +- lib/Target/Hexagon/HexagonInstrInfoVector.td | 48 +- lib/Target/Hexagon/HexagonIntrinsics.td | 40 +- lib/Target/Hexagon/HexagonIntrinsicsV4.td | 18 +- lib/Target/Hexagon/HexagonIntrinsicsV60.td | 71 +- lib/Target/Hexagon/HexagonIsetDx.td | 138 +- lib/Target/Hexagon/HexagonMachineFunctionInfo.h | 8 - lib/Target/Hexagon/HexagonMachineScheduler.cpp | 2 + lib/Target/Hexagon/HexagonMachineScheduler.h | 4 +- lib/Target/Hexagon/HexagonNewValueJump.cpp | 50 +- lib/Target/Hexagon/HexagonOperands.td | 300 +- lib/Target/Hexagon/HexagonOptAddrMode.cpp | 20 +- lib/Target/Hexagon/HexagonOptimizeSZextends.cpp | 7 +- lib/Target/Hexagon/HexagonPeephole.cpp | 7 +- lib/Target/Hexagon/HexagonRDF.cpp | 60 - lib/Target/Hexagon/HexagonRDF.h | 28 - lib/Target/Hexagon/HexagonRDFOpt.cpp | 32 +- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 5 +- lib/Target/Hexagon/HexagonRegisterInfo.td | 14 +- lib/Target/Hexagon/HexagonSelectCCInfo.td | 121 - lib/Target/Hexagon/HexagonSelectionDAGInfo.h | 2 + .../Hexagon/HexagonSplitConst32AndConst64.cpp | 122 +- lib/Target/Hexagon/HexagonSplitDouble.cpp | 11 +- lib/Target/Hexagon/HexagonStoreWidening.cpp | 4 +- lib/Target/Hexagon/HexagonSubtarget.cpp | 14 +- lib/Target/Hexagon/HexagonSystemInst.td | 2 +- lib/Target/Hexagon/HexagonTargetMachine.cpp | 20 +- lib/Target/Hexagon/HexagonTargetObjectFile.cpp | 87 +- lib/Target/Hexagon/HexagonTargetObjectFile.h | 18 +- lib/Target/Hexagon/HexagonTargetTransformInfo.cpp | 25 + lib/Target/Hexagon/HexagonTargetTransformInfo.h | 9 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 60 +- lib/Target/Hexagon/HexagonVectorPrint.cpp | 191 + .../Hexagon/MCTargetDesc/HexagonAsmBackend.cpp | 4 +- lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 5 +- .../Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 238 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 111 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 3 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 24 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.h | 4 +- .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 10 +- lib/Target/Hexagon/RDFCopy.cpp | 69 +- lib/Target/Hexagon/RDFCopy.h | 1 + lib/Target/Hexagon/RDFGraph.cpp | 648 +- lib/Target/Hexagon/RDFGraph.h | 258 +- lib/Target/Hexagon/RDFLiveness.cpp | 538 +- lib/Target/Hexagon/RDFLiveness.h | 44 +- .../Hexagon/TargetInfo/HexagonTargetInfo.cpp | 8 +- lib/Target/LLVMBuild.txt | 1 + lib/Target/Lanai/AsmParser/LLVMBuild.txt | 2 +- lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp | 6 +- lib/Target/Lanai/Disassembler/LLVMBuild.txt | 2 +- .../Lanai/Disassembler/LanaiDisassembler.cpp | 10 +- lib/Target/Lanai/LLVMBuild.txt | 2 +- lib/Target/Lanai/Lanai.h | 2 +- lib/Target/Lanai/LanaiAluCode.h | 4 +- lib/Target/Lanai/LanaiAsmPrinter.cpp | 8 +- lib/Target/Lanai/LanaiDelaySlotFiller.cpp | 15 +- lib/Target/Lanai/LanaiISelDAGToDAG.cpp | 2 +- lib/Target/Lanai/LanaiISelLowering.cpp | 3 +- lib/Target/Lanai/LanaiInstrInfo.cpp | 19 +- lib/Target/Lanai/LanaiInstrInfo.h | 10 +- lib/Target/Lanai/LanaiInstrInfo.td | 3 - lib/Target/Lanai/LanaiMCInstLower.cpp | 1 - lib/Target/Lanai/LanaiMCInstLower.h | 3 +- lib/Target/Lanai/LanaiMemAluCombiner.cpp | 7 +- lib/Target/Lanai/LanaiTargetMachine.cpp | 3 +- lib/Target/Lanai/LanaiTargetObjectFile.cpp | 39 +- lib/Target/Lanai/LanaiTargetObjectFile.h | 14 +- lib/Target/Lanai/LanaiTargetTransformInfo.h | 5 - lib/Target/Lanai/MCTargetDesc/CMakeLists.txt | 2 +- lib/Target/Lanai/MCTargetDesc/LLVMBuild.txt | 4 +- .../Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp | 17 - .../Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp | 29 +- lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h | 2 +- lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp | 9 +- .../MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp | 11 +- .../MSP430/MCTargetDesc/MSP430MCTargetDesc.h | 2 +- lib/Target/MSP430/MSP430AsmPrinter.cpp | 6 +- lib/Target/MSP430/MSP430BranchSelector.cpp | 8 +- lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 2 +- lib/Target/MSP430/MSP430ISelLowering.cpp | 15 +- lib/Target/MSP430/MSP430InstrInfo.cpp | 15 +- lib/Target/MSP430/MSP430InstrInfo.h | 10 +- lib/Target/MSP430/MSP430TargetMachine.cpp | 2 +- lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp | 11 +- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 681 +- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 180 +- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 14 +- lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h | 5 +- .../Mips/MCTargetDesc/MipsELFObjectWriter.cpp | 14 +- lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h | 4 + lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp | 9 + lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 33 +- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h | 7 + lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 17 +- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h | 8 +- lib/Target/Mips/MicroMips32r6InstrInfo.td | 575 +- lib/Target/Mips/MicroMips64r6InstrFormats.td | 46 + lib/Target/Mips/MicroMips64r6InstrInfo.td | 110 +- lib/Target/Mips/MicroMipsInstrFPU.td | 21 +- lib/Target/Mips/MicroMipsInstrFormats.td | 24 + lib/Target/Mips/MicroMipsInstrInfo.td | 237 +- lib/Target/Mips/Mips.td | 6 +- lib/Target/Mips/Mips16HardFloat.cpp | 4 +- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 7 +- lib/Target/Mips/Mips16InstrInfo.cpp | 4 +- lib/Target/Mips/Mips32r6InstrFormats.td | 16 + lib/Target/Mips/Mips32r6InstrInfo.td | 192 +- lib/Target/Mips/Mips64InstrInfo.td | 50 +- lib/Target/Mips/Mips64r6InstrInfo.td | 23 +- lib/Target/Mips/MipsAsmPrinter.cpp | 25 +- lib/Target/Mips/MipsAsmPrinter.h | 4 +- lib/Target/Mips/MipsConstantIslandPass.cpp | 11 +- lib/Target/Mips/MipsDelaySlotFiller.cpp | 54 +- lib/Target/Mips/MipsEVAInstrFormats.td | 4 +- lib/Target/Mips/MipsFastISel.cpp | 127 +- lib/Target/Mips/MipsHazardSchedule.cpp | 4 +- lib/Target/Mips/MipsISelDAGToDAG.h | 2 +- lib/Target/Mips/MipsISelLowering.cpp | 69 +- lib/Target/Mips/MipsISelLowering.h | 2 +- lib/Target/Mips/MipsInstrFPU.td | 43 +- lib/Target/Mips/MipsInstrFormats.td | 4 + lib/Target/Mips/MipsInstrInfo.cpp | 53 +- lib/Target/Mips/MipsInstrInfo.h | 10 +- lib/Target/Mips/MipsInstrInfo.td | 110 +- lib/Target/Mips/MipsLongBranch.cpp | 10 +- lib/Target/Mips/MipsMSAInstrInfo.td | 4 - lib/Target/Mips/MipsModuleISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsOptimizePICCall.cpp | 2 +- lib/Target/Mips/MipsOs16.cpp | 4 +- lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsSEISelLowering.cpp | 10 +- lib/Target/Mips/MipsSchedule.td | 83 +- lib/Target/Mips/MipsScheduleGeneric.td | 1048 +++ lib/Target/Mips/MipsScheduleP5600.td | 254 +- lib/Target/Mips/MipsTargetMachine.cpp | 17 +- lib/Target/Mips/MipsTargetObjectFile.cpp | 40 +- lib/Target/Mips/MipsTargetObjectFile.h | 14 +- lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp | 31 +- lib/Target/NVPTX/CMakeLists.txt | 1 - .../NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp | 2 +- lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h | 4 +- lib/Target/NVPTX/NVPTX.h | 5 +- lib/Target/NVPTX/NVPTX.td | 9 +- lib/Target/NVPTX/NVPTXAllocaHoisting.cpp | 4 +- lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 16 +- lib/Target/NVPTX/NVPTXAsmPrinter.h | 2 +- .../NVPTX/NVPTXFavorNonGenericAddrSpaces.cpp | 289 - lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 37 - lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 48 +- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 +- lib/Target/NVPTX/NVPTXISelLowering.cpp | 146 +- lib/Target/NVPTX/NVPTXISelLowering.h | 3 +- lib/Target/NVPTX/NVPTXInferAddressSpaces.cpp | 3 - lib/Target/NVPTX/NVPTXInstrInfo.cpp | 15 +- lib/Target/NVPTX/NVPTXInstrInfo.h | 8 +- lib/Target/NVPTX/NVPTXInstrInfo.td | 157 +- lib/Target/NVPTX/NVPTXIntrinsics.td | 196 + lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp | 4 +- lib/Target/NVPTX/NVPTXLowerAlloca.cpp | 8 +- lib/Target/NVPTX/NVPTXLowerArgs.cpp | 10 +- lib/Target/NVPTX/NVPTXPeephole.cpp | 2 +- lib/Target/NVPTX/NVPTXRegisterInfo.cpp | 24 +- lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp | 2 +- lib/Target/NVPTX/NVPTXSubtarget.cpp | 2 - lib/Target/NVPTX/NVPTXSubtarget.h | 8 + lib/Target/NVPTX/NVPTXTargetMachine.cpp | 22 +- lib/Target/NVPTX/NVPTXTargetObjectFile.h | 6 +- lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp | 23 + lib/Target/NVPTX/NVPTXTargetTransformInfo.h | 7 - lib/Target/NVPTX/NVPTXUtilities.cpp | 8 +- lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp | 14 +- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 60 +- .../PowerPC/Disassembler/PPCDisassembler.cpp | 39 +- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 61 +- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h | 1 + .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 11 +- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 3 +- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 6 +- lib/Target/PowerPC/PPC.td | 59 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 68 +- lib/Target/PowerPC/PPCBoolRetToInt.cpp | 28 +- lib/Target/PowerPC/PPCBranchSelector.cpp | 67 +- lib/Target/PowerPC/PPCCallingConv.td | 26 +- lib/Target/PowerPC/PPCEarlyReturn.cpp | 4 +- lib/Target/PowerPC/PPCFastISel.cpp | 83 +- lib/Target/PowerPC/PPCFrameLowering.cpp | 324 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 222 +- lib/Target/PowerPC/PPCISelLowering.cpp | 540 +- lib/Target/PowerPC/PPCISelLowering.h | 64 +- lib/Target/PowerPC/PPCInstr64Bit.td | 22 +- lib/Target/PowerPC/PPCInstrAltivec.td | 101 +- lib/Target/PowerPC/PPCInstrFormats.td | 59 + lib/Target/PowerPC/PPCInstrInfo.cpp | 123 +- lib/Target/PowerPC/PPCInstrInfo.h | 27 +- lib/Target/PowerPC/PPCInstrInfo.td | 170 +- lib/Target/PowerPC/PPCInstrQPX.td | 10 +- lib/Target/PowerPC/PPCInstrVSX.td | 415 +- lib/Target/PowerPC/PPCMCInstLower.cpp | 8 +- lib/Target/PowerPC/PPCMIPeephole.cpp | 59 + lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 13 +- lib/Target/PowerPC/PPCRegisterInfo.h | 2 +- lib/Target/PowerPC/PPCRegisterInfo.td | 35 +- lib/Target/PowerPC/PPCSchedule.td | 1 + lib/Target/PowerPC/PPCSubtarget.cpp | 3 +- lib/Target/PowerPC/PPCSubtarget.h | 9 +- lib/Target/PowerPC/PPCTargetMachine.cpp | 25 +- lib/Target/PowerPC/PPCTargetObjectFile.cpp | 8 +- lib/Target/PowerPC/PPCTargetObjectFile.h | 3 +- lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 7 +- lib/Target/PowerPC/PPCTargetTransformInfo.h | 7 - lib/Target/PowerPC/PPCVSXCopy.cpp | 18 +- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 3 +- lib/Target/PowerPC/README.txt | 6 + .../PowerPC/TargetInfo/PowerPCTargetInfo.cpp | 25 +- lib/Target/README.txt | 4 +- lib/Target/RISCV/CMakeLists.txt | 14 + lib/Target/RISCV/LLVMBuild.txt | 31 + lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 7 + lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt | 23 + lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 91 + .../RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp | 47 + lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp | 25 + lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h | 31 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 91 + .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 59 + lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h | 58 + lib/Target/RISCV/RISCV.td | 27 + lib/Target/RISCV/RISCVInstrFormats.td | 152 + lib/Target/RISCV/RISCVInstrInfo.td | 55 + lib/Target/RISCV/RISCVRegisterInfo.td | 90 + lib/Target/RISCV/RISCVTargetMachine.cpp | 58 + lib/Target/RISCV/RISCVTargetMachine.h | 40 + lib/Target/RISCV/TargetInfo/CMakeLists.txt | 3 + lib/Target/RISCV/TargetInfo/LLVMBuild.txt | 23 + lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp | 30 + lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 30 +- lib/Target/Sparc/DelaySlotFiller.cpp | 6 +- .../Sparc/Disassembler/SparcDisassembler.cpp | 10 +- lib/Target/Sparc/LeonFeatures.td | 131 +- lib/Target/Sparc/LeonPasses.cpp | 645 +- lib/Target/Sparc/LeonPasses.h | 114 +- .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp | 15 +- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h | 6 +- lib/Target/Sparc/Sparc.td | 147 +- lib/Target/Sparc/SparcAsmPrinter.cpp | 10 +- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 21 +- lib/Target/Sparc/SparcISelLowering.cpp | 81 +- lib/Target/Sparc/SparcInstrInfo.cpp | 42 +- lib/Target/Sparc/SparcInstrInfo.h | 10 +- lib/Target/Sparc/SparcInstrInfo.td | 24 +- lib/Target/Sparc/SparcSubtarget.cpp | 9 +- lib/Target/Sparc/SparcSubtarget.h | 20 +- lib/Target/Sparc/SparcTargetMachine.cpp | 57 +- lib/Target/Sparc/SparcTargetObjectFile.cpp | 13 +- lib/Target/Sparc/SparcTargetObjectFile.h | 10 +- lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp | 21 +- lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 531 +- lib/Target/SystemZ/CMakeLists.txt | 2 + .../SystemZ/Disassembler/SystemZDisassembler.cpp | 21 +- .../SystemZ/InstPrinter/SystemZInstPrinter.cpp | 16 + .../SystemZ/InstPrinter/SystemZInstPrinter.h | 2 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lib/Target/SystemZ/SystemZLongBranch.cpp | 6 +- lib/Target/SystemZ/SystemZMachineScheduler.cpp | 153 + lib/Target/SystemZ/SystemZMachineScheduler.h | 112 + lib/Target/SystemZ/SystemZOperands.td | 20 + lib/Target/SystemZ/SystemZOperators.td | 13 +- lib/Target/SystemZ/SystemZProcessors.td | 103 +- lib/Target/SystemZ/SystemZRegisterInfo.td | 8 + lib/Target/SystemZ/SystemZSchedule.td | 70 + lib/Target/SystemZ/SystemZScheduleZ13.td | 993 +++ lib/Target/SystemZ/SystemZScheduleZ196.td | 715 ++ lib/Target/SystemZ/SystemZScheduleZEC12.td | 745 ++ lib/Target/SystemZ/SystemZShortenInst.cpp | 4 +- lib/Target/SystemZ/SystemZTargetMachine.cpp | 18 +- lib/Target/SystemZ/SystemZTargetTransformInfo.cpp | 57 + lib/Target/SystemZ/SystemZTargetTransformInfo.h | 9 +- .../SystemZ/TargetInfo/SystemZTargetInfo.cpp | 9 +- lib/Target/TargetLoweringObjectFile.cpp | 61 +- lib/Target/TargetMachine.cpp | 26 +- lib/Target/TargetMachineC.cpp | 5 +- lib/Target/TargetRecip.cpp | 225 - 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| 3 + lib/Target/X86/X86Subtarget.h | 16 + lib/Target/X86/X86TargetMachine.cpp | 29 +- lib/Target/X86/X86TargetMachine.h | 2 - lib/Target/X86/X86TargetObjectFile.cpp | 34 +- lib/Target/X86/X86TargetObjectFile.h | 24 +- lib/Target/X86/X86TargetTransformInfo.cpp | 309 +- lib/Target/X86/X86TargetTransformInfo.h | 9 +- lib/Target/X86/X86VZeroUpper.cpp | 4 +- lib/Target/X86/X86WinAllocaExpander.cpp | 3 +- lib/Target/X86/X86WinEHState.cpp | 2 +- .../XCore/Disassembler/XCoreDisassembler.cpp | 4 +- .../XCore/MCTargetDesc/XCoreMCTargetDesc.cpp | 16 +- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h | 3 +- lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp | 7 +- lib/Target/XCore/XCoreAsmPrinter.cpp | 13 +- lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp | 4 +- lib/Target/XCore/XCoreISelDAGToDAG.cpp | 2 +- lib/Target/XCore/XCoreInstrInfo.cpp | 22 +- lib/Target/XCore/XCoreInstrInfo.h | 10 +- lib/Target/XCore/XCoreInstrInfo.td | 8 - lib/Target/XCore/XCoreMCInstLower.cpp | 7 +- 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+- lib/Transforms/IPO/FunctionImport.cpp | 125 +- lib/Transforms/IPO/GlobalDCE.cpp | 54 +- lib/Transforms/IPO/GlobalOpt.cpp | 8 +- lib/Transforms/IPO/IPO.cpp | 5 +- lib/Transforms/IPO/InferFunctionAttrs.cpp | 2 +- lib/Transforms/IPO/InlineAlways.cpp | 103 - lib/Transforms/IPO/InlineSimple.cpp | 38 +- lib/Transforms/IPO/Inliner.cpp | 333 +- lib/Transforms/IPO/Internalize.cpp | 2 +- lib/Transforms/IPO/LowerTypeTests.cpp | 235 +- lib/Transforms/IPO/MergeFunctions.cpp | 1 + lib/Transforms/IPO/PartialInlining.cpp | 15 +- lib/Transforms/IPO/PassManagerBuilder.cpp | 59 +- lib/Transforms/IPO/PruneEH.cpp | 5 +- lib/Transforms/IPO/SampleProfile.cpp | 181 +- lib/Transforms/IPO/StripSymbols.cpp | 20 +- lib/Transforms/IPO/WholeProgramDevirt.cpp | 136 +- lib/Transforms/InstCombine/InstCombineAddSub.cpp | 58 +- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 171 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 292 +- lib/Transforms/InstCombine/InstCombineCasts.cpp | 207 +- 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test/CodeGen/X86/avx512-pmovxrm.ll | 199 + test/CodeGen/X86/avx512-regcall-NoMask.ll | 607 ++ test/CodeGen/X86/avx512-select.ll | 50 +- test/CodeGen/X86/avx512-skx-insert-subvec.ll | 3 +- test/CodeGen/X86/avx512-vbroadcast.ll | 10 +- test/CodeGen/X86/avx512-vbroadcasti128.ll | 132 +- test/CodeGen/X86/avx512-vbroadcasti256.ll | 30 +- test/CodeGen/X86/avx512-vec-cmp.ll | 11 +- test/CodeGen/X86/avx512-vpermv3-commute.ll | 367 + test/CodeGen/X86/avx512-vpternlog-commute.ll | 493 ++ test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 192 + test/CodeGen/X86/avx512bw-intrinsics.ll | 200 - test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll | 845 +- test/CodeGen/X86/avx512bwvl-intrinsics.ll | 1418 +-- test/CodeGen/X86/avx512dq-intrinsics.ll | 55 +- test/CodeGen/X86/avx512dq-mask-op.ll | 2 - test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll | 1562 ++++ test/CodeGen/X86/avx512dqvl-intrinsics.ll | 1573 +--- test/CodeGen/X86/avx512vbmi-intrinsics.ll | 14 +- test/CodeGen/X86/avx512vbmivl-intrinsics.ll | 28 +- test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll | 12 +- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 1014 ++- test/CodeGen/X86/avx512vl-intrinsics.ll | 1752 +--- test/CodeGen/X86/avx512vl-logic.ll | 869 +- test/CodeGen/X86/avx512vl-mov.ll | 32 +- test/CodeGen/X86/avx512vl-vec-cmp.ll | 192 + test/CodeGen/X86/bitcast-i256.ll | 2 +- test/CodeGen/X86/block-placement.ll | 18 +- test/CodeGen/X86/branchfolding-undef.mir | 29 + test/CodeGen/X86/break-false-dep.ll | 72 +- test/CodeGen/X86/bt.ll | 12 + test/CodeGen/X86/buildvec-insertvec.ll | 11 +- test/CodeGen/X86/catchpad-reuse.ll | 107 + test/CodeGen/X86/chain_order.ll | 22 +- .../CodeGen/X86/clear_upper_vector_element_bits.ll | 16 +- test/CodeGen/X86/clz.ll | 214 +- test/CodeGen/X86/cmov-into-branch.ll | 8 +- test/CodeGen/X86/coalesce_commute_movsd.ll | 57 + test/CodeGen/X86/coalescer-win64.ll | 4 +- test/CodeGen/X86/code_placement_loop_rotation3.ll | 2 +- test/CodeGen/X86/combine-add.ll | 316 + test/CodeGen/X86/combine-and.ll | 70 +- test/CodeGen/X86/combine-fcopysign.ll | 331 + test/CodeGen/X86/combine-mul.ll | 324 + test/CodeGen/X86/combine-multiplies.ll | 105 +- test/CodeGen/X86/combine-or.ll | 67 + test/CodeGen/X86/combine-sdiv.ll | 188 + test/CodeGen/X86/combine-shl.ll | 563 ++ test/CodeGen/X86/combine-sra.ll | 313 + test/CodeGen/X86/combine-srem.ll | 87 + test/CodeGen/X86/combine-srl.ll | 521 ++ test/CodeGen/X86/combine-sub.ll | 246 + test/CodeGen/X86/combine-udiv.ll | 171 + test/CodeGen/X86/combine-urem.ll | 171 + test/CodeGen/X86/compress_expand.ll | 247 + test/CodeGen/X86/computeKnownBits_urem.ll | 22 +- test/CodeGen/X86/conditional-tailcall.ll | 53 + test/CodeGen/X86/constructor.ll | 2 + test/CodeGen/X86/copy-propagation.ll | 3 +- test/CodeGen/X86/copysign-constant-magnitude.ll | 207 +- test/CodeGen/X86/dagcombine-buildvector.ll | 23 +- .../X86/dbg-changes-codegen-branch-folding.ll | 2 +- test/CodeGen/X86/divide-windows-itanium.ll | 38 + test/CodeGen/X86/dynamic-allocas-VLAs.ll | 4 +- test/CodeGen/X86/eflags-copy-expansion.mir | 2 - test/CodeGen/X86/extractelement-index.ll | 4 +- test/CodeGen/X86/f16c-intrinsics-fast-isel.ll | 10 +- test/CodeGen/X86/f16c-intrinsics.ll | 157 +- test/CodeGen/X86/fast-isel-cmp.ll | 8 +- test/CodeGen/X86/fast-isel-load-i1.ll | 15 + test/CodeGen/X86/fast-isel-select-cmov.ll | 91 +- test/CodeGen/X86/fast-isel-store.ll | 761 +- test/CodeGen/X86/fast-isel-vecload.ll | 933 +- test/CodeGen/X86/fast-isel-x86-64.ll | 2 +- test/CodeGen/X86/fast-isel-x86.ll | 2 +- test/CodeGen/X86/fastcall-correct-mangling.ll | 2 +- test/CodeGen/X86/fixup-bw-copy.mir | 14 - test/CodeGen/X86/fma-fneg-combine.ll | 245 + test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll | 24 +- test/CodeGen/X86/fma_patterns.ll | 26 +- test/CodeGen/X86/fma_patterns_wide.ll | 10 +- test/CodeGen/X86/fold-vector-sext-zext.ll | 312 +- test/CodeGen/X86/fops-windows-itanium.ll | 92 + test/CodeGen/X86/fp-load-trunc.ll | 9 +- test/CodeGen/X86/fp-logic.ll | 2 +- test/CodeGen/X86/fp-trunc.ll | 13 +- test/CodeGen/X86/fp-une-cmp.ll | 4 +- test/CodeGen/X86/fp128-cast.ll | 6 +- test/CodeGen/X86/fpstack-debuginstr-kill.ll | 8 +- test/CodeGen/X86/frameaddr.ll | 4 +- test/CodeGen/X86/gep-expanded-vector.ll | 24 + test/CodeGen/X86/global-access-pie-copyrelocs.ll | 119 + test/CodeGen/X86/haddsub-2.ll | 16 +- test/CodeGen/X86/haddsub-undef.ll | 6 +- test/CodeGen/X86/half.ll | 10 +- test/CodeGen/X86/hidden-vis-pic.ll | 2 +- test/CodeGen/X86/hoist-spill.ll | 1 - test/CodeGen/X86/i64-to-float.ll | 308 + test/CodeGen/X86/immediate_merging64.ll | 38 + test/CodeGen/X86/implicit-null-checks.mir | 9 - test/CodeGen/X86/init-priority.ll | 6 +- .../X86/inline-asm-avx-v-constraint-32bit.ll | 136 + test/CodeGen/X86/inline-asm-avx-v-constraint.ll | 136 + .../CodeGen/X86/inline-asm-avx512f-v-constraint.ll | 72 + .../X86/inline-asm-avx512vl-v-constraint-32bit.ll | 138 + .../X86/inline-asm-avx512vl-v-constraint.ll | 121 + test/CodeGen/X86/inline-asm-tied.ll | 5 +- test/CodeGen/X86/insertelement-zero.ll | 6 +- test/CodeGen/X86/insertps-combine.ll | 31 + test/CodeGen/X86/invalid-liveness.mir | 31 + test/CodeGen/X86/known-bits-vector.ll | 91 + test/CodeGen/X86/known-bits.ll | 107 + test/CodeGen/X86/lea-opt-memop-check-1.ll | 2 +- test/CodeGen/X86/live-range-nosubreg.ll | 48 + test/CodeGen/X86/local_stack_symbol_ordering.ll | 2 +- test/CodeGen/X86/loop-blocks.ll | 35 + test/CodeGen/X86/loop-search.ll | 66 + test/CodeGen/X86/lower-vec-shift.ll | 249 +- test/CodeGen/X86/lsr-loop-exit-cond.ll | 4 +- test/CodeGen/X86/lzcnt-zext-cmp.ll | 341 + test/CodeGen/X86/machine-copy-prop.mir | 12 - test/CodeGen/X86/machine-cse.ll | 9 +- test/CodeGen/X86/machine-sink.ll | 21 + test/CodeGen/X86/mask-negated-bool.ll | 77 + test/CodeGen/X86/masked_gather_scatter.ll | 550 +- test/CodeGen/X86/masked_memop.ll | 9178 +------------------- test/CodeGen/X86/mem-intrin-base-reg.ll | 7 +- test/CodeGen/X86/merge-consecutive-loads-128.ll | 622 +- test/CodeGen/X86/merge-consecutive-loads-256.ll | 52 +- test/CodeGen/X86/merge-consecutive-loads-512.ll | 20 +- .../X86/misched-code-difference-with-debug.ll | 4 +- test/CodeGen/X86/mmx-bitcast.ll | 25 +- test/CodeGen/X86/mul-i1024.ll | 5456 ++++++++++++ test/CodeGen/X86/mul-i512.ll | 1203 +++ test/CodeGen/X86/negate-i1.ll | 154 + test/CodeGen/X86/negate-shift.ll | 49 + test/CodeGen/X86/negate.ll | 68 + test/CodeGen/X86/negative-sin.ll | 101 +- test/CodeGen/X86/nontemporal-2.ll | 2 +- test/CodeGen/X86/nontemporal-loads.ll | 176 +- test/CodeGen/X86/note-sections.ll | 19 + test/CodeGen/X86/oddshuffles.ll | 1472 ++++ test/CodeGen/X86/patchpoint-invoke.ll | 2 +- test/CodeGen/X86/peephole-cvt-sse.ll | 39 + test/CodeGen/X86/phys_subreg_coalesce-2.ll | 2 + test/CodeGen/X86/pmovsx-inreg.ll | 477 +- test/CodeGen/X86/pmul.ll | 101 +- test/CodeGen/X86/pr11202.ll | 5 +- test/CodeGen/X86/pr11334.ll | 14 +- test/CodeGen/X86/pr13577.ll | 32 +- test/CodeGen/X86/pr14204.ll | 17 +- test/CodeGen/X86/pr18014.ll | 18 +- test/CodeGen/X86/pr21792.ll | 4 +- test/CodeGen/X86/pr22774.ll | 12 +- test/CodeGen/X86/pr24374.ll | 3 +- test/CodeGen/X86/pr2656.ll | 2 +- test/CodeGen/X86/pr2659.ll | 3 +- test/CodeGen/X86/pr27591.ll | 21 +- test/CodeGen/X86/pr27681.mir | 1 - test/CodeGen/X86/pr28173.ll | 76 +- test/CodeGen/X86/pr28504.ll | 37 + test/CodeGen/X86/pr28824.ll | 23 + test/CodeGen/X86/pr29010.ll | 12 + test/CodeGen/X86/pr29022.ll | 15 + test/CodeGen/X86/pr29112.ll | 105 + test/CodeGen/X86/pr29170.ll | 32 + test/CodeGen/X86/pr30430.ll | 232 + test/CodeGen/X86/pr30511.ll | 23 + test/CodeGen/X86/pr30813.ll | 27 + test/CodeGen/X86/promote-vec3.ll | 140 + test/CodeGen/X86/pseudo_cmov_lower2.ll | 44 + test/CodeGen/X86/ragreedy-bug.ll | 22 +- test/CodeGen/X86/recip-fastmath.ll | 205 +- test/CodeGen/X86/reduce-trunc-shl.ll | 139 + test/CodeGen/X86/ret-mmx.ll | 43 +- test/CodeGen/X86/rotate.ll | 573 +- test/CodeGen/X86/sar_fold64.ll | 46 + test/CodeGen/X86/seh-catchpad.ll | 5 +- test/CodeGen/X86/seh-no-invokes.ll | 76 + test/CodeGen/X86/select-with-and-or.ll | 167 +- test/CodeGen/X86/select.ll | 610 +- test/CodeGen/X86/select_const.ll | 114 +- test/CodeGen/X86/select_meta.ll | 16 + test/CodeGen/X86/setcc.ll | 82 +- test/CodeGen/X86/sext-i1.ll | 155 +- test/CodeGen/X86/shift-combine.ll | 130 +- test/CodeGen/X86/shift-double.ll | 17 +- test/CodeGen/X86/shift-i128.ll | 55 + test/CodeGen/X86/shl-crash-on-legalize.ll | 33 + test/CodeGen/X86/shrink-compare.ll | 6 +- test/CodeGen/X86/shrink_vmul_sse.ll | 47 + test/CodeGen/X86/splat-for-size.ll | 16 +- test/CodeGen/X86/split-store.ll | 59 + test/CodeGen/X86/sqrt-fastmath-mir.ll | 4 +- test/CodeGen/X86/sqrt-fastmath-tune.ll | 57 + test/CodeGen/X86/sqrt-fastmath.ll | 246 +- test/CodeGen/X86/sse-fcopysign.ll | 6 +- test/CodeGen/X86/sse-fsignum.ll | 34 +- test/CodeGen/X86/sse-intel-ocl.ll | 2 +- test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 20 +- test/CodeGen/X86/sse-regcall.ll | 207 + test/CodeGen/X86/sse-scalar-fp-arith.ll | 48 +- test/CodeGen/X86/sse1.ll | 187 +- test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/sse2-intrinsics-x86.ll | 52 + test/CodeGen/X86/sse2.ll | 8 +- test/CodeGen/X86/sse3-avx-addsub-2.ll | 14 +- test/CodeGen/X86/sse41-pmovxrm.ll | 5 +- test/CodeGen/X86/sse41.ll | 3 +- test/CodeGen/X86/sse4a.ll | 145 +- test/CodeGen/X86/sse_partial_update.ll | 4 +- test/CodeGen/X86/stack-folding-fp-avx1.ll | 151 +- test/CodeGen/X86/stack-folding-fp-avx512.ll | 500 ++ test/CodeGen/X86/stack-folding-fp-avx512vl.ll | 361 +- test/CodeGen/X86/stack-folding-fp-sse42.ll | 113 +- test/CodeGen/X86/stack-folding-int-avx512.ll | 395 + test/CodeGen/X86/stack-folding-int-avx512vl.ll | 440 + test/CodeGen/X86/stack-protector.ll | 23 +- test/CodeGen/X86/stackmap-fast-isel.ll | 6 +- test/CodeGen/X86/stackmap-large-constants.ll | 4 +- test/CodeGen/X86/stackmap-liveness.ll | 4 +- test/CodeGen/X86/stackmap.ll | 18 +- test/CodeGen/X86/statepoint-allocas.ll | 5 +- test/CodeGen/X86/statepoint-live-in.ll | 131 + test/CodeGen/X86/statepoint-stackmap-format.ll | 6 +- test/CodeGen/X86/subvector-broadcast.ll | 1341 +++ test/CodeGen/X86/swift-return.ll | 171 +- test/CodeGen/X86/swifterror.ll | 331 +- test/CodeGen/X86/system-intrinsics-xgetbv.ll | 21 + test/CodeGen/X86/system-intrinsics-xsetbv.ll | 23 + test/CodeGen/X86/tail-call-conditional.mir | 84 + test/CodeGen/X86/tail-call-win64.ll | 2 +- test/CodeGen/X86/tail-dup-merge-loop-headers.ll | 190 + test/CodeGen/X86/tail-dup-repeat.ll | 53 + test/CodeGen/X86/tail-merge-after-mbp.ll | 94 + test/CodeGen/X86/tailcall-cgp-dup.ll | 20 + test/CodeGen/X86/taildup-crash.ll | 24 + test/CodeGen/X86/trunc-store.ll | 16 +- test/CodeGen/X86/twoaddr-lea.ll | 57 + test/CodeGen/X86/uint64-to-float.ll | 55 +- test/CodeGen/X86/uint_to_fp-3.ll | 71 + test/CodeGen/X86/update-terminator.mir | 22 + test/CodeGen/X86/v8i1-masks.ll | 4 +- test/CodeGen/X86/vec-copysign.ll | 169 + test/CodeGen/X86/vec-trunc-store.ll | 21 +- test/CodeGen/X86/vec3.ll | 32 + test/CodeGen/X86/vec_ctbits.ll | 61 +- test/CodeGen/X86/vec_extract-avx.ll | 4 +- test/CodeGen/X86/vec_extract.ll | 8 +- test/CodeGen/X86/vec_fabs.ll | 209 +- test/CodeGen/X86/vec_fp_to_int.ll | 1306 ++- test/CodeGen/X86/vec_fptrunc.ll | 59 +- test/CodeGen/X86/vec_insert-5.ll | 10 +- test/CodeGen/X86/vec_int_to_fp.ll | 1643 ++-- test/CodeGen/X86/vec_minmax_match.ll | 118 + test/CodeGen/X86/vec_ss_load_fold.ll | 345 +- test/CodeGen/X86/vec_uint_to_fp-fastmath.ll | 26 +- test/CodeGen/X86/vector-bitreverse.ll | 6 +- test/CodeGen/X86/vector-blend.ll | 12 +- test/CodeGen/X86/vector-compare-results.ll | 4 - test/CodeGen/X86/vector-half-conversions.ll | 2931 +++---- test/CodeGen/X86/vector-idiv-sdiv-128.ll | 7 +- test/CodeGen/X86/vector-idiv-sdiv-256.ll | 4 +- test/CodeGen/X86/vector-idiv-sdiv-512.ll | 2 +- test/CodeGen/X86/vector-idiv-udiv-128.ll | 7 +- test/CodeGen/X86/vector-idiv-udiv-256.ll | 4 +- test/CodeGen/X86/vector-idiv-udiv-512.ll | 2 +- test/CodeGen/X86/vector-interleave.ll | 151 + test/CodeGen/X86/vector-lzcnt-128.ll | 850 +- test/CodeGen/X86/vector-lzcnt-256.ll | 649 +- test/CodeGen/X86/vector-rem.ll | 8 +- test/CodeGen/X86/vector-sext.ll | 690 +- test/CodeGen/X86/vector-shift-ashr-512.ll | 1047 ++- test/CodeGen/X86/vector-shift-lshr-512.ll | 1046 ++- test/CodeGen/X86/vector-shift-shl-512.ll | 1046 ++- test/CodeGen/X86/vector-shuffle-128-v16.ll | 292 +- test/CodeGen/X86/vector-shuffle-128-v2.ll | 83 +- test/CodeGen/X86/vector-shuffle-128-v4.ll | 281 +- test/CodeGen/X86/vector-shuffle-128-v8.ll | 362 +- test/CodeGen/X86/vector-shuffle-256-v16.ll | 1385 ++- test/CodeGen/X86/vector-shuffle-256-v32.ll | 1014 ++- test/CodeGen/X86/vector-shuffle-256-v4.ll | 117 +- test/CodeGen/X86/vector-shuffle-256-v8.ll | 914 +- test/CodeGen/X86/vector-shuffle-512-v16.ll | 49 +- test/CodeGen/X86/vector-shuffle-512-v32.ll | 83 + test/CodeGen/X86/vector-shuffle-512-v64.ll | 258 + test/CodeGen/X86/vector-shuffle-512-v8.ll | 214 +- test/CodeGen/X86/vector-shuffle-combining-avx.ll | 359 +- test/CodeGen/X86/vector-shuffle-combining-avx2.ll | 543 +- .../X86/vector-shuffle-combining-avx512bw.ll | 1043 ++- .../X86/vector-shuffle-combining-avx512bwvl.ll | 76 + test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 172 +- test/CodeGen/X86/vector-shuffle-combining-xop.ll | 318 +- test/CodeGen/X86/vector-shuffle-combining.ll | 132 +- test/CodeGen/X86/vector-shuffle-sse1.ll | 4 +- test/CodeGen/X86/vector-shuffle-sse4a.ll | 8 +- test/CodeGen/X86/vector-shuffle-v1.ll | 55 +- test/CodeGen/X86/vector-shuffle-variable-256.ll | 3 +- test/CodeGen/X86/vector-trunc-math.ll | 470 +- test/CodeGen/X86/vector-trunc.ll | 555 +- test/CodeGen/X86/vector-tzcnt-128.ll | 591 +- test/CodeGen/X86/vector-tzcnt-256.ll | 403 +- test/CodeGen/X86/vector-tzcnt-512.ll | 1 - test/CodeGen/X86/vector-zext.ll | 445 +- test/CodeGen/X86/viabs.ll | 373 +- test/CodeGen/X86/vselect-2.ll | 36 +- test/CodeGen/X86/vselect-avx.ll | 172 +- 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