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from 1c340c62058 [RISCV] Support stack offset exceed 32-bit for RV64 new 259954721b5 AMDGPU/GlobalISel: Select 16-bit VALU bit ops new 68c7c7683b3 AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
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Summary of changes: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 7 +++++++ lib/Target/AMDGPU/VOP2Instructions.td | 6 +++--- test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 11 +++++------ test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 11 +++++------ test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 11 +++++------ .../AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir | 18 ++++++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir | 17 +++++++++++++++++ 7 files changed, 60 insertions(+), 21 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir