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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from 81ceb36b96 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds a44da25aa6 target/riscv: Update the ePMP CSR address adds 15732b8ed2 target/riscv: Fix satp write adds 0f0b70eeec target/riscv: Expose interrupt pending bits as GPIO lines adds a714b8aa02 hw/intc: sifive_clint: Use RISC-V CPU GPIO lines adds e5cc6aaeb5 hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds f436ecc315 hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds 57a3a62265 hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines adds 5bf6f1acdd hw/timer: Add SiFive PWM support adds ea6eaa0604 sifive_u: Connect the SiFive PWM device adds cc63a18282 hw/intc: Rename sifive_clint sources to riscv_aclint sources adds b8fb878aa2 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT adds 0ffc1a9522 hw/riscv: virt: Re-factor FDT generation adds 954886ea6d hw/riscv: virt: Add optional ACLINT support to virt machine adds de7c7988d2 hw/dma: sifive_pdma: reset Next* registers when Control.clai [...] adds 9a8c26c08c hw/dma: sifive_pdma: claim bit must be set before DMA transactions adds e22d90f5f9 hw/dma: sifive_pdma: allow non-multiple transaction size tra [...] adds ae000c5f65 hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer adds 758c07c9fc docs/system/riscv: sifive_u: Update U-Boot instructions adds c601354756 target/riscv: Backup/restore mstatus.SD bit when virtual reg [...] adds db70794ea8 target/riscv: csr: Rename HCOUNTEREN_CY and friends adds ed481d9837 hw/riscv: opentitan: Correct the USB Dev address adds 2c3e83f92d Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...]
No new revisions were added by this update.
Summary of changes: docs/system/riscv/sifive_u.rst | 50 +- docs/system/riscv/virt.rst | 10 + hw/dma/sifive_pdma.c | 54 +- hw/intc/Kconfig | 2 +- hw/intc/ibex_plic.c | 17 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 460 +++++++++++++++ hw/intc/sifive_clint.c | 287 --------- hw/intc/sifive_plic.c | 30 +- hw/riscv/Kconfig | 13 +- hw/riscv/microchip_pfsoc.c | 13 +- hw/riscv/opentitan.c | 13 +- hw/riscv/shakti_c.c | 16 +- hw/riscv/sifive_e.c | 15 +- hw/riscv/sifive_u.c | 68 ++- hw/riscv/spike.c | 16 +- hw/riscv/virt.c | 654 ++++++++++++++------- hw/timer/Kconfig | 3 + hw/timer/ibex_timer.c | 17 +- hw/timer/meson.build | 1 + hw/timer/sifive_pwm.c | 468 +++++++++++++++ hw/timer/trace-events | 6 + include/hw/intc/ibex_plic.h | 2 + include/hw/intc/riscv_aclint.h | 80 +++ include/hw/intc/sifive_clint.h | 60 -- include/hw/intc/sifive_plic.h | 4 + include/hw/riscv/sifive_u.h | 14 +- include/hw/riscv/virt.h | 2 + include/hw/timer/ibex_timer.h | 2 + .../stm32f4xx_syscfg.h => timer/sifive_pwm.h} | 48 +- target/riscv/cpu.c | 31 + target/riscv/cpu_bits.h | 12 +- target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 26 +- 34 files changed, 1807 insertions(+), 692 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 hw/timer/sifive_pwm.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h copy include/hw/{misc/stm32f4xx_syscfg.h => timer/sifive_pwm.h} (60%)