[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (f6929c01952 -> 45a4f34bd19)

23 Dec 2020


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig
in repository toolchain/ci/llvm-project.
from  f6929c01952 [SLP] add reduction tests for maxnum/minnum intrinsics; NFC
      adds  3dbe471a260 [clangd] Use atomics instead of locks to track periodic mem [...]
      adds  df6cbd37f57 [mlir] Lower gpu.memcpy to GPU runtime calls.
      adds  f7a26127f21 [clangd] Release notes for b8c37153d5393aad96
      adds  a781a706b96 [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
      adds  8de43b926f0 [mlir] Remove instance methods from LLVMType
      adds  1c19804ebf4 [OpenMP] Add OpenMP Documentation for Libomptarget environm [...]
      adds  75a3f326c3d [IR] Add an ImplicitLocOpBuilder helper class for building  [...]
      adds  6dfe5801e01 scudo: Move the configuration for the primary allocator to  [...]
      adds  ca4bf58e4ee [AMDGPU] Support unaligned flat scratch in TLI
      adds  d15119a02d9 [AMDGPU][GlobalISel] GlobalISel for flat scratch
      adds  e6b3db6309f scudo: Replace the Cache argument on MapAllocator with a Co [...]
      adds  faac1c02c80 scudo: Move the management of the UseMemoryTagging bit out  [...]
      adds  22cf54a7fba Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it  [...]
      adds  5bec0828347 VirtRegMap: Use Register
      adds  29ed846d671 AMDGPU: Fix assert when checking for implicit operand legality
      adds  c8874464b5f [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down  [...]
      adds  42687839980 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions
      adds  ad0a7ad950f [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf [...]
      adds  bac54639c7b AMDGPU: Add spilled CSR SGPRs to entry block live ins
      adds  8bf9cdeaee4 AMDGPU: Use Register
      adds  77fb45e59e4 [lld/mac] Add --version flag
      adds  581d13f8aeb GlobalISel: Return APInt from getConstantVRegVal
      adds  e6fde1ae7df [MemorySSA] Use is_contained (NFC)
      adds  efe7f5ede0b [WebAssembly][NFC] Refactor SIMD load/store tablegen defs
      adds  3c707d73f26 [NewGVN] Remove for_each_found (NFC)
      adds  0219cf7dfaf [NewPM] Fix objc-arc-apelim pass typo
      adds  4d479443934 [RISCV] Define the vfmin, vfmax RVV intrinsics
      adds  032600b9aef [RISCV] Define vmerge/vfmerge intrinsics.
      adds  bdef1f87aba [llvm-readobj] - Dump the ELF file type better.
      adds  6301871d06d [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwn [...]
      adds  221fdedc692 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses
      adds  65ba0cd3955 [mlir] Modernize std-to-llvm operation conversion doc
      adds  8451d4872ed [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All  [...]
      adds  32a884c9c52 [mlir] Add translation of omp.wsloop to LLVM IR
      adds  19a0d0a40ce [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() [...]
      adds  25a02c3d1a6 Revert "PR24076, PR33655, C++ CWG 1558: Consider the instan [...]
      adds  eb9483b2105 [format] Add overload to parseConfiguration that accept llv [...]
      adds  7ed9cfc7b19 [mlir] Remove static constructors from LLVMType
      adds  c3acda0798f [VE] Vector 'and' isel and tests
      adds  acaa6e4260c [NFC] Uniquify 'const' in TargetTransformInfoImpl.h
      adds  a9f14cdc620 [ARM] Add bank conflict hazarding
      adds  6e603464959 [OpenMP] Fixing Typo in Documentation
      adds  5426b2f9ed9 [clang-format] PR48535 clang-format Incorrectly Removes Spa [...]
      adds  031743cb5b3 [clang-format] PR48539 ReflowComments breaks Qt translation [...]
      adds  1d0dc9be6d7 [MLIR][SPIRV] Add rewrite pattern to convert select+cmp int [...]
      adds  2522fa053b6 [clangd] Do not take stale definition from the static index.
      adds  9fb074e7bb1 [BPI] Improve static heuristics for "cold" paths.
      adds  e122a71a0a2 [TableGen] Add the !substr() bang operator
      adds  9d1140e18e6 [lld-macho] Simulator & DriverKit executables should always be PIE
      adds  631501b1f90 [OpenMP] Fixing typo on memory size in Documenation
      adds  7ad666798f1 Revert 741978d727 and things that landed on top of it.
      adds  42980a789d2 [mlir][spirv] Convert functions returning one value
      adds  fcf9479f7d6 [lldb] Don't instrument demangling.
      adds  a9448872fec [lldb] Refactor and simplify GetCommandSPExact interface
      adds  e0110a47402 [RISCV] Add intrinsics for vfmv.v.f
      adds  b920adf3b4f This is a test commit
      adds  3b3a9d24188 Updated GettingInvolved.md to reflect Flang Biweekly Call changes
      adds  b1191c84380 [IROutliner] Adding support for elevating constants that ar [...]
      adds  bbd758a7913 Revert "This is a test commit"
      adds  1876a2914fe Revert more changes that landed on top of 741978d727
      adds  74186880ba9 [mlir][vector] Add more vector Ops canonicalization
      adds  4c37453a04f clang: Build and run FrontendTests with CLANG_ENABLE_STATIC [...]
      adds  e1248447092 [LoopIdiom] Introduce 'left-shift until bittest' idiom
      adds  cb2e5980bae [LoopIdiom] 'left-shift until bittest' idiom: support const [...]
      adds  a0ddc61c5b9 [LoopIdiom] 'left-shift until bittest' idiom: support canon [...]
      adds  2b61e7c68cd [LoopIdiom] 'left-shift until bittest' idiom: support rewri [...]
      adds  a16fbff17d3 [mlir][spirv] Create a pass for testing SCFToSPIRV patterns
      adds  34e70d722df Append ".__part." to every basic block section symbol.
      adds  930c74f12d7 [mlir][spirv] NFC: rename SPIR-V conversion files for consistency
      adds  897990e614c [IROutliner] Use isa instead of dyn_cast where the casted v [...]
      adds  ae895ac4b9f [mlir][spirv] De-template deserialization
      adds  fc41777702a [mlir][spirv] De-template serialization
      adds  de127d83d81 [InstCombine] Add tests for PR48577 (NFC)
      adds  899faa50f20 [InstCombine] Check inbounds in load/store of gep null tran [...]
      adds  1a7ac29a89f [RISCV] Add ISel support for RVV vector/scalar forms
      adds  c7e825b910a [format][NFC] Use unsigned char as the base of all enums in [...]
      adds  87087a02ae4 [InstCombine] Add tests for gep of null (NFC)
      adds  eb79fd3c928 [InstCombine] Fold gep inbounds of null to null
      adds  759b8c11c39 [InstCombine] Handle different pointer types when folding g [...]
      adds  cce473e0c56 [IRSim] Adding commutativity matching to structure checking
      adds  05039266024 [IRSim] Adding support for isomorphic predicates
      adds  f8079355c60 [InstCombine] canonicalizeAbsNabs(): don't propagate NSW fl [...]
      adds  374f1d81feb [clang-format] Fix handling of TextProto comments
      adds  47877c9079c [clang-format] Add SpaceBeforeCaseColon option
       new  45a4f34bd19 Revert "[IRSim] Adding support for isomorphic predicates"
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 clang-tools-extra/clangd/ClangdLSPServer.cpp       |   37 +-
 clang-tools-extra/clangd/ClangdLSPServer.h         |   11 +-
 clang-tools-extra/clangd/index/Merge.cpp           |    6 +
 clang-tools-extra/clangd/support/Threading.cpp     |   12 +
 clang-tools-extra/clangd/support/Threading.h       |   29 +
 clang-tools-extra/clangd/unittests/IndexTests.cpp  |   34 +
 .../clangd/unittests/support/ThreadingTests.cpp    |   21 +
 clang-tools-extra/docs/ReleaseNotes.rst            |   12 +-
 clang/docs/ClangFormatStyleOptions.rst             |   10 +
 clang/docs/ReleaseNotes.rst                        |    3 +
 clang/docs/tools/dump_format_style.py              |    2 +-
 clang/include/clang/AST/Type.h                     |    4 +-
 clang/include/clang/Basic/CodeGenOptions.h         |    2 -
 clang/include/clang/Basic/DiagnosticDriverKinds.td |    2 +
 .../include/clang/Basic/DiagnosticFrontendKinds.td |    2 +
 clang/include/clang/Driver/Options.td              | 1362 ++++++----------
 clang/include/clang/Format/Format.h                |   81 +-
 clang/lib/AST/ItaniumMangle.cpp                    |    4 -
 clang/lib/CodeGen/CGCall.h                         |    6 +-
 clang/lib/Format/BreakableToken.cpp                |   13 +-
 clang/lib/Format/Format.cpp                        |   18 +-
 clang/lib/Format/TokenAnnotator.cpp                |   15 +-
 clang/lib/Frontend/CompilerInvocation.cpp          |  902 +++++++++--
 clang/test/CXX/drs/dr15xx.cpp                      |   14 -
 clang/test/CodeGen/basic-block-sections.c          |   10 +-
 clang/test/CodeGenCXX/mangle-template.cpp          |   20 -
 clang/test/Format/error-config.cpp                 |    4 +-
 clang/test/Profile/c-generate.c                    |    2 +-
 .../test/SemaTemplate/instantiation-dependence.cpp |   74 -
 .../test/SemaTemplate/partial-spec-instantiate.cpp |   18 +-
 clang/unittests/CMakeLists.txt                     |    2 +-
 clang/unittests/Format/FormatTest.cpp              |  135 ++
 clang/unittests/Format/FormatTestComments.cpp      |    6 +
 clang/unittests/Format/FormatTestTextProto.cpp     |   16 +-
 .../unittests/Frontend/CompilerInvocationTest.cpp  |   84 +-
 clang/www/cxx_dr_status.html                       |    2 +-
 .../lib/scudo/standalone/allocator_config.h        |   51 +-
 compiler-rt/lib/scudo/standalone/combined.h        |   32 +-
 compiler-rt/lib/scudo/standalone/memtag.h          |    5 +
 compiler-rt/lib/scudo/standalone/options.h         |    6 +
 compiler-rt/lib/scudo/standalone/primary32.h       |   32 +-
 compiler-rt/lib/scudo/standalone/primary64.h       |   35 +-
 compiler-rt/lib/scudo/standalone/secondary.h       |   14 +-
 .../lib/scudo/standalone/tests/combined_test.cpp   |   25 +-
 .../lib/scudo/standalone/tests/primary_test.cpp    |   62 +-
 .../lib/scudo/standalone/tests/secondary_test.cpp  |   20 +-
 flang/docs/GettingInvolved.md                      |    6 +-
 lld/COFF/Options.td                                |    2 +-
 lld/MachO/Driver.cpp                               |   40 +-
 lld/MachO/Options.td                               |    4 +-
 lld/test/ELF/lto/basic-block-sections.ll           |    8 +-
 lld/test/MachO/driver.test                         |    4 +-
 lld/test/MachO/platform-version.s                  |    2 +-
 lld/test/MachO/x86-64-reloc-unsigned.s             |    4 +
 lldb/include/lldb/Interpreter/CommandInterpreter.h |    2 +-
 lldb/source/Commands/CommandObjectCommands.cpp     |    7 +-
 lldb/source/Core/Mangled.cpp                       |    9 -
 lldb/source/Interpreter/CommandInterpreter.cpp     |  139 +-
 llvm/docs/TableGen/ProgRef.rst                     |   10 +-
 llvm/include/llvm/Analysis/BranchProbabilityInfo.h |  153 +-
 .../include/llvm/Analysis/IRSimilarityIdentifier.h |   15 +-
 .../llvm/Analysis/LazyBranchProbabilityInfo.h      |    2 +-
 .../llvm/Analysis/TargetTransformInfoImpl.h        |  196 ++-
 .../llvm/CodeGen/GlobalISel/MIPatternMatch.h       |    2 +-
 llvm/include/llvm/CodeGen/GlobalISel/Utils.h       |   11 +-
 llvm/include/llvm/CodeGen/VirtRegMap.h             |    8 +-
 llvm/include/llvm/IR/IntrinsicsRISCV.td            |   53 +-
 llvm/include/llvm/IR/SymbolTableListTraits.h       |    8 +-
 llvm/include/llvm/Object/Binary.h                  |    4 +-
 llvm/include/llvm/Option/OptParser.td              |   18 +-
 llvm/include/llvm/TableGen/Record.h                |    2 +-
 llvm/include/llvm/Transforms/IPO/IROutliner.h      |   13 +-
 llvm/lib/Analysis/BranchProbabilityInfo.cpp        |  645 ++++----
 llvm/lib/Analysis/IRSimilarityIdentifier.cpp       |  149 +-
 llvm/lib/Analysis/MemorySSA.cpp                    |    3 +-
 llvm/lib/Analysis/OptimizationRemarkEmitter.cpp    |    2 +-
 llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp     |    7 +-
 llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp     |   28 +-
 .../lib/CodeGen/GlobalISel/InstructionSelector.cpp |    2 +-
 llvm/lib/CodeGen/GlobalISel/Utils.cpp              |   30 +-
 llvm/lib/CodeGen/LiveRangeEdit.cpp                 |    2 +-
 llvm/lib/CodeGen/MachineBasicBlock.cpp             |    5 +-
 llvm/lib/Object/COFFObjectFile.cpp                 |   24 +-
 llvm/lib/Object/ELFObjectFile.cpp                  |    3 +-
 llvm/lib/Object/XCOFFObjectFile.cpp                |    4 +-
 llvm/lib/Passes/PassRegistry.def                   |    2 +-
 llvm/lib/TableGen/Record.cpp                       |   28 +-
 llvm/lib/TableGen/TGLexer.cpp                      |    1 +
 llvm/lib/TableGen/TGLexer.h                        |    6 +-
 llvm/lib/TableGen/TGParser.cpp                     |   95 +-
 llvm/lib/TableGen/TGParser.h                       |    1 +
 .../AArch64/GISel/AArch64InstructionSelector.cpp   |   47 +-
 .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp  |    2 +-
 .../AArch64/GISel/AArch64PostLegalizerCombiner.cpp |    2 +-
 .../AArch64/GISel/AArch64PostLegalizerLowering.cpp |    2 +-
 llvm/lib/Target/AMDGPU/AMDGPUGISel.td              |    8 +
 .../Target/AMDGPU/AMDGPUInstructionSelector.cpp    |   97 +-
 llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |    3 +
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |   26 +-
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |    2 +-
 llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp         |    8 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp          |   15 +-
 llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp       |   19 +-
 llvm/lib/Target/ARM/ARM.td                         |    4 +-
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp           |   25 +
 llvm/lib/Target/ARM/ARMBaseInstrInfo.h             |    4 +
 llvm/lib/Target/ARM/ARMHazardRecognizer.cpp        |  173 ++
 llvm/lib/Target/ARM/ARMHazardRecognizer.h          |   32 +
 llvm/lib/Target/ARM/ARMSubtarget.cpp               |    1 +
 llvm/lib/Target/ARM/ARMSubtarget.h                 |    2 +
 llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp       |    9 +-
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp        |   46 +
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h          |    3 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp        |   57 +
 llvm/lib/Target/RISCV/RISCVISelLowering.h          |    4 +
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td    |  293 +++-
 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td |  166 ++
 llvm/lib/Target/VE/VVPInstrInfo.td                 |    3 +
 llvm/lib/Target/VE/VVPInstrPatternsVec.td          |    3 +
 llvm/lib/Target/VE/VVPNodes.def                    |    1 +
 .../MCTargetDesc/WebAssemblyMCTargetDesc.h         |   40 +-
 .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td |  322 ++--
 llvm/lib/Target/X86/X86InstructionSelector.cpp     |    2 +-
 llvm/lib/Transforms/IPO/IROutliner.cpp             |  209 ++-
 .../InstCombine/InstCombineLoadStoreAlloca.cpp     |   24 +-
 .../Transforms/InstCombine/InstCombineSelect.cpp   |    7 +-
 .../InstCombine/InstructionCombining.cpp           |    7 +
 llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp  |  326 +++-
 llvm/lib/Transforms/Scalar/LoopPredication.cpp     |    2 +-
 llvm/lib/Transforms/Scalar/NewGVN.cpp              |   12 -
 .../Analysis/BlockFrequencyInfo/redundant_edges.ll |    2 +-
 llvm/test/Analysis/BranchProbabilityInfo/basic.ll  |   40 +-
 .../BranchProbabilityInfo/deopt-intrinsic.ll       |    4 +-
 .../Analysis/BranchProbabilityInfo/deopt-invoke.ll |  107 ++
 llvm/test/Analysis/BranchProbabilityInfo/loop.ll   |  209 ++-
 .../Analysis/BranchProbabilityInfo/noreturn.ll     |   35 +-
 .../Analysis/BranchProbabilityInfo/unreachable.ll  |  154 ++
 .../irtranslator-invoke-probabilities.ll           |    2 +-
 .../GlobalISel/extractelement-stack-lower.ll       | 1675 +++++++++++---------
 .../CodeGen/AMDGPU/GlobalISel/extractelement.ll    |   16 +-
 .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll |  749 +++++++++
 .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll    |  260 ++-
 .../GlobalISel/llvm.amdgcn.global.atomic.fadd.ll   |   30 +-
 .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll  |   89 +-
 llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll         |   11 +-
 .../CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir     |   35 +
 llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir    |   16 +
 .../transform-block-with-return-to-epilog.ll       |    4 +-
 llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll   |   69 +-
 llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll   |    2 +-
 llvm/test/CodeGen/ARM/sub-cmp-peephole.ll          |    2 +-
 .../CodeGen/ARM/v8m.base-jumptable_alignment.ll    |   22 +-
 llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll        |  182 +--
 llvm/test/CodeGen/PowerPC/pr36292.ll               |    5 +-
 llvm/test/CodeGen/PowerPC/sms-cpy-1.ll             |    1 +
 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll    |  822 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll    |  794 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll         |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll         | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll         |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll         | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll          |  881 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll          | 1201 ++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll        |  441 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll        |  601 +++++++
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll          |  881 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll          | 1201 ++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll         |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll         | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll         |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll         | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll       |  421 +++++
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll       |  421 +++++
 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll        |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll        | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll        |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll        | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll        |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll        | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll        |  856 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll        | 1142 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll   |  512 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll   |  698 ++++++++
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll     |  523 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll     |  713 +++++++++
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll        |  482 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll        |  868 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll        |  482 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll        |  868 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll       |  482 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll       |  868 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll       |  482 ++++++
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll       |  868 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll         |  973 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll         | 1189 ++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll     | 1109 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll     | 1081 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll    |  845 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll    |  817 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll    |  800 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll    |  978 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll      |   24 +
 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll      | 1000 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll         |  266 ++++
 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll    |  845 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll    |  817 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll         | 1034 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll         | 1412 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll       | 1034 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll       | 1412 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll        | 1034 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll        | 1412 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll       |  516 ++++++
 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll       |  704 ++++++++
 llvm/test/CodeGen/SPARC/missinglabel.ll            |    2 +-
 llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir       |    4 +-
 llvm/test/CodeGen/Thumb2/schedm7-hazard.ll         |   38 +
 llvm/test/CodeGen/VE/Vector/vec_and.ll             |  132 ++
 llvm/test/CodeGen/WebAssembly/simd-build-vector.ll |    6 +-
 llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll   |   10 +-
 llvm/test/CodeGen/WebAssembly/simd-load-splat.ll   |    2 +-
 .../WebAssembly/simd-load-store-alignment.ll       |   36 +-
 .../CodeGen/WebAssembly/simd-nested-shuffles.ll    |    2 +-
 llvm/test/CodeGen/WebAssembly/simd-offset.ll       |   96 +-
 .../WebAssembly/simd-shift-complex-splats.ll       |    2 +-
 .../CodeGen/WebAssembly/simd-shuffle-bitcast.ll    |    2 +-
 llvm/test/CodeGen/WebAssembly/simd.ll              |   48 +-
 .../WebAssembly/switch-unreachable-default.ll      |    4 +-
 llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll   |   19 +-
 .../X86/basic-block-sections-blockaddress-taken.ll |    4 +-
 .../X86/basic-block-sections-clusters-branches.ll  |    8 +-
 .../X86/basic-block-sections-clusters-eh.ll        |    4 +-
 .../CodeGen/X86/basic-block-sections-clusters.ll   |    8 +-
 .../X86/basic-block-sections-directjumps.ll        |   14 +-
 llvm/test/CodeGen/X86/basic-block-sections-eh.ll   |    4 +-
 llvm/test/CodeGen/X86/basic-block-sections-list.ll |   16 +-
 .../CodeGen/X86/basic-block-sections-listbb.ll     |    4 +-
 .../CodeGen/X86/basic-block-sections-mir-parse.mir |    6 +-
 .../X86/basic-block-sections-unreachable.ll        |    2 +-
 llvm/test/CodeGen/X86/basic-block-sections.ll      |   12 +-
 llvm/test/CodeGen/X86/basic-block-sections_2.ll    |   61 +
 llvm/test/CodeGen/X86/block-placement.ll           |    4 +-
 .../test/CodeGen/X86/cfi-basic-block-sections-1.ll |    8 +-
 ...r-basic-block-sections-callee-save-registers.ll |    4 +-
 .../CodeGen/X86/gcc_except_table_bb_sections.ll    |   22 +-
 .../CodeGen/X86/misched_phys_reg_assign_order.ll   |    6 +-
 llvm/test/CodeGen/X86/pr27501.ll                   |   10 +-
 llvm/test/CodeGen/X86/pr37916.ll                   |    2 +-
 llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll      |  117 +-
 llvm/test/DebugInfo/X86/basic-block-sections_1.ll  |   24 +-
 llvm/test/MC/Disassembler/WebAssembly/wasm.txt     |    2 +-
 llvm/test/MC/WebAssembly/simd-encodings.s          |   24 +-
 llvm/test/Object/elf-unknown-type.test             |   10 -
 llvm/test/TableGen/substr.td                       |   81 +
 .../IROutliner/outlining-commutative-fp.ll         |  107 ++
 .../Transforms/IROutliner/outlining-commutative.ll |  254 +++
 .../IROutliner/outlining-constants-vs-registers.ll |   42 +-
 .../IROutliner/outlining-different-constants.ll    |   24 +-
 .../IROutliner/outlining-different-globals.ll      |   14 +-
 llvm/test/Transforms/InstCombine/abs-1.ll          |    6 +-
 llvm/test/Transforms/InstCombine/abs_abs.ll        |  148 +-
 llvm/test/Transforms/InstCombine/getelementptr.ll  |   34 +
 llvm/test/Transforms/InstCombine/load.ll           |   19 +-
 llvm/test/Transforms/InstCombine/select_meta.ll    |    4 +-
 llvm/test/Transforms/InstCombine/store.ll          |   26 +-
 .../test/Transforms/JumpThreading/thread-prob-3.ll |    4 +-
 .../AMDGPU/adjust-alloca-alignment.ll              |   35 +-
 .../LoopIdiom/X86/left-shift-until-bittest.ll      | 1049 ++++++++----
 llvm/test/tools/llvm-readobj/ELF/file-types.test   |   10 +-
 llvm/tools/llvm-readobj/ELFDumper.cpp              |   49 +-
 .../Analysis/IRSimilarityIdentifierTest.cpp        |   44 +-
 llvm/utils/gn/secondary/clang/unittests/BUILD.gn   |    2 +-
 mlir/docs/ConversionToLLVMDialect.md               |  467 ------
 mlir/docs/Dialects/SPIR-V.md                       |    2 +-
 mlir/docs/LLVMDialectMemRefConvention.md           |  439 +++++
 mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp         |   21 +-
 mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp         |   21 +-
 .../{ConvertGPUToSPIRV.h => GPUToSPIRV.h}          |   10 +-
 .../{ConvertGPUToSPIRVPass.h => GPUToSPIRVPass.h}  |   19 +-
 .../mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h  |    4 +-
 .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h   |    4 +-
 mlir/include/mlir/Conversion/Passes.h              |    9 +-
 mlir/include/mlir/Conversion/Passes.td             |   17 +
 .../mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h        |    4 +-
 .../SCFToSPIRVPass.h}                              |   14 +-
 .../{ConvertSPIRVToLLVM.h => SPIRVToLLVM.h}        |    8 +-
 ...{ConvertSPIRVToLLVMPass.h => SPIRVToLLVMPass.h} |   10 +-
 .../StandardToLLVM/ConvertStandardToLLVM.h         |   13 +-
 ...{ConvertStandardToSPIRV.h => StandardToSPIRV.h} |   16 +-
 ...StandardToSPIRVPass.h => StandardToSPIRVPass.h} |   14 +-
 .../{ConvertVectorToSPIRV.h => VectorToSPIRV.h}    |   10 +-
 ...vertVectorToSPIRVPass.h => VectorToSPIRVPass.h} |   12 +-
 mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td        |   32 +-
 mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h       |  182 +--
 mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td        |    9 +-
 mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td      |    5 +
 .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h   |   31 +
 mlir/include/mlir/Dialect/Vector/VectorOps.td      |    1 +
 mlir/include/mlir/IR/ImplicitLocOpBuilder.h        |  123 ++
 .../include/mlir/Target/LLVMIR/ModuleTranslation.h |    3 +
 mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp    |  156 +-
 .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp  |  105 +-
 mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h     |   24 +-
 .../GPUCommon/IndexIntrinsicsOpLowering.h          |   13 +-
 .../Conversion/GPUCommon/OpToFuncCallLowering.h    |   14 +-
 .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp  |    8 +-
 mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt      |    8 +-
 .../{ConvertGPUToSPIRV.cpp => GPUToSPIRV.cpp}      |    7 +-
 ...onvertGPUToSPIRVPass.cpp => GPUToSPIRVPass.cpp} |   15 +-
 .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp |  106 +-
 mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp  |    2 +-
 mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt   |    2 +-
 .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp |    2 +-
 .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp |    2 +-
 mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt      |    5 +-
 mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp      |    5 +-
 .../SCFToSPIRVPass.cpp}                            |   25 +-
 mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt     |    4 +-
 .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp   |   11 +-
 .../{ConvertSPIRVToLLVM.cpp => SPIRVToLLVM.cpp}    |   34 +-
 ...vertSPIRVToLLVMPass.cpp => SPIRVToLLVMPass.cpp} |    6 +-
 .../Conversion/StandardToLLVM/StandardToLLVM.cpp   |  263 +--
 mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt |    6 +-
 .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp   |    4 +-
 ...vertStandardToSPIRV.cpp => StandardToSPIRV.cpp} |   12 +-
 ...dardToSPIRVPass.cpp => StandardToSPIRVPass.cpp} |    9 +-
 .../VectorToLLVM/ConvertVectorToLLVM.cpp           |   48 +-
 .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp |   10 +-
 mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt   |    1 +
 .../lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp |   43 +-
 .../VectorToSPIRVPass.cpp}                         |   33 +-
 mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp         |  248 +--
 mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp           |  283 +---
 mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp         |   22 +-
 mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp        |   12 +-
 mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt           |    1 +
 mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td |   30 +
 .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp |   35 +
 .../Dialect/SPIRV/Transforms/SPIRVConversion.cpp   |   12 +-
 mlir/lib/Dialect/Vector/VectorOps.cpp              |   99 +-
 mlir/lib/ExecutionEngine/JitRunner.cpp             |   19 +-
 mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp       |   45 +-
 mlir/lib/Target/LLVMIR/ModuleTranslation.cpp       |  136 +-
 mlir/lib/Target/SPIRV/Deserialization.cpp          |  106 ++
 mlir/lib/Target/SPIRV/Serialization.cpp            |   62 +-
 .../lower-memcpy-to-gpu-runtime-calls.mlir         |   19 +
 ...est_spirv_entry_point.mlir => entry-point.mlir} |    0
 mlir/test/Conversion/GPUToSPIRV/if.mlir            |  167 --
 mlir/test/Conversion/GPUToSPIRV/loop.mlir          |   98 --
 mlir/test/Conversion/SCFToSPIRV/for.mlir           |   86 +
 mlir/test/Conversion/SCFToSPIRV/if.mlir            |  156 ++
 .../StandardToSPIRV/std-ops-to-spirv.mlir          |   26 +
 mlir/test/Dialect/LLVMIR/invalid.mlir              |    8 +-
 .../SPIRV/Transforms/glsl_canonicalize.mlir        |  113 ++
 mlir/test/Dialect/Vector/canonicalize.mlir         |   47 +
 mlir/test/Target/openmp-llvm.mlir                  |   34 +-
 mlir/test/lib/Dialect/SPIRV/CMakeLists.txt         |    1 +
 .../lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp |   39 +
 mlir/test/lib/Transforms/TestConvertCallOp.cpp     |    3 +-
 .../mlir-cuda-runner/cuda-runtime-wrappers.cpp     |    7 +
 mlir/tools/mlir-opt/mlir-opt.cpp                   |    2 +
 .../mlir-rocm-runner/rocm-runtime-wrappers.cpp     |    5 +
 .../mlir-spirv-cpu-runner.cpp                      |    4 +-
 mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp           |   50 +-
 .../mlir-vulkan-runner/mlir-vulkan-runner.cpp      |    4 +-
 openmp/docs/design/Runtimes.rst                    |   82 +
 366 files changed, 62714 insertions(+), 6102 deletions(-)
 delete mode 100644 clang/test/SemaTemplate/instantiation-dependence.cpp
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
 create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
 create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
 create mode 100644 llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
 create mode 100644 llvm/test/CodeGen/VE/Vector/vec_and.ll
 create mode 100644 llvm/test/CodeGen/X86/basic-block-sections_2.ll
 delete mode 100644 llvm/test/Object/elf-unknown-type.test
 create mode 100644 llvm/test/TableGen/substr.td
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative.ll
 create mode 100644 mlir/docs/LLVMDialectMemRefConvention.md
 rename mlir/include/mlir/Conversion/GPUToSPIRV/{ConvertGPUToSPIRV.h => GPUToSPIRV. [...]
 rename mlir/include/mlir/Conversion/GPUToSPIRV/{ConvertGPUToSPIRVPass.h => GPUToSP [...]
 copy mlir/include/mlir/Conversion/{LinalgToSPIRV/LinalgToSPIRVPass.h => SCFToSPIRV [...]
 rename mlir/include/mlir/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVM.h => SPIRVToLL [...]
 rename mlir/include/mlir/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVMPass.h => SPIRV [...]
 rename mlir/include/mlir/Conversion/StandardToSPIRV/{ConvertStandardToSPIRV.h => S [...]
 rename mlir/include/mlir/Conversion/StandardToSPIRV/{ConvertStandardToSPIRVPass.h  [...]
 rename mlir/include/mlir/Conversion/VectorToSPIRV/{ConvertVectorToSPIRV.h => Vecto [...]
 rename mlir/include/mlir/Conversion/VectorToSPIRV/{ConvertVectorToSPIRVPass.h => V [...]
 create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h
 create mode 100644 mlir/include/mlir/IR/ImplicitLocOpBuilder.h
 rename mlir/lib/Conversion/GPUToSPIRV/{ConvertGPUToSPIRV.cpp => GPUToSPIRV.cpp} (98%)
 rename mlir/lib/Conversion/GPUToSPIRV/{ConvertGPUToSPIRVPass.cpp => GPUToSPIRVPass [...]
 copy mlir/lib/Conversion/{StandardToSPIRV/ConvertStandardToSPIRVPass.cpp => SCFToS [...]
 rename mlir/lib/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVM.cpp => SPIRVToLLVM.cpp} (98%)
 rename mlir/lib/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVMPass.cpp => SPIRVToLLVMP [...]
 rename mlir/lib/Conversion/StandardToSPIRV/{ConvertStandardToSPIRV.cpp => Standard [...]
 rename mlir/lib/Conversion/StandardToSPIRV/{ConvertStandardToSPIRVPass.cpp => Stan [...]
 copy mlir/lib/Conversion/{LinalgToSPIRV/LinalgToSPIRVPass.cpp => VectorToSPIRV/Vec [...]
 create mode 100644 mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp
 create mode 100644 mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
 rename mlir/test/Conversion/GPUToSPIRV/{test_spirv_entry_point.mlir => entry-point [...]
 delete mode 100644 mlir/test/Conversion/GPUToSPIRV/if.mlir
 delete mode 100644 mlir/test/Conversion/GPUToSPIRV/loop.mlir
 create mode 100644 mlir/test/Conversion/SCFToSPIRV/for.mlir
 create mode 100644 mlir/test/Conversion/SCFToSPIRV/if.mlir
 create mode 100644 mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir
 create mode 100644 mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp
-- 
To stop receiving notification emails like this one, please contact
the administrator of this repository.

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (f6929c01952 -> 45a4f34bd19)