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from 0b26163a3b0 [LCG] Remove yet another variable only used inside of asserts. new d08104f67e7 [ARM] Add registers to debuginfo MIR test cases.
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Summary of changes: test/DebugInfo/MIR/ARM/split-superreg-complex.mir | 3 ++- test/DebugInfo/MIR/ARM/split-superreg-piece.mir | 7 ++++--- test/DebugInfo/MIR/ARM/split-superreg.mir | 7 ++++--- 3 files changed, 10 insertions(+), 7 deletions(-)