[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-O3_LTO updated (bef9eb84b2f -> aebb4a60522)

This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-O3_LTO in repository toolchain/ci/llvm-project.

from bef9eb84b2f [clang] NFC: Refactor custom class into a lambda in Compile [...] adds 5b37f0d9708 [MCInstrDesc] [TableGen] Reduce size of MCOperandInfo instances. adds ef4dbb2b7a8 [LV] Use ScalarEvolution::getURemExpr to reduce duplication. adds 28b00ba7311 [openacc][openmp][NFC] Fix typo in comments adds 0586f048d79 [RISCV] Basic jump table lowering adds 3e07b0b9d33 [MLIR] Fix lowering of affine operations with return values adds 0955d8df063 [mlir] Add gpu.memcpy op. adds 8eec7294fea [SVE] Lower vector BITREVERSE and BSWAP operations. adds 9a7895dc208 [Flang][openmp][5.0] Add task_reduction clause. adds 8a58f21f5b6 [PowerPC][Power10] Exploit store rightmost vector element i [...] adds 5c1c8443eb7 [lldb] Abstract scoped timer logic behind LLDB_SCOPED_TIMER (NFC) adds be85b3e4324 Fix some misnamed variables in sve-fixed-length-int-minmax.ll. adds 5d10b8ad595 [ADT] Add resize_for_overwrite method to SmallVector. adds f106b281be2 [tests] precommit a test mentioned in review for D93317 adds ac90bbc9cb8 [LoopDeletion] Add test case where outer loop needs to be deleted. adds f5071489ea8 [ADT] Fix some tests after 5d10b8ad adds e17a00fc87b [lldb] Add SBType::IsScopedEnumerationType method adds 1432ae57bf6 [lldb] Add SBType::GetEnumerationIntegerType method adds 612ddc3117c [OpenMP][Docs] Updated the faq about building an OpenMP off [...] adds 85d4a4bcc71 Revert "Fix memory leak complicated non-type template arguments." adds ab7a60eb410 Revert "Fix MSVC "not all control paths return a value" war [...] adds 20802323339 Revert "[c++20] P1907R1: Support for generalized non-type t [...] adds af0dbaaa38f Revert "Following up on PR48517, fix handling of template a [...] adds 34e72a14611 Revert "DR2064: decltype(E) is only a dependent type if E i [...] adds 1aa10ab2e1d Revert "[Flang][openmp][5.0] Add task_reduction clause." adds b2e734d5f46 Revert "[clangd] zap a few warnings" adds 6283d2aa519 Revert "[LLDB] Unbreak the build after recent clang changes" adds a5311d731e1 [clang-tidy] Handle template instantiations in container si [...] adds ae8f4b2178c [AMDGPU] Folding of FI operand with flat scratch adds 333108e8bef Add a llvm.coro.end.async intrinsic adds 9cb748724ef [OpenMP][Docs] Add FAQ entry about math and complex on GPUs adds 1eb082c2ea4 [OpenMP][Docs] Fixed a typo in the doc that can mislead use [...] adds 7b0f9dd79a3 [OpenMP][Docs] Fix Typo adds 53deef9e0b8 [RISCV] Remove unneeded !eq comparing a single bit value to [...] adds 7ec7788ac17 Try to fix build on Windows adds 57ffbe020af glld/mac] Don't add names of unreferenced symbols to string table adds 0d15d4b6f43 [SLP] use operand index abstraction for number of operands adds f6929c01952 [SLP] add reduction tests for maxnum/minnum intrinsics; NFC adds 3dbe471a260 [clangd] Use atomics instead of locks to track periodic mem [...] adds df6cbd37f57 [mlir] Lower gpu.memcpy to GPU runtime calls. adds f7a26127f21 [clangd] Release notes for b8c37153d5393aad96 adds a781a706b96 [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats adds 8de43b926f0 [mlir] Remove instance methods from LLVMType adds 1c19804ebf4 [OpenMP] Add OpenMP Documentation for Libomptarget environm [...] adds 75a3f326c3d [IR] Add an ImplicitLocOpBuilder helper class for building [...] adds 6dfe5801e01 scudo: Move the configuration for the primary allocator to [...] adds ca4bf58e4ee [AMDGPU] Support unaligned flat scratch in TLI adds d15119a02d9 [AMDGPU][GlobalISel] GlobalISel for flat scratch adds e6b3db6309f scudo: Replace the Cache argument on MapAllocator with a Co [...] adds faac1c02c80 scudo: Move the management of the UseMemoryTagging bit out [...] adds 22cf54a7fba Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it [...] adds 5bec0828347 VirtRegMap: Use Register adds 29ed846d671 AMDGPU: Fix assert when checking for implicit operand legality adds c8874464b5f [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down [...] adds 42687839980 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions adds ad0a7ad950f [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf [...] adds bac54639c7b AMDGPU: Add spilled CSR SGPRs to entry block live ins adds 8bf9cdeaee4 AMDGPU: Use Register adds 77fb45e59e4 [lld/mac] Add --version flag adds 581d13f8aeb GlobalISel: Return APInt from getConstantVRegVal adds e6fde1ae7df [MemorySSA] Use is_contained (NFC) adds efe7f5ede0b [WebAssembly][NFC] Refactor SIMD load/store tablegen defs adds 3c707d73f26 [NewGVN] Remove for_each_found (NFC) adds 0219cf7dfaf [NewPM] Fix objc-arc-apelim pass typo adds 4d479443934 [RISCV] Define the vfmin, vfmax RVV intrinsics adds 032600b9aef [RISCV] Define vmerge/vfmerge intrinsics. adds bdef1f87aba [llvm-readobj] - Dump the ELF file type better. adds 6301871d06d [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwn [...] adds 221fdedc692 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses adds 65ba0cd3955 [mlir] Modernize std-to-llvm operation conversion doc adds 8451d4872ed [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All [...] adds 32a884c9c52 [mlir] Add translation of omp.wsloop to LLVM IR adds 19a0d0a40ce [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() [...] adds 25a02c3d1a6 Revert "PR24076, PR33655, C++ CWG 1558: Consider the instan [...] adds eb9483b2105 [format] Add overload to parseConfiguration that accept llv [...] adds 7ed9cfc7b19 [mlir] Remove static constructors from LLVMType adds c3acda0798f [VE] Vector 'and' isel and tests adds acaa6e4260c [NFC] Uniquify 'const' in TargetTransformInfoImpl.h adds a9f14cdc620 [ARM] Add bank conflict hazarding adds 6e603464959 [OpenMP] Fixing Typo in Documentation adds 5426b2f9ed9 [clang-format] PR48535 clang-format Incorrectly Removes Spa [...] adds 031743cb5b3 [clang-format] PR48539 ReflowComments breaks Qt translation [...] adds 1d0dc9be6d7 [MLIR][SPIRV] Add rewrite pattern to convert select+cmp int [...] adds 2522fa053b6 [clangd] Do not take stale definition from the static index. adds 9fb074e7bb1 [BPI] Improve static heuristics for "cold" paths. adds e122a71a0a2 [TableGen] Add the !substr() bang operator adds 9d1140e18e6 [lld-macho] Simulator & DriverKit executables should always be PIE adds 631501b1f90 [OpenMP] Fixing typo on memory size in Documenation adds 7ad666798f1 Revert 741978d727 and things that landed on top of it. adds 42980a789d2 [mlir][spirv] Convert functions returning one value adds fcf9479f7d6 [lldb] Don't instrument demangling. adds a9448872fec [lldb] Refactor and simplify GetCommandSPExact interface adds e0110a47402 [RISCV] Add intrinsics for vfmv.v.f adds b920adf3b4f This is a test commit adds 3b3a9d24188 Updated GettingInvolved.md to reflect Flang Biweekly Call changes adds b1191c84380 [IROutliner] Adding support for elevating constants that ar [...] adds bbd758a7913 Revert "This is a test commit" adds 1876a2914fe Revert more changes that landed on top of 741978d727 adds 74186880ba9 [mlir][vector] Add more vector Ops canonicalization adds 4c37453a04f clang: Build and run FrontendTests with CLANG_ENABLE_STATIC [...] adds e1248447092 [LoopIdiom] Introduce 'left-shift until bittest' idiom adds cb2e5980bae [LoopIdiom] 'left-shift until bittest' idiom: support const [...] adds a0ddc61c5b9 [LoopIdiom] 'left-shift until bittest' idiom: support canon [...] adds 2b61e7c68cd [LoopIdiom] 'left-shift until bittest' idiom: support rewri [...] adds a16fbff17d3 [mlir][spirv] Create a pass for testing SCFToSPIRV patterns adds 34e70d722df Append ".__part." to every basic block section symbol. adds 930c74f12d7 [mlir][spirv] NFC: rename SPIR-V conversion files for consistency adds 897990e614c [IROutliner] Use isa instead of dyn_cast where the casted v [...] adds ae895ac4b9f [mlir][spirv] De-template deserialization adds fc41777702a [mlir][spirv] De-template serialization adds de127d83d81 [InstCombine] Add tests for PR48577 (NFC) adds 899faa50f20 [InstCombine] Check inbounds in load/store of gep null tran [...] adds 1a7ac29a89f [RISCV] Add ISel support for RVV vector/scalar forms adds c7e825b910a [format][NFC] Use unsigned char as the base of all enums in [...] adds 87087a02ae4 [InstCombine] Add tests for gep of null (NFC) adds eb79fd3c928 [InstCombine] Fold gep inbounds of null to null adds 759b8c11c39 [InstCombine] Handle different pointer types when folding g [...] adds cce473e0c56 [IRSim] Adding commutativity matching to structure checking adds 05039266024 [IRSim] Adding support for isomorphic predicates adds f8079355c60 [InstCombine] canonicalizeAbsNabs(): don't propagate NSW fl [...] adds 374f1d81feb [clang-format] Fix handling of TextProto comments adds 47877c9079c [clang-format] Add SpaceBeforeCaseColon option adds 45a4f34bd19 Revert "[IRSim] Adding support for isomorphic predicates" adds 74b3acefc7b [clangd] Fix case mismatch crash on in CDB on windows after [...] adds d97e9f1a3d8 [lldb] Simplify ObjectFile::FindPlugin (NFC) adds 7143923f86b Fix lldb test failure due to D93082. adds be89d7460b6 [lld][test] Relax test assertion of cmake defaults appearin [...] adds 747f67e034a [AMDGPU] Fix adjustWritemask subreg handling adds 245218bb355 Basic: Support named pipes natively in SourceManager and Fi [...] adds 3ee43adfb20 Basic: Add native support for stdin to SourceManager and Fi [...] adds ca1ab0c66d1 [mlir] Add tensor passes to passes.md adds d29f93bda51 [DAGCombiner] Don't create sexts of deleted xors when they [...] adds 69132d12dea [Clang] Reverse test to save on indentation. NFC. adds 48ad8194a56 [IRSim] Adding support for isomorphic predicates adds db7a2f347f1 Precommit transform tests that have poison as insertelement [...] adds 30365472489 Precommit analysis/etc tests for inselt poison placeholder adds 9939cf5a564 [ExecutionEngine, Linker] Use erase_if (NFC) adds 200b15af45a [Analysis] Remove spliceFunction (NFC) adds b8cb1802a8a [obj2yaml] - Dump the content of a broken GNU hash table properly. adds 90177912a4d Revert "[InstCombine] Fold gep inbounds of null to null" adds 61177943c9c [AMDGPU] Use MUBUF instructions for global address space access adds e0751234ef0 [CodeGen] Add "noreturn" attirbute to _Unwind_Resume adds ef2f843347b Revert "[InstCombine] Check inbounds in load/store of gep n [...] adds ce4413e4894 Moved dwarf_eh_resume.ll from Generic to X86 folder adds fb468953082 [Support] Explicitly state that KnownBits::getMinValue/getM [...] adds 6895581fd2c [Support] Add KnownBits::getSignedMinValue/getSignedMaxValu [...] adds 89abe1cf83a [InstCombine] foldICmpUsingKnownBits - use KnownBits signed [...] adds df812115e3c [CodeGen, Transforms] Use llvm::any_of (NFC) adds e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC) adds ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused [...] adds b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...] adds da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test adds 1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern adds 5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y` adds 8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern adds d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value adds 6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...] adds 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() adds b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) adds 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() adds 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) adds e334c52addc [llvm-objcopy] Use llvm::erase_if (NFC) adds 622ea9cf74b [RISCV] Define vector widening reduction intrinsic. adds e8c7e7cdbbb [ValueTracking] Add more known non zero tests (NFC) adds b2184075127 [ValueTracking] Handle more non-trivial conditions in isKno [...] adds c7dcc4c7258 [clang-format] PR48569 clang-format fails to align case lab [...] adds c4ca1089669 [SLP] use switch to improve readability; NFC adds badf0f20f3b [SLP] rename reduction variables for readability; NFC adds 62beac7ed7c [NFC] Refactor some SourceMgr code adds 9c9bca45f09 [llvm-pdbutil] Use llvm::is_contained (NFC) adds 63a2bde2812 [TableGen] Use llvm::erase_if (NFC) adds b676f2fee1f [llvm-cov, llvm-symbolizer] Use llvm::erase_if (NFC) adds 5bc5c016c4b [CVP] Add tests for select form of and/or (NFC) adds 8791949f55b [test] Pin some tests to legacy PM adds 9eb3e564d3b [ODS] Make the getType() method on a OneResult instruction [...] adds 76202f09b52 [RISCV] Improve VMConstraint checking on more unary and nul [...] adds 33051d5d61f [X86] Remove X86Fmadd SDNode from tablegen. Use standard fm [...] adds 7df3544e80f [GlobalISel] Fix assertion failures after "GlobalISel: Retu [...] adds aca4488847b [lldb] Surpress "ingoring result" warning in reproducer_handler adds bd39a5cb30a [lldb/test] Automatically skip remote lldb-server tests whe [...] adds 7a3e11fe96d [ARM] Add some NEON anyextend testing. NFC adds 0c6e19b7058 [AArch64] Add some anyextend testing. NFC adds fb77d950221 [AArch64] Fix legalization of i128 ctpop without neon adds 0af42d3dc73 [PatternMatch][LVI] Handle select-form and/or in LVI adds 079923309c6 [llvm-cov] Use is_contained (NFC) adds 789d2506136 [CodeGen, Transforms] Use *Map::lookup (NFC) adds 8299fb8f256 [Transforms] Use llvm::append_range (NFC) adds 0ea3749b3cd [LV] Set up branch from middle block earlier. adds 0d05c1f40d6 [GVN] Add tests for select form of and/or (NFC) adds 0060f101345 [EarlyCSE] Add tests for select form of and/or (NFC) adds f1d648b973d [GVN] Use m_LogicalAnd/Or to propagate equality from branch [...] adds d3f1f7b6bca [EarlyCSE] Use m_LogicalAnd/Or matchers to handle branch co [...] adds eca40c36ef1 [ValueTracking] Add unit tests for isKnownNonZero, isImplie [...] adds 4ad41902e8c [GVN] Correctly set modified status when doing PRE on indices. adds 860199dfbe6 [ValueTracking] Use m_LogicalAnd/Or to look into conditions adds 9d70dbdc2bf [InstCombine] use poison as placeholder for undemanded elems adds d76c1d2247a [RS4GC] Lazily set changed flag when folding single entry phis adds 31c2b93d83f [MachineSink] add threshold in machinesink pass to reduce c [...] adds fde3ae88ee4 [asan][memprof] Declare _DYNAMIC and fix -Wparentheses adds 0b56e3cdda5 [sanitizer] Defined SANITIZER_TEST_HAS_PVALLOC only on glibc adds 99d650b3699 [compiler-rt][test] Make glibc-* feature detection work on [...] adds 60afb58bfee [msan] Delete unused glibc header <execinfo.h> adds d85a198e852 [RISCV] Pattern-match more vector-splatted constants adds a485a59d217 [benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20 adds 5b17263b6b9 [AMDGPU][MC][NFC] Parser refactoring adds 8c25bb3d0d5 [AMDGPU][MC] Improved errors handling for v_interp* operands adds e673d401994 [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics. adds 644da789e36 [AMDGPU] Split edge to make si_if dominate end_cf adds 0999408aea7 [clangd] Add error handling (elog) in code completion. adds c3b9d85bd4b [clang-tidy][NFC] Remove unnecessary headers adds e73f885c988 [PowerPC] Remove redundant COPY_TO_REGCLASS introduced by 8 [...] adds 496fb70b141 [MachO] Fix enum-int mismatch warning adds d55627d221b [flang] Fix bugs in .mod file for abstract interface adds b9a7c89d432 [MIRPrinter] Fix incorrect output of unnamed stack names adds d4ccef38d0b [InstCombine] 'hoist xor-by-constant from xor-by-value': ig [...] adds 4820af99ddc [TableGen] Fix bug in !interleave operator adds 38bfa25387f Revert "[benchmark] Fixed a build error when using CMake 3. [...] adds c7ff2c0da1a [AMDGPU][MC][NFC] Split large asm tests into smaller chunks adds dcd21572f97 [ValueTracking] Fix isKnownNonEqual() with constexpr mul adds e4df6a40dad [LV] Vectorize (some) early and multiple exit loops adds 4ffcd4fe9ac Revert "[LV] Vectorize (some) early and multiple exit loops" adds 4b33b238778 Reapply "[LV] Vectorize (some) early and multiple exit loop [...] adds 30f589c9121 [libc++] Constexpr-proof some machinery in not_fn.pass.cpp. NFCI. adds 7b00e9fae38 [libc++] [P1065] Constexpr invoke, reference_wrapper, mem_f [...] adds 9abc457724b [NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative adds dd756e3e848 [libc++] Fix a test failure in 7b00e9fae3 (D93815). adds 76a718ee939 [lldb] Deduplicate some lldb-server tests adds cf8f682c2dd [RISCV] Adjust tested vor ops for more stable tests. NFC. adds 34405b41d61 [CodeGen][ObjC] Destroy callee-destroyed arguments in the c [...] adds 6d02d12e172 [AMDGPU][MC][NFC] Added more tests for flat_global adds f931290308a [PowerPC] Parse and ignore .machine adds ef93f7a11c3 [SimplifyCFG] FoldBranchToCommonDest: gracefully handle unr [...] adds 87c032f7b44 [IR] Make Value::getType() work better with invalid IR. adds 1351f719d49 [InstSimplify] add tests for ctpop; NFC (PR48608) adds 236c4524a7c [InstSimplify] remove ctpop of 1 (low) bit adds b4655a0815d [NFC][sanitizer] Remove unused typedef adds 4a16c507cb6 [InstCombine] Disable unsafe select transform behind a flag adds 0f2c180163a [ValueTracking] Implement impliesPoison adds 44ee14f993f [WebAssembly][NFC] Finish cleaning up SIMD tablegen adds 6c36286a2e1 [NewPM] Fix CGSCCOptimizerLateEPCallbacks place in pipeline adds 5e09e9979bc [WebAssembly] Prototype extending pairwise add instructions adds 25007b4d7e0 [MLIR][NFC] Change FunctionLike::setAllArgAttrs/setAllResul [...] adds e6ae623314b [IROutliner] Adding support for consolidating functions wit [...] adds 85af1d6257f [test] Fix pr45360.ll under NPM adds 4ddf140c004 Fix PR35902: incorrect alignment used for ubsan check. adds c0a2d3b90b3 [libc++] Fix a test failure in 7b00e9fae3 (D93815). adds f782d5ea86f [flang] Detect call to abstract interface adds 4646de5d75c [NewPM][CodeGen] Introduce CodeGenPassBuilder to help build [...] adds 94427af60c6 Revert "[NewPM][CodeGen] Introduce CodeGenPassBuilder to he [...] adds 0e9abcfc192 [AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector) adds 4f568fbd216 [PowerPC] Do not emit HW loop when TLS var accessed in PHI [...] adds 8b67c98c477 [UpdateTestChecks] Fix update_analyze_test_checks.py failure adds f3f9ce3b794 [RISCV] Define vmclr.m/vmset.m intrinsics. adds 1e23802507d [IROutliner] Merging identical output blocks for extracted [...] adds 1e3ed09165c [CodeGen] Use llvm::append_range (NFC) adds 5d2529f28f9 [Scalar] Construct SmallVector with iterator ranges (NFC) adds 2883cd98f3c [CFGPrinter] Use succ_empty (NFC) adds 55d13e6a867 [asan][test] Annotate glibc specific tests with REQUIRES: g [...] adds c2ef06d3dd0 [NewPM] Port infer-address-spaces adds c5d100fdf2d [test] Fix conditional-temporaries.cpp adds a8970dff1ae [ubsan][test] FLush stdout before checking interleaved stdo [...] adds 53f80d6b3a0 [lldb] Fix logging in lldb-server tests adds ed146d6291c [LLD][ELF] - Use LLVM_ELF_IMPORT_TYPES_ELFT instead of mult [...] adds ae6e89327b0 Precommit tests that have poison as shufflevector's placeholder adds a0b68a2925f [lldb] Deduplicate some tests in TestLldbGdbServer adds 5abfeccf10b [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM adds 0a19fc3088f [PowerPC] Disable CTR loops containing operations on half-p [...] adds aebb4a60522 [RISCV] Rewrite and simplify helper function. NFC.

No new revisions were added by this update.

Summary of changes: clang-tools-extra/clang-tidy/ClangTidy.cpp | 4 - clang-tools-extra/clang-tidy/ClangTidyCheck.cpp | 2 - .../clang-tidy/ClangTidyDiagnosticConsumer.cpp | 6 +- clang-tools-extra/clang-tidy/ClangTidyModule.h | 2 - clang-tools-extra/clang-tidy/ClangTidyOptions.cpp | 1 - .../clang-tidy/ClangTidyProfiling.cpp | 2 - .../readability/ContainerSizeEmptyCheck.cpp | 183 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 37 +- clang-tools-extra/clangd/ClangdLSPServer.h | 11 +- clang-tools-extra/clangd/CodeComplete.cpp | 12 +- clang-tools-extra/clangd/DumpAST.cpp | 1 - clang-tools-extra/clangd/FindTarget.cpp | 1 - .../clangd/GlobalCompilationDatabase.cpp | 11 +- clang-tools-extra/clangd/index/Merge.cpp | 6 + clang-tools-extra/clangd/index/remote/Client.cpp | 3 +- clang-tools-extra/clangd/support/Threading.cpp | 12 + clang-tools-extra/clangd/support/Threading.h | 29 + clang-tools-extra/clangd/unittests/IndexTests.cpp | 34 + .../clangd/unittests/support/ThreadingTests.cpp | 21 + clang-tools-extra/docs/ReleaseNotes.rst | 12 +- .../checkers/readability-container-size-empty.cpp | 218 +- clang/docs/ClangFormatStyleOptions.rst | 10 + clang/docs/ReleaseNotes.rst | 3 + clang/docs/tools/dump_format_style.py | 2 +- clang/include/clang/AST/ASTContext.h | 4 +- clang/include/clang/AST/Decl.h | 3 + clang/include/clang/AST/DependenceFlags.h | 6 - clang/include/clang/AST/Expr.h | 14 +- clang/include/clang/AST/PropertiesBase.td | 12 - clang/include/clang/AST/RecursiveASTVisitor.h | 2 - clang/include/clang/AST/TemplateArgumentVisitor.h | 2 - clang/include/clang/AST/TemplateBase.h | 53 +- clang/include/clang/AST/Type.h | 4 +- clang/include/clang/Basic/BuiltinsWebAssembly.def | 6 + clang/include/clang/Basic/CodeGenOptions.h | 2 - clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + .../include/clang/Basic/DiagnosticFrontendKinds.td | 2 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 5 + clang/include/clang/Basic/FileEntry.h | 9 + clang/include/clang/Basic/FileManager.h | 11 + clang/include/clang/Driver/Options.td | 1362 +- clang/include/clang/Format/Format.h | 81 +- clang/include/clang/Sema/Sema.h | 7 +- .../include/clang/Serialization/ASTRecordWriter.h | 1 - clang/lib/AST/ASTContext.cpp | 13 +- clang/lib/AST/ASTImporter.cpp | 11 - clang/lib/AST/ASTStructuralEquivalence.cpp | 4 - clang/lib/AST/ComputeDependence.cpp | 13 +- clang/lib/AST/Decl.cpp | 15 +- clang/lib/AST/Expr.cpp | 35 +- clang/lib/AST/ExprCXX.cpp | 11 +- clang/lib/AST/ExprConstant.cpp | 101 +- clang/lib/AST/ItaniumMangle.cpp | 52 +- clang/lib/AST/MicrosoftMangle.cpp | 11 - clang/lib/AST/ODRHash.cpp | 2 - clang/lib/AST/StmtProfile.cpp | 6 - clang/lib/AST/TemplateBase.cpp | 127 +- clang/lib/AST/Type.cpp | 20 +- clang/lib/AST/TypeLoc.cpp | 1 - clang/lib/Basic/FileEntry.cpp | 1 + clang/lib/Basic/FileManager.cpp | 25 +- clang/lib/Basic/SourceManager.cpp | 50 +- clang/lib/CodeGen/CGBuiltin.cpp | 22 + clang/lib/CodeGen/CGCXXABI.cpp | 4 +- clang/lib/CodeGen/CGCall.h | 6 +- clang/lib/CodeGen/CGDebugInfo.cpp | 8 - clang/lib/CodeGen/CGExprConstant.cpp | 10 +- clang/lib/CodeGen/CGObjCMac.cpp | 22 +- clang/lib/CodeGen/CodeGenAction.cpp | 126 +- clang/lib/CodeGen/CodeGenFunction.cpp | 8 +- clang/lib/Format/BreakableToken.cpp | 13 +- clang/lib/Format/Format.cpp | 18 +- clang/lib/Format/TokenAnnotator.cpp | 15 +- clang/lib/Format/UnwrappedLineParser.cpp | 19 +- clang/lib/Frontend/CompilerInstance.cpp | 58 +- clang/lib/Frontend/CompilerInvocation.cpp | 902 +- clang/lib/Index/USRGeneration.cpp | 4 - clang/lib/Sema/SemaLookup.cpp | 1 - clang/lib/Sema/SemaOverload.cpp | 19 +- clang/lib/Sema/SemaTemplate.cpp | 232 +- clang/lib/Sema/SemaTemplateDeduction.cpp | 94 +- clang/lib/Sema/SemaTemplateInstantiate.cpp | 16 +- clang/lib/Sema/SemaTemplateVariadic.cpp | 2 - clang/lib/Sema/TreeTransform.h | 12 +- clang/lib/Serialization/ASTReader.cpp | 1 - clang/lib/Serialization/ASTWriter.cpp | 1 - clang/test/CXX/drs/dr15xx.cpp | 14 - clang/test/CXX/drs/dr20xx.cpp | 12 - .../SystemZ/builtins-systemz-zvector-constrained.c | 2 +- .../CodeGen/SystemZ/builtins-systemz-zvector.c | 18 +- .../builtins-systemz-zvector2-constrained.c | 4 +- .../CodeGen/SystemZ/builtins-systemz-zvector2.c | 4 +- clang/test/CodeGen/basic-block-sections.c | 10 +- clang/test/CodeGen/builtins-wasm.c | 28 + clang/test/CodeGenCXX/catch-undef-behavior.cpp | 13 +- clang/test/CodeGenCXX/conditional-temporaries.cpp | 25 +- clang/test/CodeGenCXX/mangle-ms-templates.cpp | 10 - clang/test/CodeGenCXX/mangle-template.cpp | 60 +- clang/test/CodeGenCXX/template-arguments.cpp | 81 - clang/test/CodeGenObjC/objc-dispatch-null-check.m | 34 + clang/test/CodeGenObjC/strong-in-c-struct.m | 18 + clang/test/CodeGenObjC/weak-in-c-struct.m | 19 + clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm | 53 + clang/test/Driver/aarch64-cpus.c | 8 + clang/test/Format/error-config.cpp | 4 +- clang/test/Misc/dev-fd-fs.c | 13 + .../OpenMP/distribute_dist_schedule_messages.cpp | 2 +- ...tribute_parallel_for_dist_schedule_messages.cpp | 2 +- ...te_parallel_for_simd_dist_schedule_messages.cpp | 2 +- .../distribute_simd_dist_schedule_messages.cpp | 2 +- .../target_parallel_for_simd_collapse_messages.cpp | 2 +- .../target_parallel_for_simd_ordered_messages.cpp | 2 +- .../test/OpenMP/target_simd_collapse_messages.cpp | 2 +- ...get_teams_distribute_dist_schedule_messages.cpp | 2 +- ...tribute_parallel_for_dist_schedule_messages.cpp | 2 +- ...te_parallel_for_simd_dist_schedule_messages.cpp | 2 +- ...eams_distribute_simd_dist_schedule_messages.cpp | 2 +- clang/test/OpenMP/target_update_from_messages.cpp | 2 +- clang/test/OpenMP/target_update_to_messages.cpp | 2 +- clang/test/OpenMP/task_messages.cpp | 4 +- .../teams_distribute_dist_schedule_messages.cpp | 2 +- ...tribute_parallel_for_dist_schedule_messages.cpp | 2 +- ...te_parallel_for_simd_dist_schedule_messages.cpp | 2 +- ...eams_distribute_simd_dist_schedule_messages.cpp | 2 +- clang/test/Profile/c-generate.c | 2 +- clang/test/Sema/invalid-bitwidth-expr.mm | 1 - .../SemaCXX/invalid-template-base-specifier.cpp | 4 +- clang/test/SemaCXX/warn-unused-lambda-capture.cpp | 2 +- clang/test/SemaTemplate/dependent-expr.cpp | 7 +- .../test/SemaTemplate/instantiation-dependence.cpp | 74 - .../test/SemaTemplate/partial-spec-instantiate.cpp | 18 +- clang/test/SemaTemplate/temp_arg_nontype_cxx17.cpp | 513 - clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp | 505 + clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp | 80 +- .../test/SemaTemplate/temp_arg_template_cxx1z.cpp | 8 +- clang/tools/libclang/CIndex.cpp | 5 - clang/tools/libclang/CXCursor.cpp | 3 - clang/unittests/CMakeLists.txt | 2 +- clang/unittests/Format/FormatTest.cpp | 149 +- clang/unittests/Format/FormatTestComments.cpp | 6 + clang/unittests/Format/FormatTestTextProto.cpp | 16 +- .../unittests/Frontend/CompilerInvocationTest.cpp | 84 +- clang/www/cxx_dr_status.html | 4 +- compiler-rt/lib/asan/asan_linux.cpp | 3 +- compiler-rt/lib/memprof/memprof_linux.cpp | 4 +- compiler-rt/lib/memprof/memprof_mapping.h | 2 +- compiler-rt/lib/msan/msan_linux.cpp | 1 - .../lib/sanitizer_common/sanitizer_stacktrace.h | 2 - .../sanitizer_common/tests/sanitizer_test_utils.h | 4 +- .../lib/scudo/standalone/allocator_config.h | 51 +- compiler-rt/lib/scudo/standalone/combined.h | 32 +- compiler-rt/lib/scudo/standalone/memtag.h | 5 + compiler-rt/lib/scudo/standalone/options.h | 6 + compiler-rt/lib/scudo/standalone/primary32.h | 32 +- compiler-rt/lib/scudo/standalone/primary64.h | 35 +- compiler-rt/lib/scudo/standalone/secondary.h | 14 +- .../lib/scudo/standalone/tests/combined_test.cpp | 25 +- .../lib/scudo/standalone/tests/primary_test.cpp | 62 +- .../lib/scudo/standalone/tests/secondary_test.cpp | 20 +- .../test/asan/TestCases/Linux/printf-fortify-1.c | 2 +- .../test/asan/TestCases/Linux/printf-fortify-2.c | 2 +- .../test/asan/TestCases/Linux/printf-fortify-3.c | 2 +- .../test/asan/TestCases/Linux/printf-fortify-4.c | 2 +- .../test/asan/TestCases/Linux/printf-fortify-5.c | 2 +- .../TestCases/Linux/swapcontext_annotation.cpp | 4 +- .../test/asan/TestCases/Linux/swapcontext_test.cpp | 4 +- .../test/asan/TestCases/malloc-no-intercept.c | 2 +- compiler-rt/test/lit.common.cfg.py | 12 +- compiler-rt/test/ubsan/TestCases/Misc/monitor.cpp | 1 + flang/docs/GettingInvolved.md | 6 +- flang/lib/Semantics/mod-file.cpp | 11 +- flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/lib/Semantics/resolve-names.cpp | 10 +- flang/test/Semantics/modfile10.f90 | 37 + flang/test/Semantics/omp-private03.f90 | 39 + flang/test/Semantics/procinterface01.f90 | 2 +- flang/test/Semantics/resolve20.f90 | 11 + flang/test/Semantics/symbol15.f90 | 2 +- libcxx/docs/Cxx2aStatusPaperStatus.csv | 2 +- libcxx/docs/FeatureTestMacroTable.rst | 2 +- libcxx/include/__functional_base | 19 +- libcxx/include/functional | 54 +- libcxx/include/type_traits | 14 +- libcxx/include/version | 5 +- .../support.limits.general/array.version.pass.cpp | 26 - .../functional.version.pass.cpp | 30 +- .../iterator.version.pass.cpp | 26 - .../string_view.version.pass.cpp | 32 +- .../support.limits.general/tuple.version.pass.cpp | 26 - .../utility.version.pass.cpp | 26 - .../version.version.pass.cpp | 30 +- .../func.invoke/invoke_constexpr.pass.cpp | 279 + .../func.memfn/member_data.pass.cpp | 11 +- .../func.memfn/member_function.pass.cpp | 23 +- .../func.memfn/member_function_const.pass.cpp | 23 +- .../function.objects/func.not_fn/not_fn.pass.cpp | 248 +- .../func.search.default/default.pass.cpp | 21 +- .../func.search.default/default.pred.pass.cpp | 75 +- .../generate_feature_test_macro_components.py | 7 +- lld/COFF/Options.td | 2 +- lld/ELF/InputFiles.h | 7 +- lld/ELF/SyntheticSections.h | 7 +- lld/ELF/Writer.cpp | 5 +- lld/MachO/Driver.cpp | 40 +- lld/MachO/Options.td | 4 +- lld/MachO/SyntheticSections.cpp | 22 +- .../MachO/MachONormalizedFileFromAtoms.cpp | 2 +- lld/test/ELF/lto/basic-block-sections.ll | 8 +- lld/test/MachO/driver.test | 4 +- lld/test/MachO/platform-version.s | 2 +- lld/test/MachO/symtab.s | 6 +- lld/test/MachO/x86-64-reloc-unsigned.s | 4 + lldb/bindings/interface/SBType.i | 6 + lldb/include/lldb/API/SBType.h | 5 + lldb/include/lldb/Interpreter/CommandInterpreter.h | 2 +- lldb/include/lldb/Symbol/CompilerType.h | 4 + lldb/include/lldb/Symbol/TypeSystem.h | 5 + lldb/include/lldb/Utility/Timer.h | 7 + lldb/include/lldb/lldb-enumerations.h | 1 - lldb/packages/Python/lldbsuite/test/dotest.py | 9 + .../test/tools/lldb-server/gdbremote_testcase.py | 8 +- lldb/source/API/SBType.cpp | 20 + lldb/source/API/SystemInitializerFull.cpp | 3 - lldb/source/Commands/CommandObjectCommands.cpp | 7 +- lldb/source/Commands/CommandObjectTarget.cpp | 3 +- lldb/source/Core/Disassembler.cpp | 4 +- lldb/source/Core/Mangled.cpp | 12 - lldb/source/Core/Module.cpp | 43 +- .../Initialization/SystemInitializerCommon.cpp | 6 +- lldb/source/Interpreter/CommandInterpreter.cpp | 149 +- .../CPlusPlus/CPPLanguageRuntime.cpp | 4 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 5 +- .../BSD-Archive/ObjectContainerBSDArchive.cpp | 4 +- .../Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 4 +- .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 3 +- .../ScriptInterpreter/Lua/ScriptInterpreterLua.cpp | 3 +- .../Python/ScriptInterpreterPython.cpp | 9 +- .../Plugins/SymbolFile/DWARF/DWARFDebugAranges.cpp | 3 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 8 +- .../Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp | 3 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 19 +- .../SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp | 12 +- .../Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp | 3 +- .../Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp | 3 +- .../Plugins/TypeSystem/Clang/TypeSystemClang.cpp | 24 +- .../Plugins/TypeSystem/Clang/TypeSystemClang.h | 5 + lldb/source/Symbol/CompileUnit.cpp | 3 +- lldb/source/Symbol/CompilerType.cpp | 12 + lldb/source/Symbol/DWARFCallFrameInfo.cpp | 3 +- lldb/source/Symbol/LocateSymbolFile.cpp | 9 +- lldb/source/Symbol/ObjectFile.cpp | 234 +- lldb/source/Symbol/Symtab.cpp | 26 +- lldb/source/Target/Target.cpp | 4 +- lldb/source/Target/TargetList.cpp | 7 +- lldb/test/API/python_api/type/TestTypeList.py | 23 + lldb/test/API/python_api/type/main.cpp | 7 + .../API/tools/lldb-server/TestGdbRemoteAttach.py | 21 +- .../tools/lldb-server/TestGdbRemoteAuxvSupport.py | 1 - .../tools/lldb-server/TestGdbRemoteCompletion.py | 3 +- .../API/tools/lldb-server/TestGdbRemoteExitCode.py | 2 - .../lldb-server/TestGdbRemoteExpeditedRegisters.py | 107 +- .../API/tools/lldb-server/TestGdbRemoteHostInfo.py | 22 +- .../API/tools/lldb-server/TestGdbRemoteKill.py | 1 - .../tools/lldb-server/TestGdbRemoteProcessInfo.py | 5 - .../lldb-server/TestGdbRemoteRegisterState.py | 2 - .../tools/lldb-server/TestGdbRemoteSingleStep.py | 1 - .../lldb-server/TestGdbRemoteThreadsInStopReply.py | 5 - .../lldb-server/TestGdbRemote_qThreadStopInfo.py | 82 +- .../API/tools/lldb-server/TestLldbGdbServer.py | 257 +- .../commandline/TestGdbRemoteConnection.py | 19 - .../inferior-crash/TestGdbRemoteAbort.py | 1 - .../inferior-crash/TestGdbRemoteSegFault.py | 1 - .../register-reading/TestGdbRemoteGPacket.py | 1 - .../signal-filtering/TestGdbRemote_QPassSignals.py | 4 - lldb/test/Shell/Unwind/basic-block-sections.test | 14 +- lldb/tools/driver/Driver.cpp | 3 +- lldb/tools/lldb-test/SystemInitializerTest.cpp | 3 - llvm/docs/AMDGPUUsage.rst | 5 + llvm/docs/Coroutines.rst | 42 + llvm/docs/TableGen/ProgRef.rst | 10 +- llvm/include/llvm/ADT/SmallVector.h | 14 +- llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/Analysis/BranchProbabilityInfo.h | 153 +- llvm/include/llvm/Analysis/CallGraph.h | 7 - .../include/llvm/Analysis/IRSimilarityIdentifier.h | 37 +- .../llvm/Analysis/LazyBranchProbabilityInfo.h | 2 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 196 +- llvm/include/llvm/Analysis/ValueTracking.h | 5 + llvm/include/llvm/CodeGen/Analysis.h | 5 - .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 2 +- llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 11 +- llvm/include/llvm/CodeGen/MachineInstrBuilder.h | 3 + llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h | 5 +- llvm/include/llvm/CodeGen/VirtRegMap.h | 8 +- llvm/include/llvm/IR/Intrinsics.td | 2 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 187 + llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 9 + llvm/include/llvm/IR/PatternMatch.h | 95 +- llvm/include/llvm/IR/SymbolTableListTraits.h | 8 +- llvm/include/llvm/MC/MCInstrDesc.h | 31 +- llvm/include/llvm/Object/Binary.h | 4 +- llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/include/llvm/Option/OptParser.td | 18 +- llvm/include/llvm/Support/AArch64TargetParser.def | 3 + llvm/include/llvm/Support/ARMTargetParser.def | 4 +- llvm/include/llvm/Support/KnownBits.h | 24 +- llvm/include/llvm/TableGen/Record.h | 2 +- llvm/include/llvm/Transforms/IPO/IROutliner.h | 36 +- .../llvm/Transforms/InstCombine/InstCombiner.h | 13 + .../llvm/Transforms/Scalar/InferAddressSpaces.h | 27 + .../llvm/Transforms/Utils/BasicBlockUtils.h | 2 +- llvm/include/llvm/Transforms/Utils/Local.h | 14 - llvm/lib/Analysis/BasicAliasAnalysis.cpp | 13 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 645 +- llvm/lib/Analysis/CFGPrinter.cpp | 2 +- llvm/lib/Analysis/CallGraph.cpp | 14 - llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 226 +- llvm/lib/Analysis/InstructionSimplify.cpp | 9 + llvm/lib/Analysis/LazyValueInfo.cpp | 14 +- llvm/lib/Analysis/MemorySSA.cpp | 3 +- llvm/lib/Analysis/OptimizationRemarkEmitter.cpp | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 192 +- llvm/lib/CodeGen/Analysis.cpp | 21 - llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 3 +- llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp | 7 +- llvm/lib/CodeGen/AsmPrinter/WinCFGuard.cpp | 3 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 2 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 + llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 29 +- .../lib/CodeGen/GlobalISel/InstructionSelector.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp | 9 +- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 30 +- llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 10 +- llvm/lib/CodeGen/MIRPrinter.cpp | 2 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 5 +- llvm/lib/CodeGen/MachineFunction.cpp | 2 +- llvm/lib/CodeGen/MachineModuleInfo.cpp | 3 +- llvm/lib/CodeGen/MachineOutliner.cpp | 6 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 2 +- llvm/lib/CodeGen/MachineSink.cpp | 36 + llvm/lib/CodeGen/MultiHazardRecognizer.cpp | 7 +- llvm/lib/CodeGen/RDFLiveness.cpp | 4 +- llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 3 +- llvm/lib/CodeGen/RegAllocPBQP.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- .../CodeGen/SelectionDAG/StatepointLowering.cpp | 2 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ExecutionEngine/SectionMemoryManager.cpp | 8 +- llvm/lib/Linker/IRMover.cpp | 3 +- llvm/lib/Object/COFFObjectFile.cpp | 24 +- llvm/lib/Object/ELFObjectFile.cpp | 3 +- llvm/lib/Object/XCOFFObjectFile.cpp | 4 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Passes/PassBuilder.cpp | 23 +- llvm/lib/Passes/PassRegistry.def | 3 +- llvm/lib/Support/SourceMgr.cpp | 28 +- llvm/lib/TableGen/Record.cpp | 65 +- llvm/lib/TableGen/TGLexer.cpp | 1 + llvm/lib/TableGen/TGLexer.h | 6 +- llvm/lib/TableGen/TGParser.cpp | 95 +- llvm/lib/TableGen/TGParser.h | 1 + llvm/lib/Target/AArch64/AArch64.td | 20 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 26 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 + llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 6 +- llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 + llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 + .../AArch64/GISel/AArch64InstructionSelector.cpp | 47 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 4 +- .../AArch64/GISel/AArch64PostLegalizerCombiner.cpp | 2 +- .../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 22 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 28 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 8 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 97 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 64 + llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 160 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 34 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 23 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 59 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 3 + .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 194 +- llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 + llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 13 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 8 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 62 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 19 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 + llvm/lib/Target/AMDGPU/SIInstrInfo.td | 7 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 19 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 + llvm/lib/Target/ARM/ARM.td | 14 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 25 + llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 4 + llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 173 + llvm/lib/Target/ARM/ARMHazardRecognizer.h | 32 + llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 + llvm/lib/Target/ARM/ARMSubtarget.h | 3 + llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 9 +- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 6 +- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 25 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 72 +- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 +- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 33 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 55 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 3 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 102 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 5 + llvm/lib/Target/RISCV/RISCVInstrFormats.td | 56 +- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 18 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 1011 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 166 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 3 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 52 +- llvm/lib/Target/VE/VVPInstrInfo.td | 3 + llvm/lib/Target/VE/VVPInstrPatternsVec.td | 3 + llvm/lib/Target/VE/VVPNodes.def | 1 + .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 40 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 1158 +- .../Target/WebAssembly/WebAssemblyRegStackify.cpp | 2 +- llvm/lib/Target/X86/X86InstrAVX512.td | 10 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 2 - llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 +- llvm/lib/Transforms/Coroutines/CoroEarly.cpp | 7 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 19 +- llvm/lib/Transforms/Coroutines/CoroInstr.h | 40 +- llvm/lib/Transforms/Coroutines/CoroInternal.h | 4 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 100 +- llvm/lib/Transforms/Coroutines/Coroutines.cpp | 25 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 4 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 757 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 2 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 2 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 15 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 51 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 7 +- .../Transforms/InstCombine/InstCombineNegator.cpp | 3 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 54 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 23 +- .../InstCombine/InstructionCombining.cpp | 7 +- .../Instrumentation/ControlHeightReduction.cpp | 9 +- .../Instrumentation/DataFlowSanitizer.cpp | 3 +- llvm/lib/Transforms/Scalar/EarlyCSE.cpp | 16 +- llvm/lib/Transforms/Scalar/GVN.cpp | 17 +- llvm/lib/Transforms/Scalar/GuardWidening.cpp | 3 +- llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp | 94 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 350 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopSink.cpp | 3 +- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 8 +- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp | 4 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 12 - llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp | 3 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 4 +- .../Transforms/Scalar/RewriteStatepointsForGC.cpp | 9 +- llvm/lib/Transforms/Scalar/SROA.cpp | 4 +- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 6 +- llvm/lib/Transforms/Utils/BuildLibCalls.cpp | 4 +- llvm/lib/Transforms/Utils/CodeMoverUtils.cpp | 45 +- llvm/lib/Transforms/Utils/Evaluator.cpp | 6 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 7 +- llvm/lib/Transforms/Utils/Local.cpp | 28 - llvm/lib/Transforms/Utils/LoopVersioning.cpp | 4 +- llvm/lib/Transforms/Utils/SSAUpdater.cpp | 3 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 8 + .../Vectorize/LoopVectorizationLegality.cpp | 25 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 95 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 148 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 22 + .../Analysis/BlockFrequencyInfo/redundant_edges.ll | 2 +- llvm/test/Analysis/BranchProbabilityInfo/basic.ll | 40 +- .../BranchProbabilityInfo/deopt-intrinsic.ll | 4 +- .../Analysis/BranchProbabilityInfo/deopt-invoke.ll | 107 + llvm/test/Analysis/BranchProbabilityInfo/loop.ll | 209 +- .../Analysis/BranchProbabilityInfo/noreturn.ll | 35 +- .../Analysis/BranchProbabilityInfo/unreachable.ll | 154 + .../CostModel/AArch64/kryo-inseltpoison.ll | 26 + .../PowerPC/insert_extract-inseltpoison.ll | 187 + .../CostModel/SystemZ/vectorinstrs-inseltpoison.ll | 56 + .../X86/insert-extract-at-zero-inseltpoison.ll | 40 + .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll | 39 + .../X86/masked-intrinsic-cost-inseltpoison.ll | 1911 + .../CostModel/X86/uniformshift-inseltpoison.ll | 39 + .../CostModel/X86/vector-insert-inseltpoison.ll | 1270 + .../CostModel/X86/vector_gep-inseltpoison.ll | 17 + .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 1843 + .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 1867 + .../CostModel/X86/vshift-shl-cost-inseltpoison.ll | 2197 + .../Analysis/DemandedBits/vectors-inseltpoison.ll | 136 + .../test/Analysis/ValueTracking/known-non-equal.ll | 12 + .../combine-shift-immed-mismatch-crash.mir | 58 + .../irtranslator-invoke-probabilities.ll | 2 +- llvm/test/CodeGen/AArch64/aarch64-smull.ll | 583 +- llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll | 1144 +- llvm/test/CodeGen/AArch64/ctpop-nonean.ll | 36 + .../CodeGen/AArch64/sve-fixed-length-int-minmax.ll | 48 +- llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll | 643 + .../CodeGen/AArch64/sve-intrinsics-reversal.ll | 35 - llvm/test/CodeGen/AArch64/sve-rev.ll | 97 + .../GlobalISel/extractelement-stack-lower.ll | 1675 +- .../CodeGen/AMDGPU/GlobalISel/extractelement.ll | 16 +- .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 749 + .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll | 260 +- .../GlobalISel/llvm.amdgcn.global.atomic.fadd.ll | 30 +- .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 89 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 11 +- .../CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir | 35 + llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir | 88 + .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 2 +- .../test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll | 15 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 5 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll | 2 +- .../AMDGPU/memory-legalizer-global-agent.ll | 838 +- .../AMDGPU/memory-legalizer-global-nontemporal.ll | 18 +- .../AMDGPU/memory-legalizer-global-singlethread.ll | 838 +- .../AMDGPU/memory-legalizer-global-system.ll | 838 +- .../AMDGPU/memory-legalizer-global-wavefront.ll | 838 +- .../AMDGPU/memory-legalizer-global-workgroup.ll | 838 +- .../CodeGen/AMDGPU/memory-legalizer-local-agent.ll | 402 +- .../AMDGPU/memory-legalizer-local-nontemporal.ll | 38 +- .../AMDGPU/memory-legalizer-local-singlethread.ll | 402 +- .../AMDGPU/memory-legalizer-local-system.ll | 402 +- .../AMDGPU/memory-legalizer-local-wavefront.ll | 402 +- .../AMDGPU/memory-legalizer-local-workgroup.ll | 402 +- .../AMDGPU/memory-legalizer-private-nontemporal.ll | 78 +- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 16 + llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll | 3 + llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll | 1 + llvm/test/CodeGen/AMDGPU/sroa-before-unroll.ll | 2 + .../transform-block-with-return-to-epilog.ll | 4 +- llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll | 69 +- .../AMDGPU/unstructured-cfg-def-use-issue.ll | 333 + llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll | 2 +- llvm/test/CodeGen/AMDGPU/vector-alloca.ll | 1 + llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll | 2 +- llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 2 +- .../CodeGen/ARM/v8m.base-jumptable_alignment.ll | 22 +- llvm/test/CodeGen/ARM/vadd.ll | 601 +- llvm/test/CodeGen/ARM/vmla.ll | 473 +- llvm/test/CodeGen/ARM/vmls.ll | 473 +- llvm/test/CodeGen/ARM/vmul.ll | 697 +- llvm/test/CodeGen/ARM/vsub.ll | 601 +- llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll | 23 + llvm/test/CodeGen/PowerPC/alloca-crspill.ll | 8 +- llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll | 261 +- llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll | 182 +- llvm/test/CodeGen/PowerPC/pr36292.ll | 5 +- llvm/test/CodeGen/PowerPC/pr48519.ll | 55 + llvm/test/CodeGen/PowerPC/pr48527.ll | 70 + llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 1 + .../CodeGen/PowerPC/store-rightmost-vector-elt.ll | 109 + llvm/test/CodeGen/RISCV/jumptable.ll | 349 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll | 822 + llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll | 794 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll | 881 + llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll | 1201 + llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll | 441 + llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll | 601 + llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll | 881 + llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll | 1201 + llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll | 421 + llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 421 + llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 856 + llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll | 1142 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 + llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 + llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 + llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 + llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 + llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 + llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 + llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll | 512 + llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll | 698 + llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 523 + llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 713 + llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll | 482 + llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll | 868 + llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll | 482 + llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll | 868 + llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll | 482 + llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll | 868 + llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll | 482 + llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll | 868 + llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll | 43 + llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll | 85 + llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll | 43 + llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll | 85 + llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll | 545 + llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll | 673 + llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll | 722 + llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll | 882 + llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll | 99 + llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll | 99 + llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll | 973 + llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll | 1189 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll | 99 + llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll | 99 + llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll | 1109 + llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll | 1081 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 + llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 + llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 + llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 + llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll | 845 + llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll | 817 + llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll | 800 + llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll | 978 + llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll | 24 + llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll | 1000 + llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 266 + llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll | 845 + llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll | 817 + llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll | 1034 + llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll | 1412 + llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll | 1034 + llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll | 1412 + llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll | 1034 + llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll | 1412 + llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll | 516 + llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll | 704 + llvm/test/CodeGen/SPARC/missinglabel.ll | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir | 4 +- llvm/test/CodeGen/SystemZ/sext-zext.ll | 19 + llvm/test/CodeGen/Thumb2/schedm7-hazard.ll | 38 + llvm/test/CodeGen/VE/Vector/vec_and.ll | 132 + llvm/test/CodeGen/WebAssembly/simd-build-vector.ll | 6 +- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 51 +- llvm/test/CodeGen/WebAssembly/simd-load-splat.ll | 2 +- .../WebAssembly/simd-load-store-alignment.ll | 36 +- .../CodeGen/WebAssembly/simd-nested-shuffles.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-offset.ll | 96 +- .../WebAssembly/simd-shift-complex-splats.ll | 2 +- .../CodeGen/WebAssembly/simd-shuffle-bitcast.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd.ll | 48 +- .../WebAssembly/switch-unreachable-default.ll | 4 +- llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll | 19 +- .../X86/basic-block-sections-blockaddress-taken.ll | 4 +- .../X86/basic-block-sections-clusters-branches.ll | 8 +- .../X86/basic-block-sections-clusters-eh.ll | 4 +- .../CodeGen/X86/basic-block-sections-clusters.ll | 8 +- .../X86/basic-block-sections-directjumps.ll | 14 +- llvm/test/CodeGen/X86/basic-block-sections-eh.ll | 4 +- llvm/test/CodeGen/X86/basic-block-sections-list.ll | 16 +- .../CodeGen/X86/basic-block-sections-listbb.ll | 4 +- .../CodeGen/X86/basic-block-sections-mir-parse.mir | 6 +- .../X86/basic-block-sections-unreachable.ll | 2 +- llvm/test/CodeGen/X86/basic-block-sections.ll | 12 +- llvm/test/CodeGen/X86/basic-block-sections_2.ll | 61 + llvm/test/CodeGen/X86/block-placement.ll | 4 +- .../test/CodeGen/X86/cfi-basic-block-sections-1.ll | 8 +- ...r-basic-block-sections-callee-save-registers.ll | 4 +- llvm/test/CodeGen/X86/dwarf_eh_resume.ll | 23 + .../CodeGen/X86/gcc_except_table_bb_sections.ll | 22 +- .../CodeGen/X86/misched_phys_reg_assign_order.ll | 6 +- llvm/test/CodeGen/X86/pr27501.ll | 10 +- llvm/test/CodeGen/X86/pr37916.ll | 2 +- llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 117 +- llvm/test/DebugInfo/X86/basic-block-sections_1.ll | 24 +- .../X86/stack-value-piece-inseltpoison.ll | 114 + llvm/test/MC/AMDGPU/flat-global.s | 40 + llvm/test/MC/AMDGPU/gfx10_asm_all.s | 126143 ------------------ llvm/test/MC/AMDGPU/gfx10_asm_ds.s | 6987 + llvm/test/MC/AMDGPU/gfx10_asm_flat.s | 128 + llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s | 2289 + llvm/test/MC/AMDGPU/gfx10_asm_smem.s | 1194 + llvm/test/MC/AMDGPU/gfx10_asm_sop.s | 10072 ++ llvm/test/MC/AMDGPU/gfx10_asm_vop1.s | 16229 +++ llvm/test/MC/AMDGPU/gfx10_asm_vop2.s | 13092 ++ llvm/test/MC/AMDGPU/gfx10_asm_vop3.s | 13141 ++ llvm/test/MC/AMDGPU/gfx10_asm_vopc.s | 11576 ++ llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s | 21692 +++ llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s | 13816 ++ llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s | 15975 +++ llvm/test/MC/AMDGPU/gfx10_err_pos.s | 51 +- llvm/test/MC/AMDGPU/gfx7_asm_all.s | 86860 ------------ llvm/test/MC/AMDGPU/gfx7_asm_ds.s | 3055 + llvm/test/MC/AMDGPU/gfx7_asm_exp.s | 82 + llvm/test/MC/AMDGPU/gfx7_asm_flat.s | 691 + llvm/test/MC/AMDGPU/gfx7_asm_mimg.s | 6661 + llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s | 1369 + llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s | 5371 + llvm/test/MC/AMDGPU/gfx7_asm_smrd.s | 751 + llvm/test/MC/AMDGPU/gfx7_asm_sop1.s | 4096 + llvm/test/MC/AMDGPU/gfx7_asm_sop2.s | 6832 + llvm/test/MC/AMDGPU/gfx7_asm_sopc.s | 2266 + llvm/test/MC/AMDGPU/gfx7_asm_sopk.s | 850 + llvm/test/MC/AMDGPU/gfx7_asm_sopp.s | 145 + llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s | 85 + llvm/test/MC/AMDGPU/gfx7_asm_vop1.s | 4576 + llvm/test/MC/AMDGPU/gfx7_asm_vop2.s | 3796 + llvm/test/MC/AMDGPU/gfx7_asm_vop3.s | 41875 ++++++ llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s | 10534 ++ llvm/test/MC/AMDGPU/gfx7_asm_vopc.s | 14113 ++ llvm/test/MC/AMDGPU/gfx8_asm_all.s | 119543 ----------------- llvm/test/MC/AMDGPU/gfx8_asm_ds.s | 3160 + llvm/test/MC/AMDGPU/gfx8_asm_exp.s | 82 + llvm/test/MC/AMDGPU/gfx8_asm_flat.s | 601 + llvm/test/MC/AMDGPU/gfx8_asm_mimg.s | 6865 + llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s | 2689 + llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s | 5488 + llvm/test/MC/AMDGPU/gfx8_asm_smem.s | 1165 + llvm/test/MC/AMDGPU/gfx8_asm_sop1.s | 4153 + llvm/test/MC/AMDGPU/gfx8_asm_sop2.s | 6952 + llvm/test/MC/AMDGPU/gfx8_asm_sopc.s | 2545 + llvm/test/MC/AMDGPU/gfx8_asm_sopk.s | 850 + llvm/test/MC/AMDGPU/gfx8_asm_sopp.s | 163 + llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s | 85 + llvm/test/MC/AMDGPU/gfx8_asm_vop1.s | 13768 ++ llvm/test/MC/AMDGPU/gfx8_asm_vop2.s | 12568 ++ llvm/test/MC/AMDGPU/gfx8_asm_vop3.s | 43843 ++++++ llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s | 13501 ++ llvm/test/MC/AMDGPU/gfx8_asm_vopc.s | 22963 ++++ llvm/test/MC/AMDGPU/gfx9_asm_all.s | 119325 ----------------- llvm/test/MC/AMDGPU/gfx9_asm_ds.s | 3364 + llvm/test/MC/AMDGPU/gfx9_asm_exp.s | 82 + llvm/test/MC/AMDGPU/gfx9_asm_flat.s | 4303 + llvm/test/MC/AMDGPU/gfx9_asm_mimg.s | 7108 + llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s | 2497 + llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s | 5638 + llvm/test/MC/AMDGPU/gfx9_asm_smem.s | 4477 + llvm/test/MC/AMDGPU/gfx9_asm_sop1.s | 3634 + llvm/test/MC/AMDGPU/gfx9_asm_sop2.s | 6880 + llvm/test/MC/AMDGPU/gfx9_asm_sopc.s | 2113 + llvm/test/MC/AMDGPU/gfx9_asm_sopk.s | 652 + llvm/test/MC/AMDGPU/gfx9_asm_sopp.s | 166 + llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s | 85 + llvm/test/MC/AMDGPU/gfx9_asm_vop1.s | 17017 +++ llvm/test/MC/AMDGPU/gfx9_asm_vop2.s | 14962 +++ llvm/test/MC/AMDGPU/gfx9_asm_vop3.s | 37702 ++++++ llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s | 16642 +++ llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s | 3484 + llvm/test/MC/AMDGPU/gfx9_asm_vopc.s | 29311 ++++ llvm/test/MC/AMDGPU/vintrp-err.s | 53 +- llvm/test/MC/Disassembler/WebAssembly/wasm.txt | 2 +- llvm/test/MC/PowerPC/ppc-machine.s | 5 + llvm/test/MC/RISCV/rvv/invalid.s | 20 + llvm/test/MC/WebAssembly/simd-encodings.s | 36 +- llvm/test/Object/elf-unknown-type.test | 10 - llvm/test/Other/new-pm-defaults.ll | 2 +- llvm/test/Other/scalable-vectors-core-ir.ll | 12 +- llvm/test/TableGen/interleave.td | 9 + llvm/test/TableGen/substr.td | 81 + .../Attributor/dereferenceable-2-inseltpoison.ll | 847 + llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/BDCE/vectors-inseltpoison.ll | 102 + .../AArch64/gather-scatter-opt-inseltpoison.ll | 113 + .../AArch64/sink-free-instructions-inseltpoison.ll | 274 + .../bypass-slow-div-debug-info-inseltpoison.ll | 76 + .../ARM/sink-add-mul-shufflevector-inseltpoison.ll | 219 + .../ARM/sink-free-instructions-inseltpoison.ll | 232 + .../CodeGenPrepare/ARM/sinkchain-inseltpoison.ll | 107 + .../X86/cgp_shuffle_crash-inseltpoison.ll | 14 + .../X86/gather-scatter-opt-inseltpoison.ll | 113 + .../X86/sink-addrmode-inseltpoison.ll | 321 + .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll | 411 + .../X86/x86-shuffle-sink-inseltpoison.ll | 257 + llvm/test/Transforms/Coroutines/coro-async.ll | 67 +- llvm/test/Transforms/Coroutines/coro-inline.ll | 2 +- .../Transforms/CorrelatedValuePropagation/basic.ll | 194 + .../masked-dead-store-inseltpoison.ll | 78 + llvm/test/Transforms/EarlyCSE/and_or.ll | 116 + .../2016-08-30-MaskedScatterGather-inseltpoison.ll | 42 + llvm/test/Transforms/GVN/PRE/modified-status.ll | 60 + llvm/test/Transforms/GVN/PRE/pre-gep-load.ll | 13 +- llvm/test/Transforms/GVN/condprop.ll | 66 + ...xpr-vector-constainsundef-crash-inseltpoison.ll | 25 + .../GVN/non-integral-pointers-inseltpoison.ll | 456 + llvm/test/Transforms/IROutliner/extraction.ll | 46 +- llvm/test/Transforms/IROutliner/illegal-assumes.ll | 22 +- llvm/test/Transforms/IROutliner/illegal-memcpy.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-memmove.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-vaarg.ll | 30 +- .../IROutliner/outlining-commutative-fp.ll | 107 + .../Transforms/IROutliner/outlining-commutative.ll | 254 + .../IROutliner/outlining-constants-vs-registers.ll | 42 +- .../IROutliner/outlining-different-constants.ll | 24 +- .../IROutliner/outlining-different-globals.ll | 14 +- .../outlining-different-output-blocks.ll | 110 + .../IROutliner/outlining-isomorphic-predicates.ll | 170 + .../IROutliner/outlining-remapped-outputs.ll | 74 + .../IROutliner/outlining-same-output-blocks.ll | 98 + llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll | 29 +- .../AMDGPU/infer-address-space.ll | 1 + .../AMDGPU/old-pass-regressions-inseltpoison.ll | 143 + .../dereferenceable-inseltpoison.ll | 357 + .../Inline/inlined-loop-metadata-inseltpoison.ll | 159 + .../AArch64/sve-bitcast-inseltpoison.ll | 13 + llvm/test/Transforms/InstCombine/AArch64/tbl1.ll | 2 +- .../amdgcn-demanded-vector-elts-inseltpoison.ll | 3828 + llvm/test/Transforms/InstCombine/ARM/tbl1.ll | 2 +- llvm/test/Transforms/InstCombine/X86/clmulqdq.ll | 18 +- .../X86/shufflemask-undef-inseltpoison.ll | 110 + .../InstCombine/X86/x86-addsub-inseltpoison.ll | 194 + llvm/test/Transforms/InstCombine/X86/x86-addsub.ll | 4 +- .../InstCombine/X86/x86-avx2-inseltpoison.ll | 110 + .../InstCombine/X86/x86-avx512-inseltpoison.ll | 3407 + llvm/test/Transforms/InstCombine/X86/x86-avx512.ll | 40 +- .../InstCombine/X86/x86-f16c-inseltpoison.ll | 71 + .../Transforms/InstCombine/X86/x86-insertps.ll | 4 +- .../InstCombine/X86/x86-masked-memops.ll | 16 +- .../InstCombine/X86/x86-muldq-inseltpoison.ll | 281 + llvm/test/Transforms/InstCombine/X86/x86-muldq.ll | 4 +- .../InstCombine/X86/x86-pack-inseltpoison.ll | 635 + llvm/test/Transforms/InstCombine/X86/x86-pack.ll | 4 +- .../InstCombine/X86/x86-pshufb-inseltpoison.ll | 515 + llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll | 72 +- .../InstCombine/X86/x86-sse-inseltpoison.ll | 694 + llvm/test/Transforms/InstCombine/X86/x86-sse.ll | 70 +- .../InstCombine/X86/x86-sse2-inseltpoison.ll | 541 + llvm/test/Transforms/InstCombine/X86/x86-sse2.ll | 66 +- .../InstCombine/X86/x86-sse41-inseltpoison.ll | 124 + llvm/test/Transforms/InstCombine/X86/x86-sse41.ll | 18 +- .../InstCombine/X86/x86-sse4a-inseltpoison.ll | 420 + llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll | 18 +- .../X86/x86-vec_demanded_elts-inseltpoison.ll | 110 + .../InstCombine/X86/x86-vec_demanded_elts.ll | 43 +- .../X86/x86-vector-shifts-inseltpoison.ll | 3783 + .../InstCombine/X86/x86-vector-shifts.ll | 20 +- .../InstCombine/X86/x86-vpermil-inseltpoison.ll | 301 + .../test/Transforms/InstCombine/X86/x86-vpermil.ll | 2 +- .../InstCombine/X86/x86-xop-inseltpoison.ll | 305 + llvm/test/Transforms/InstCombine/X86/x86-xop.ll | 4 +- llvm/test/Transforms/InstCombine/abs-1.ll | 6 +- llvm/test/Transforms/InstCombine/abs_abs.ll | 148 +- llvm/test/Transforms/InstCombine/and-xor-or.ll | 43 + .../Transforms/InstCombine/assume-inseltpoison.ll | 656 + .../Transforms/InstCombine/bitcast-bigendian.ll | 6 +- .../Transforms/InstCombine/bitcast-inseltpoison.ll | 573 + .../InstCombine/bitcast-vec-canon-inseltpoison.ll | 167 + .../Transforms/InstCombine/bitcast-vec-canon.ll | 4 +- llvm/test/Transforms/InstCombine/bitcast.ll | 6 +- .../InstCombine/broadcast-inseltpoison.ll | 179 + llvm/test/Transforms/InstCombine/broadcast.ll | 4 +- .../Transforms/InstCombine/bswap-inseltpoison.ll | 867 + llvm/test/Transforms/InstCombine/cast.ll | 8 +- llvm/test/Transforms/InstCombine/ctpop.ll | 6 +- .../InstCombine/extractelement-inseltpoison.ll | 332 + .../Transforms/InstCombine/fmul-inseltpoison.ll | 1176 + .../InstCombine/fold-vector-zero-inseltpoison.ll | 35 + llvm/test/Transforms/InstCombine/getelementptr.ll | 40 +- .../hoist-xor-by-constant-from-xor-by-value.ll | 89 + .../InstCombine/icmp-bc-vec-inseltpoison.ll | 127 + .../InstCombine/icmp-vec-inseltpoison.ll | 375 + .../InstCombine/inselt-binop-inseltpoison.ll | 635 + .../Transforms/InstCombine/insert-const-shuf.ll | 18 +- .../insert-extract-shuffle-inseltpoison.ll | 735 + .../InstCombine/insert-extract-shuffle.ll | 14 +- .../invert-variable-mask-in-masked-merge-scalar.ll | 5 +- .../invert-variable-mask-in-masked-merge-vector.ll | 5 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 192 +- llvm/test/Transforms/InstCombine/load.ll | 18 +- .../InstCombine/logical-select-inseltpoison.ll | 637 + .../InstCombine/masked_intrinsics-inseltpoison.ll | 271 + .../Transforms/InstCombine/masked_intrinsics.ll | 8 +- llvm/test/Transforms/InstCombine/minmax-fold.ll | 2 +- .../Transforms/InstCombine/mul-inseltpoison.ll | 1108 + .../Transforms/InstCombine/nsw-inseltpoison.ll | 142 + .../InstCombine/obfuscated_splat-inseltpoison.ll | 11 + llvm/test/Transforms/InstCombine/or-xor.ll | 68 +- .../InstCombine/pr2645-0-inseltpoison.ll | 34 + llvm/test/Transforms/InstCombine/pr2645-0.ll | 3 +- .../Transforms/InstCombine/pr38984-inseltpoison.ll | 41 + .../InstCombine/scalarization-inseltpoison.ll | 335 + llvm/test/Transforms/InstCombine/select-and-or.ll | 87 + .../select-extractelement-inseltpoison.ll | 213 + llvm/test/Transforms/InstCombine/select_meta.ll | 4 +- .../InstCombine/shift-add-inseltpoison.ll | 122 + .../InstCombine/shuffle-cast-inseltpoison.ll | 123 + .../shuffle-select-narrow-inseltpoison.ll | 144 + .../InstCombine/shuffle_select-inseltpoison.ll | 1467 + llvm/test/Transforms/InstCombine/shuffle_select.ll | 22 +- .../InstCombine/shufflevec-bitcast-inseltpoison.ll | 169 + .../shufflevec-constant-inseltpoison.ll | 17 + .../shufflevector-div-rem-inseltpoison.ll | 122 + .../InstCombine/shufflevector-div-rem.ll | 2 +- llvm/test/Transforms/InstCombine/store.ll | 25 +- .../InstCombine/sub-of-negatible-inseltpoison.ll | 1406 + .../Transforms/InstCombine/sub-of-negatible.ll | 2 +- .../trunc-extractelement-inseltpoison.ll | 195 + .../Transforms/InstCombine/trunc-inseltpoison.ll | 1023 + llvm/test/Transforms/InstCombine/trunc.ll | 2 +- .../InstCombine/type_pun-inseltpoison.ll | 155 + .../InstCombine/udiv-pow2-vscale-inseltpoison.ll | 27 + .../unfold-masked-merge-with-const-mask-scalar.ll | 6 +- .../unfold-masked-merge-with-const-mask-vector.ll | 6 +- .../InstCombine/vec-binop-select-inseltpoison.ll | 287 + .../InstCombine/vec_demanded_elts-inseltpoison.ll | 850 + .../Transforms/InstCombine/vec_demanded_elts.ll | 44 +- .../vec_extract_var_elt-inseltpoison.ll | 26 + .../InstCombine/vec_gep_scalar_arg-inseltpoison.ll | 16 + .../InstCombine/vec_phi_extract-inseltpoison.ll | 107 + .../InstCombine/vec_shuffle-inseltpoison.ll | 1791 + llvm/test/Transforms/InstCombine/vec_shuffle.ll | 64 +- .../InstCombine/vector-casts-inseltpoison.ll | 413 + llvm/test/Transforms/InstCombine/vector-casts.ll | 2 +- .../vector-concat-binop-inseltpoison.ll | 282 + .../InstCombine/vector_gep1-inseltpoison.ll | 74 + .../vector_insertelt_shuffle-inseltpoison.ll | 93 + .../InstCombine/vector_insertelt_shuffle.ll | 22 +- .../vscale_extractelement-inseltpoison.ll | 185 + .../vscale_insertelement-inseltpoison.ll | 102 + llvm/test/Transforms/InstCombine/xor2.ll | 44 +- .../ConstProp/InsertElement-inseltpoison.ll | 52 + .../ConstProp/vector-undef-elts-inseltpoison.ll | 69 + .../InstSimplify/ConstProp/vscale-inseltpoison.ll | 301 + .../ConstProp/vscale-shufflevector-inseltpoison.ll | 39 + llvm/test/Transforms/InstSimplify/call.ll | 62 +- .../Transforms/InstSimplify/select-inseltpoison.ll | 1007 + .../InstSimplify/shufflevector-inseltpoison.ll | 286 + .../Transforms/InstSimplify/vscale-inseltpoison.ll | 199 + .../AArch64/binopshuffles-inseltpoison.ll | 151 + ...terleaved-accesses-extract-user-inseltpoison.ll | 113 + .../AArch64/interleaved-accesses-inseltpoison.ll | 801 + ...terleaved-accesses-extract-user-inseltpoison.ll | 113 + .../ARM/interleaved-accesses-inseltpoison.ll | 1432 + ...interleaved-accesses-64bits-avx-inseltpoison.ll | 243 + .../X86/interleavedLoad-inseltpoison.ll | 158 + .../X86/interleavedStore-inseltpoison.ll | 243 + .../test/Transforms/JumpThreading/thread-prob-3.ll | 4 +- .../AMDGPU/adjust-alloca-alignment.ll | 35 +- .../AMDGPU/selects-inseltpoison.ll | 95 + .../X86/load-width-inseltpoison.ll | 40 + .../X86/vectorize-i8-nested-add-inseltpoison.ll | 165 + .../LoopDeletion/noop-loops-with-subloops.ll | 172 + .../LoopIdiom/X86/left-shift-until-bittest.ll | 1784 +- .../LoopSimplify/do-preheader-dbg-inseltpoison.ll | 122 + .../AMDGPU/lsr-void-inseltpoison.ll | 37 + .../ARM/vctp-chains-inseltpoison.ll | 257 + .../p8-unrolling-legalize-vectors-inseltpoison.ll | 256 + .../LoopUnroll/X86/pr46430-inseltpoison.ll | 23 + .../SystemZ/predicated-first-order-recurrence.ll | 6 +- .../LoopVectorize/X86/invariant-load-gather.ll | 4 +- llvm/test/Transforms/LoopVectorize/control-flow.ll | 2 +- .../LoopVectorize/first-order-recurrence.ll | 6 +- llvm/test/Transforms/LoopVectorize/induction.ll | 2 +- llvm/test/Transforms/LoopVectorize/loop-form.ll | 541 +- .../LoopVectorize/loop-legality-checks.ll | 23 +- .../LoopVectorize/reduction-inloop-pred.ll | 2 +- .../Transforms/LoopVectorize/reduction-inloop.ll | 2 +- .../LoopVectorize/skeleton-lcssa-crash.ll | 137 + ...08-30-MaskedScatterGather-xfail-inseltpoison.ll | 43 + .../PGOProfile/counter_promo_nest-inseltpoison.ll | 165 + .../PhaseOrdering/X86/addsub-inseltpoison.ll | 101 + .../PhaseOrdering/X86/horiz-math-inseltpoison.ll | 153 + .../Transforms/PhaseOrdering/X86/horiz-math.ll | 2 +- .../X86/scalarization-inseltpoison.ll | 71 + .../PhaseOrdering/X86/shuffle-inseltpoison.ll | 319 + .../PhaseOrdering/vector-trunc-inseltpoison.ll | 23 + .../base-vector-inseltpoison.ll | 279 + .../check_traversal_order-inseltpoison.ll | 38 + .../live-vector-nosplit-inseltpoison.ll | 119 + .../accelerate-vector-functions-inseltpoison.ll | 1300 + .../SLPVectorizer/AArch64/getelementptr.ll | 6 +- .../AArch64/insertelement-inseltpoison.ll | 44 + .../AArch64/transpose-inseltpoison.ll | 294 + .../AMDGPU/add_sub_sat-inseltpoison.ll | 336 + .../SLPVectorizer/AMDGPU/bswap-inseltpoison.ll | 38 + .../SLPVectorizer/AMDGPU/round-inseltpoison.ll | 38 + .../ARM/extract-insert-inseltpoison.ll | 31 + .../non-vectorizable-intrinsic-inseltpoison.ll | 57 + .../SLPVectorizer/X86/PR35865-inseltpoison.ll | 29 + .../X86/alternate-calls-inseltpoison.ll | 65 + .../X86/alternate-cast-inseltpoison.ll | 466 + .../Transforms/SLPVectorizer/X86/alternate-cast.ll | 4 +- .../SLPVectorizer/X86/alternate-fp-inseltpoison.ll | 179 + .../X86/alternate-int-inseltpoison.ll | 497 + .../SLPVectorizer/X86/arith-fp-inseltpoison.ll | 1365 + .../X86/blending-shuffle-inseltpoison.ll | 200 + .../SLPVectorizer/X86/cmp_commute-inseltpoison.ll | 283 + .../X86/crash_scheduling-inseltpoison.ll | 81 + .../X86/external_user_jumbled_load-inseltpoison.ll | 43 + .../X86/extract-shuffle-inseltpoison.ll | 22 + llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll | 147 + llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll | 147 + .../SLPVectorizer/X86/fptosi-inseltpoison.ll | 534 + .../SLPVectorizer/X86/hadd-inseltpoison.ll | 433 + .../SLPVectorizer/X86/hsub-inseltpoison.ll | 433 + .../insert-element-build-vector-inseltpoison.ll | 540 + .../SLPVectorizer/X86/load-merge-inseltpoison.ll | 208 + .../SLPVectorizer/X86/pr31599-inseltpoison.ll | 30 + .../SLPVectorizer/X86/pr42022-inseltpoison.ll | 278 + .../SLPVectorizer/X86/pr44067-inseltpoison.ll | 118 + .../SLPVectorizer/X86/pr47629-inseltpoison.ll | 664 + .../SLPVectorizer/X86/sext-inseltpoison.ll | 1039 + .../SLPVectorizer/X86/sign-extend-inseltpoison.ll | 62 + .../SLPVectorizer/X86/sitofp-inseltpoison.ll | 1331 + .../SLPVectorizer/X86/value-bug-inseltpoison.ll | 108 + .../X86/vec_list_bias-inseltpoison.ll | 105 + .../SLPVectorizer/X86/zext-inseltpoison.ll | 1123 + .../vectorizable-functions-inseltpoison.ll | 78 + .../Transforms/Scalarizer/basic-inseltpoison.ll | 561 + .../Scalarizer/dbgloc-bug-inseltpoison.ll | 44 + .../Scalarizer/order-bug-inseltpoison.ll | 24 + .../Transforms/Scalarizer/phi-bug-inseltpoison.ll | 25 + .../ARM/speculate-vector-ops-inseltpoison.ll | 112 + .../SimplifyCFG/fold-branch-to-common-dest.ll | 54 + .../speculate-vector-ops-inseltpoison.ll | 60 + .../spec-other-inseltpoison.ll | 88 + .../rebuild-ssa-infinite-loop-inseltpoison.ll | 53 + .../AArch64/vscale-bitcast-shuffle-inseltpoison.ll | 21 + .../AMDGPU/as-transition-inseltpoison.ll | 36 + .../VectorCombine/Hexagon/load-inseltpoison.ll | 17 + .../X86/extract-binop-inseltpoison.ll | 575 + .../VectorCombine/X86/insert-binop-inseltpoison.ll | 234 + .../X86/insert-binop-with-constant-inseltpoison.ll | 728 + .../VectorCombine/X86/load-inseltpoison.ll | 649 + .../VectorCombine/X86/no-sse-inseltpoison.ll | 15 + .../X86/scalarize-cmp-inseltpoison.ll | 290 + .../VectorCombine/X86/shuffle-inseltpoison.ll | 152 + llvm/test/tools/llvm-readobj/ELF/file-types.test | 10 +- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml | 21 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-cov/CodeCoverage.cpp | 11 +- llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objcopy/COFF/Object.cpp | 19 +- llvm/tools/llvm-objcopy/MachO/Object.cpp | 4 +- llvm/tools/llvm-objcopy/wasm/Object.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 115 +- llvm/tools/llvm-size/llvm-size.cpp | 4 +- llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp | 6 +- llvm/tools/obj2yaml/elf2yaml.cpp | 26 +- llvm/tools/opt/opt.cpp | 8 +- llvm/unittests/ADT/SmallVectorTest.cpp | 25 + .../Analysis/IRSimilarityIdentifierTest.cpp | 190 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 182 + llvm/unittests/Support/KnownBitsTest.cpp | 14 + llvm/unittests/Support/TargetParserTest.cpp | 19 +- llvm/utils/TableGen/AsmWriterEmitter.cpp | 6 +- llvm/utils/TableGen/DirectiveEmitter.cpp | 6 +- llvm/utils/TableGen/InstrInfoEmitter.cpp | 5 +- llvm/utils/gn/secondary/clang/unittests/BUILD.gn | 2 +- .../gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 1 + llvm/utils/update_analyze_test_checks.py | 5 +- mlir/docs/ConversionToLLVMDialect.md | 467 - mlir/docs/Dialects/SPIR-V.md | 2 +- mlir/docs/LLVMDialectMemRefConvention.md | 439 + mlir/docs/Passes.md | 4 + mlir/docs/Tutorials/Toy/Ch-2.md | 4 +- .../standalone/include/Standalone/StandaloneOps.h | 1 + mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 21 +- mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp | 21 +- .../mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h | 29 - .../Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h | 30 - .../mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h | 29 + .../mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h | 29 + .../mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h | 4 +- .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h | 4 +- mlir/include/mlir/Conversion/Passes.h | 9 +- mlir/include/mlir/Conversion/Passes.td | 17 + .../mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h | 4 +- .../mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h | 25 + .../Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h | 60 - .../SPIRVToLLVM/ConvertSPIRVToLLVMPass.h | 38 - .../mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h | 60 + .../mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h | 38 + .../StandardToLLVM/ConvertStandardToLLVM.h | 13 +- .../StandardToSPIRV/ConvertStandardToSPIRV.h | 35 - .../StandardToSPIRV/ConvertStandardToSPIRVPass.h | 28 - .../Conversion/StandardToSPIRV/StandardToSPIRV.h | 35 + .../StandardToSPIRV/StandardToSPIRVPass.h | 28 + .../VectorToSPIRV/ConvertVectorToSPIRV.h | 29 - .../VectorToSPIRV/ConvertVectorToSPIRVPass.h | 25 - .../mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h | 29 + .../Conversion/VectorToSPIRV/VectorToSPIRVPass.h | 25 + mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h | 1 + mlir/include/mlir/Dialect/ArmNeon/ArmNeonDialect.h | 1 + mlir/include/mlir/Dialect/GPU/GPUOps.td | 35 + mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 32 +- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 182 +- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 9 +- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 5 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h | 31 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 1 + mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/include/mlir/IR/FunctionSupport.h | 52 +- mlir/include/mlir/IR/ImplicitLocOpBuilder.h | 123 + mlir/include/mlir/IR/OpBase.td | 105 +- mlir/include/mlir/IR/OpDefinition.h | 60 +- mlir/include/mlir/TableGen/Type.h | 3 + .../include/mlir/Target/LLVMIR/ModuleTranslation.h | 3 + .../AffineToStandard/AffineToStandard.cpp | 125 +- mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 716 +- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 105 +- mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h | 24 +- .../GPUCommon/IndexIntrinsicsOpLowering.h | 13 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 14 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 8 +- mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt | 8 +- .../Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp | 347 - .../GPUToSPIRV/ConvertGPUToSPIRVPass.cpp | 73 - mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp | 348 + mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp | 70 + .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 106 +- mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp | 2 +- mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt | 2 +- .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp | 2 +- .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp | 2 +- mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt | 5 +- mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp | 5 +- mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp | 51 + mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt | 4 +- .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp | 11 +- .../Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp | 1559 - .../SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp | 61 - mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp | 1561 + .../lib/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.cpp | 61 + .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 263 +- mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt | 6 +- .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 1127 - .../StandardToSPIRV/ConvertStandardToSPIRVPass.cpp | 50 - .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 4 +- .../Conversion/StandardToSPIRV/StandardToSPIRV.cpp | 1131 + .../StandardToSPIRV/StandardToSPIRVPass.cpp | 49 + .../VectorToLLVM/ConvertVectorToLLVM.cpp | 55 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 10 +- mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt | 1 + .../lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp | 43 +- .../Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp | 53 + mlir/lib/Dialect/GPU/IR/GPUDialect.cpp | 18 + mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 248 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 283 +- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 22 +- mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 12 +- mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td | 30 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp | 35 + .../Dialect/SPIRV/Transforms/SPIRVConversion.cpp | 12 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 108 +- mlir/lib/Dialect/Vector/VectorTransforms.cpp | 5 +- mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- mlir/lib/ExecutionEngine/JitRunner.cpp | 19 +- mlir/lib/IR/Value.cpp | 5 + mlir/lib/TableGen/Type.cpp | 5 + mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 45 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 136 +- mlir/lib/Target/SPIRV/Deserialization.cpp | 106 + mlir/lib/Target/SPIRV/Serialization.cpp | 62 +- .../Conversion/AffineToStandard/lower-affine.mlir | 125 + .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + .../lower-memcpy-to-gpu-runtime-calls.mlir | 19 + ...est_spirv_entry_point.mlir => entry-point.mlir} | 0 mlir/test/Conversion/GPUToSPIRV/if.mlir | 167 - mlir/test/Conversion/GPUToSPIRV/loop.mlir | 98 - mlir/test/Conversion/SCFToSPIRV/for.mlir | 86 + mlir/test/Conversion/SCFToSPIRV/if.mlir | 156 + .../StandardToSPIRV/std-ops-to-spirv.mlir | 26 + mlir/test/Dialect/GPU/invalid.mlir | 14 + mlir/test/Dialect/GPU/ops.mlir | 11 + mlir/test/Dialect/LLVMIR/invalid.mlir | 8 +- .../SPIRV/Transforms/glsl_canonicalize.mlir | 113 + mlir/test/Dialect/Vector/canonicalize.mlir | 47 + mlir/test/Target/openmp-llvm.mlir | 34 +- mlir/test/lib/Dialect/SPIRV/CMakeLists.txt | 1 + .../lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp | 39 + mlir/test/lib/Transforms/TestConvertCallOp.cpp | 3 +- mlir/test/mlir-cpu-runner/async-value.mlir | 81 + .../mlir-cuda-runner/cuda-runtime-wrappers.cpp | 7 + mlir/tools/mlir-opt/mlir-opt.cpp | 2 + .../mlir-rocm-runner/rocm-runtime-wrappers.cpp | 5 + .../mlir-spirv-cpu-runner.cpp | 4 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 9 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 50 +- .../mlir-vulkan-runner/mlir-vulkan-runner.cpp | 4 +- openmp/docs/SupportAndFAQ.rst | 50 +- openmp/docs/design/Runtimes.rst | 82 + 1240 files changed, 726129 insertions(+), 471659 deletions(-) delete mode 100644 clang/test/CodeGenCXX/template-arguments.cpp create mode 100644 clang/test/CodeGenObjC/objc-dispatch-null-check.m delete mode 100644 clang/test/SemaTemplate/instantiation-dependence.cpp delete mode 100644 clang/test/SemaTemplate/temp_arg_nontype_cxx17.cpp create mode 100644 clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 libcxx/test/std/utilities/function.objects/func.invoke/invoke_c [...] create mode 100644 llvm/include/llvm/Transforms/Scalar/InferAddressSpaces.h create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll create mode 100644 llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltp [...] create mode 100644 llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll create mode 100644 llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismat [...] create mode 100644 llvm/test/CodeGen/AArch64/ctpop-nonean.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-rev.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll create mode 100644 llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir create mode 100644 llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir create mode 100644 llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll create mode 100644 llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll create mode 100644 llvm/test/CodeGen/PowerPC/pr48519.ll create mode 100644 llvm/test/CodeGen/PowerPC/pr48527.ll create mode 100644 llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll create mode 100644 llvm/test/CodeGen/Thumb2/schedm7-hazard.ll create mode 100644 llvm/test/CodeGen/VE/Vector/vec_and.ll create mode 100644 llvm/test/CodeGen/X86/basic-block-sections_2.ll create mode 100644 llvm/test/CodeGen/X86/dwarf_eh_resume.ll create mode 100644 llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll delete mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_all.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_ds.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_flat.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_smem.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_sop.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vop3.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vopc.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s create mode 100644 llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s delete mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_all.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_ds.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_exp.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_flat.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_mimg.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_smrd.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_sop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_sop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_sopc.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_sopk.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_sopp.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vop3.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s create mode 100644 llvm/test/MC/AMDGPU/gfx7_asm_vopc.s delete mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_all.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_ds.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_exp.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_flat.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_mimg.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_smem.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_sop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_sop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_sopc.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_sopk.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_sopp.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vop3.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s create mode 100644 llvm/test/MC/AMDGPU/gfx8_asm_vopc.s delete mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_all.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_ds.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_exp.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_flat.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_mimg.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_smem.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_sop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_sop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_sopc.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_sopk.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_sopp.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vop3.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s create mode 100644 llvm/test/MC/AMDGPU/gfx9_asm_vopc.s delete mode 100644 llvm/test/Object/elf-unknown-type.test create mode 100644 llvm/test/TableGen/substr.td create mode 100644 llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll create mode 100644 llvm/test/Transforms/BDCE/vectors-inseltpoison.ll create mode 100644 llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt- [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/AArch64/sink-free-instructi [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debu [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevec [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sink-free-instructions- [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-insel [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inse [...] create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inselt [...] create mode 100644 llvm/test/Transforms/DeadStoreElimination/masked-dead-store-ins [...] create mode 100644 llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltp [...] create mode 100644 llvm/test/Transforms/GVN/PRE/modified-status.ll create mode 100644 llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash- [...] create mode 100644 llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-commutative.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll create mode 100644 llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regress [...] create mode 100644 llvm/test/Transforms/InferFunctionAttrs/dereferenceable-inseltp [...] create mode 100755 llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/AArch64/sve-bitcast-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector- [...] create mode 100644 llvm/test/Transforms/InstCombine/X86/shufflemask-undef-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-avx2-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pshufb-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inse [...] create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/assume-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/bswap-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/fold-vector-zero-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor [...] create mode 100644 llvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/icmp-vec-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltp [...] create mode 100644 llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/mul-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/nsw-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/obfuscated_splat-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/pr2645-0-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/pr38984-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/select-and-or.ll create mode 100644 llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shuffle-cast-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shuffle-select-narrow-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/udiv-pow2-vscale-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec-binop-select-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vector-concat-binop-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vector_insertelt_shuffle-insel [...] create mode 100644 llvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/InsertElement-insel [...] create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-i [...] create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevecto [...] create mode 100644 llvm/test/Transforms/InstSimplify/select-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstSimplify/shufflevector-inseltpoison.ll create mode 100644 llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-in [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-acce [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-acce [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inse [...] create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-ins [...] create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltp [...] create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/X86/load-width-inseltp [...] create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-neste [...] create mode 100644 llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll create mode 100755 llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll create mode 100644 llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltp [...] create mode 100644 llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltp [...] create mode 100644 llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-v [...] create mode 100644 llvm/test/Transforms/LoopUnroll/X86/pr46430-inseltpoison.ll create mode 100644 llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll create mode 100644 llvm/test/Transforms/NewGVN/2016-08-30-MaskedScatterGather-xfai [...] create mode 100644 llvm/test/Transforms/PGOProfile/counter_promo_nest-inseltpoison.ll create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll create mode 100644 llvm/test/Transforms/PhaseOrdering/vector-trunc-inseltpoison.ll create mode 100644 llvm/test/Transforms/RewriteStatepointsForGC/base-vector-inselt [...] create mode 100644 llvm/test/Transforms/RewriteStatepointsForGC/check_traversal_or [...] create mode 100644 llvm/test/Transforms/RewriteStatepointsForGC/live-vector-nospli [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-fu [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inselt [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intri [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltp [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltp [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_lo [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vec [...] create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/vectorizable-functions-insel [...] create mode 100644 llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll create mode 100644 llvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/Scalarizer/phi-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops-insel [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/speculate-vector-ops-inseltpoison.ll create mode 100644 llvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll create mode 100644 llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-i [...] create mode 100644 llvm/test/Transforms/VectorCombine/AArch64/vscale-bitcast-shuff [...] create mode 100644 llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltp [...] create mode 100644 llvm/test/Transforms/VectorCombine/Hexagon/load-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/insert-binop-with-consta [...] create mode 100644 llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/no-sse-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/scalarize-cmp-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/shuffle-inseltpoison.ll create mode 100644 mlir/docs/LLVMDialectMemRefConvention.md delete mode 100644 mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h delete mode 100644 mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h create mode 100644 mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h create mode 100644 mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h create mode 100644 mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h delete mode 100644 mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h delete mode 100644 mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h create mode 100644 mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h create mode 100644 mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h delete mode 100644 mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h delete mode 100644 mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToS [...] create mode 100644 mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h create mode 100644 mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h delete mode 100644 mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRV.h delete mode 100644 mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h create mode 100644 mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h create mode 100644 mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h create mode 100644 mlir/include/mlir/IR/ImplicitLocOpBuilder.h delete mode 100644 mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp delete mode 100644 mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp create mode 100644 mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp create mode 100644 mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp create mode 100644 mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp delete mode 100644 mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp delete mode 100644 mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp create mode 100644 mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp create mode 100644 mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.cpp delete mode 100644 mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp delete mode 100644 mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.cpp create mode 100644 mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp create mode 100644 mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRVPass.cpp create mode 100644 mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp create mode 100644 mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp create mode 100644 mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir rename mlir/test/Conversion/GPUToSPIRV/{test_spirv_entry_point.mlir => entry-point [...] delete mode 100644 mlir/test/Conversion/GPUToSPIRV/if.mlir delete mode 100644 mlir/test/Conversion/GPUToSPIRV/loop.mlir create mode 100644 mlir/test/Conversion/SCFToSPIRV/for.mlir create mode 100644 mlir/test/Conversion/SCFToSPIRV/if.mlir create mode 100644 mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir create mode 100644 mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir