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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig in repository toolchain/ci/llvm-project.
from 99464b7eb1d [clangd][Hover] Change arrow in return type back to → adds 01fd650ba3d [RISCV] Pass target-abi via module flag metadata adds 7c5784746cf [RISCV] Check the target-abi module flag matches the option adds 4d342b7d8e9 Revert "[RISCV] Support ABI checking with per function targ [...] adds 72882ca30d8 [RISCV] Support ABI checking with per function target-features adds c23212a438f [IR] Keep a double break between functions when printing a module adds 87c7863c3ec Reland "[StackColoring] Remap PseudoSourceValue frame indic [...] adds 6472fec9a69 [clangd][Hover] Handle uninstantiated templates adds 54b022d3444 [lldb] Fix nondeterminism in TestCppBitfields
No new revisions were added by this update.
Summary of changes: clang-tools-extra/clangd/Hover.cpp | 27 ++++++++++++++-------- clang-tools-extra/clangd/unittests/HoverTests.cpp | 19 +++++++++++++++ clang/lib/CodeGen/CodeGenModule.cpp | 7 ++++++ clang/test/CodeGen/riscv-metadata.c | 14 +++++++++++ .../test/lang/cpp/bitfields/TestCppBitfields.py | 2 +- .../lldbsuite/test/lang/cpp/bitfields/main.cpp | 2 +- llvm/lib/CodeGen/StackColoring.cpp | 16 +++++++------ llvm/lib/IR/AsmWriter.cpp | 4 +++- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 ++-- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 +++++++++-- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 24 +++++++++++-------- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 ++ llvm/test/CodeGen/RISCV/module-target-abi.ll | 24 +++++++++++++++++++ llvm/test/CodeGen/RISCV/module-target-abi2.ll | 27 ++++++++++++++++++++++ llvm/test/Feature/undefined.ll | 13 +++++++++++ 15 files changed, 167 insertions(+), 33 deletions(-) create mode 100644 clang/test/CodeGen/riscv-metadata.c create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi.ll create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi2.ll