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from 3d4f91d8d07 [GlobalISel] Introduce a CSEConfigBase class to allow targe [...] new 040f61e1172 [GlobalISel] Enable CSE in the IRTranslator & legalizer for [...]
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Summary of changes: lib/CodeGen/GlobalISel/CSEInfo.cpp | 2 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 18 +- lib/CodeGen/GlobalISel/Legalizer.cpp | 1 + lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- lib/CodeGen/TargetPassConfig.cpp | 2 +- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 5 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 28 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 29 +- .../AArch64/GlobalISel/call-translator-ios.ll | 2 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 3 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 8 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 5 +- .../legalize-load-store-s128-unaligned.mir | 3 +- .../AArch64/GlobalISel/legalize-merge-values.mir | 3 +- test/CodeGen/AArch64/GlobalISel/legalize-phi.mir | 3 +- test/CodeGen/AArch64/GlobalISel/legalize-rem.mir | 5 +- test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 15 +- test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 10 +- test/CodeGen/AArch64/GlobalISel/translate-gep.ll | 21 +- .../AMDGPU/GlobalISel/legalize-addrspacecast.mir | 34 +-- test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 240 +++++++---------- test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir | 6 +- .../AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir | 9 +- test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 9 +- test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir | 6 +- .../AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 9 +- test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 240 +++++++---------- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 37 ++- test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 300 +++++++++------------ test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 18 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 133 ++++----- test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 18 +- .../ARM/GlobalISel/arm-legalize-bitcounts.mir | 2 - .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 8 - test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 16 +- .../ARM/GlobalISel/arm-legalize-load-store.mir | 12 +- test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 12 +- test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 30 +-- .../Mips/GlobalISel/legalizer/rem_and_div.mir | 92 +++---- test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 12 +- test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll | 16 +- test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll | 40 ++- .../CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll | 36 ++- test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll | 20 +- test/CodeGen/X86/GlobalISel/add-ext.ll | 79 +++--- test/CodeGen/X86/GlobalISel/gep.ll | 16 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 38 +-- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 3 +- .../x86_64-irtranslator-struct-return.ll | 39 ++- 52 files changed, 697 insertions(+), 1016 deletions(-)