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from f64b91568f3 rs6000: Enable 32bit variable vec_insert [PR99718] new 19199a6f2b0 aarch64: PR target/99822 Don't allow zero register in first [...]
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Summary of changes: gcc/config/aarch64/aarch64.md | 2 +- gcc/testsuite/gcc.c-torture/compile/pr99822.c | 41 +++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr99822.c