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from e8c83ab9d51 RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE new 2985049049f rs6000: Don't ICE when we disassemble an MMA variable [PR101322]
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Summary of changes: gcc/config/rs6000/rs6000-builtin.cc | 7 ++++++- gcc/testsuite/g++.target/powerpc/pr101322.C | 17 +++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/powerpc/pr101322.C