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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from 5316e12bb2 Merge tag 'dbus-pull-request' of https://gitlab.com/marcandr [...] adds e788cd2972 elf: Add machine type value for LoongArch adds afa33258f3 MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer adds 6cb14e4de2 tcg/loongarch64: Add the tcg-target.h file adds 71bb0283f5 tcg/loongarch64: Add generated instruction opcodes and encod [...] adds 1bcfbf03df tcg/loongarch64: Add register names, allocation order and in [...] adds ba0cdd8040 tcg/loongarch64: Define the operand constraints adds bf8c1c8140 tcg/loongarch64: Implement necessary relocation operations adds fae2361dc9 tcg/loongarch64: Implement the memory barrier op adds dacc51720d tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi adds e3b15766b9 tcg/loongarch64: Implement goto_ptr adds 6be08fcfc3 tcg/loongarch64: Implement sign-/zero-extension ops adds 97b2fafbf7 tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops adds 7257809f62 tcg/loongarch64: Implement deposit/extract ops adds 4ab2aff0db tcg/loongarch64: Implement bswap{16,32,64} ops adds fde6930160 tcg/loongarch64: Implement clz/ctz ops adds a164010b05 tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops adds 39f54ce5c4 tcg/loongarch64: Implement add/sub ops adds ff13c19689 tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops adds 94505c02f4 tcg/loongarch64: Implement br/brcond ops adds 9ee775cf29 tcg/loongarch64: Implement setcond ops adds a26d99d72f tcg/loongarch64: Implement tcg_out_call adds 251ebcd812 tcg/loongarch64: Implement simple load/store ops adds d3a1727c19 tcg/loongarch64: Add softmmu load/store helpers, implement q [...] adds 697a598059 tcg/loongarch64: Implement tcg_target_qemu_prologue adds 30d420e4d3 tcg/loongarch64: Implement exit_tb/goto_tb adds 8df89cf0ae tcg/loongarch64: Implement tcg_target_init adds a9ae47486a tcg/loongarch64: Register the JIT adds 6016b7b46e common-user: Add safe syscall handling for loongarch64 hosts adds ad812c3bd6 linux-user: Implement CPU-specific signal handler for loonga [...] adds dfcf900ba6 configure, meson.build: Mark support for loongarch64 hosts adds 8c5f94cd41 Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7 [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 5 + .../host/{riscv => loongarch64}/safe-syscall.inc.S | 53 +- configure | 5 + include/elf.h | 2 + linux-user/host/loongarch64/host-signal.h | 87 + meson.build | 2 +- tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++++++++ tcg/{riscv => loongarch64}/tcg-target-con-set.h | 25 +- tcg/{riscv => loongarch64}/tcg-target-con-str.h | 11 +- tcg/loongarch64/tcg-target.c.inc | 1677 ++++++++++++++++++++ tcg/{riscv => loongarch64}/tcg-target.h | 127 +- 11 files changed, 2876 insertions(+), 97 deletions(-) copy common-user/host/{riscv => loongarch64}/safe-syscall.inc.S (66%) create mode 100644 linux-user/host/loongarch64/host-signal.h create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc copy tcg/{riscv => loongarch64}/tcg-target-con-set.h (64%) copy tcg/{riscv => loongarch64}/tcg-target-con-str.h (62%) create mode 100644 tcg/loongarch64/tcg-target.c.inc copy tcg/{riscv => loongarch64}/tcg-target.h (66%)