[Tcwg-commits] [toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os updated (fe7a351a8e -> a75a6a4164)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os in repository toolchain/ci/binutils-gdb.

from fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h adds 24a7f1b548 gdb: fix indentation in infrun.c adds 3034143dc6 src-release: fix indentation adds 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure

No new revisions were added by this update.

Summary of changes: ChangeLog | 4 + bfd/ChangeLog | 80 + bfd/Makefile.in | 1 + bfd/bfd-in2.h | 7 +- bfd/compress.c | 3 +- bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 5 +- bfd/elf32-bfin.c | 235 +- bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 202 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/section.c | 7 +- bfd/version.h | 2 +- binutils/ChangeLog | 31 + binutils/MAINTAINERS | 6 +- binutils/Makefile.in | 1 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/po/sv.po | 3804 +++++++++++--------- binutils/readelf.c | 8 +- gas/ChangeLog | 76 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 4 - gas/config/tc-i386.c | 42 +- gas/config/tc-riscv.c | 521 ++- gas/config/tc-riscv.h | 6 +- gas/doc/Makefile.in | 1 + gas/doc/as.texi | 7 - gas/dwarf2dbg.c | 24 +- gas/read.c | 3 + gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 168 + gdb/MAINTAINERS | 1 + gdb/arc-linux-nat.c | 16 +- gdb/arc-linux-tdep.c | 43 +- gdb/arc-newlib-tdep.c | 11 +- gdb/arc-tdep.c | 151 +- gdb/arc-tdep.h | 7 +- gdb/auto-load.c | 82 +- gdb/auto-load.h | 16 +- gdb/copyright.py | 2 +- gdb/extension-priv.h | 2 +- gdb/extension.c | 7 +- gdb/extension.h | 5 +- gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-auto-load.c | 5 +- gdb/infrun.c | 2 +- gdb/jit.c | 64 +- gdb/nat/amd64-linux-siginfo.c | 13 + gdb/objfiles.h | 3 +- gdb/python/py-auto-load.c | 5 +- gdb/python/python-internal.h | 5 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/remote.c | 412 ++- gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-tdep.c | 50 + gdb/riscv-tdep.h | 23 + gdb/testsuite/ChangeLog | 22 + gdb/testsuite/gdb.base/style.exp | 49 +- gdb/testsuite/gdb.fortran/array-slices.exp | 5 +- .../gdb.server/stop-reply-no-thread-multi.c | 77 + .../gdb.server/stop-reply-no-thread-multi.exp | 136 + gdb/trad-frame.c | 5 +- gdb/tui/tui.c | 4 +- gold/ChangeLog | 16 + gold/po/fr.po | 730 ++-- gold/powerpc.cc | 1 - gold/testsuite/ifuncmain6pie.c | 14 +- gold/testsuite/ifuncmod6.c | 10 +- gprof/ChangeLog | 4 + gprof/Makefile.in | 1 + include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 146 + ld/Makefile.in | 1 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/emultempl/aarch64elf.em | 2 +- ld/emultempl/armelf.em | 2 +- ld/emultempl/beos.em | 2 +- ld/emultempl/cskyelf.em | 2 +- ld/emultempl/hppaelf.em | 2 +- ld/emultempl/m68hc1xelf.em | 2 +- ld/emultempl/metagelf.em | 2 +- ld/emultempl/mipself.em | 2 +- ld/emultempl/mmo.em | 2 +- ld/emultempl/msp430.em | 5 +- ld/emultempl/nios2elf.em | 2 +- ld/emultempl/pe.em | 4 +- ld/emultempl/pep.em | 4 +- ld/emultempl/ppc64elf.em | 2 +- ld/emultempl/spuelf.em | 4 +- ld/emultempl/vms.em | 2 +- ld/ld.texi | 4 + ld/ldelf.c | 8 +- ld/ldelfgen.c | 252 +- ld/ldlang.c | 48 +- ld/ldlang.h | 11 +- ld/po/fr.po | 3699 ++++++++++--------- ld/testsuite/config/default.exp | 5 + ld/testsuite/ld-elf/compressed1d.d | 5 +- ld/testsuite/ld-elf/elf.exp | 13 + ld/testsuite/ld-elf/pr26256-2a.d | 1 - ld/testsuite/ld-elf/pr26256-2b.d | 3 +- ld/testsuite/ld-elf/pr26256-3b.d | 1 - ld/testsuite/ld-elf/size-2.d | 2 +- ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-i386/i386.exp | 6 + ld/testsuite/ld-i386/pr27193.dd | 5 + ld/testsuite/ld-i386/pr27193a.o.bz2 | Bin 0 -> 468 bytes ld/testsuite/ld-i386/pr27193b.s | 8 + ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + ld/testsuite/ld-ifunc/ifunc.exp | 22 +- ld/testsuite/ld-ifunc/pr23169a.c | 2 +- ld/testsuite/ld-plugin/lto.exp | 2 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- ld/testsuite/ld-x86-64/report-reloc-1-x32.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.l | 2 + ld/testsuite/ld-x86-64/report-reloc-1.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 2 + libctf/ChangeLog | 4 + libctf/Makefile.in | 1 + opcodes/ChangeLog | 20 + opcodes/Makefile.in | 1 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++---- sim/ChangeLog | 22 + sim/Makefile.in | 14 + sim/README-HACKING | 6 +- sim/common/ChangeLog | 29 + sim/common/Make-common.in | 5 +- sim/common/Makefile.in | 135 - sim/common/configure | 3718 ------------------- sim/common/configure.ac | 34 - sim/common/create-version.sh | 17 +- sim/common/gennltvals.sh | 321 +- sim/common/gentvals.sh | 74 - sim/common/nltvals.def | 7 + sim/common/sim-events.c | 4 +- sim/common/sim-events.h | 4 +- sim/common/sim-watch.c | 17 +- sim/configure | 195 +- sim/configure.ac | 17 +- sim/h8300/ChangeLog | 14 +- sim/h8300/compile.c | 91 +- sim/h8300/sim-main.h | 1 - sim/testsuite/ChangeLog | 41 + sim/testsuite/Makefile.in | 9 +- sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s 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}/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 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rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => 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=> }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename 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sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename 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