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from af884a78b16 Add test case peeking through vector concat when combining [...] new fd32ab2eb99 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops.
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Summary of changes: lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +++++++++++++- test/CodeGen/X86/avx512-cvt.ll | 17 ++- test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 ++++++++++++------------- test/CodeGen/X86/machine-combiner-int-vec.ll | 117 ++++++++++++-------- test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +-- test/CodeGen/X86/midpoint-int-vec-256.ll | 24 ++--- test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +++++++-------- test/CodeGen/X86/sadd_sat_vec.ll | 57 +++++++--- test/CodeGen/X86/ssub_sat_vec.ll | 57 +++++++--- test/CodeGen/X86/vec_int_to_fp.ll | 16 +-- test/CodeGen/X86/vector-bitreverse.ll | 43 ++++---- test/CodeGen/X86/vector-fshl-256.ll | 9 +- test/CodeGen/X86/vector-fshl-512.ll | 56 +++++----- test/CodeGen/X86/vector-fshl-rot-256.ll | 20 ++-- test/CodeGen/X86/vector-fshl-rot-512.ll | 42 ++++---- test/CodeGen/X86/vector-fshr-256.ll | 29 +++-- test/CodeGen/X86/vector-fshr-512.ll | 154 +++++++++++++-------------- test/CodeGen/X86/vector-fshr-rot-256.ll | 20 ++-- test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +++++++------- test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- test/CodeGen/X86/vector-rotate-128.ll | 77 +++++++++++--- test/CodeGen/X86/vector-rotate-256.ll | 69 +++++++----- test/CodeGen/X86/vector-rotate-512.ll | 92 +++++++--------- test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- test/CodeGen/X86/vector-shift-ashr-256.ll | 18 ++-- test/CodeGen/X86/vector-shift-ashr-512.ll | 18 ++-- test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- 27 files changed, 766 insertions(+), 589 deletions(-)