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from 8e8c64faa1f [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering new 2bd04d66a7c [SeparateConstOffsetFromGEP] Fix up addrspace in the AMDGPU test new f42f82fde05 [Hexagon] Implement HVX codegen for vector shifts new e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass.
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Summary of changes: lib/Target/Hexagon/HexagonISelLowering.cpp | 92 ++--- lib/Target/Hexagon/HexagonISelLowering.h | 1 + lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 6 + lib/Target/Hexagon/HexagonPatterns.td | 22 +- lib/Target/X86/X86.h | 2 +- lib/Target/X86/X86RetpolineThunks.cpp | 135 +++++--- test/CodeGen/Hexagon/autohvx/isel-build-undef.ll | 2 +- test/CodeGen/Hexagon/autohvx/shift-128b.ll | 376 +++++++++++++++++++++ test/CodeGen/Hexagon/autohvx/shift-64b.ll | 232 +++++++++++++ test/CodeGen/X86/O0-pipeline.ll | 3 +- ...split-gep-and-gvn-addrspace-addressing-modes.ll | 12 +- 11 files changed, 756 insertions(+), 127 deletions(-) create mode 100644 test/CodeGen/Hexagon/autohvx/shift-128b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/shift-64b.ll