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from f963705752e Fortran tests: Revise line end tests allowing windows testing. new 43122c45607 RISC-V: Remove redundant attributes [NFC] new eb1c2960184 RISC-V: Add vlse/vsse intrinsics support new caa87b98fc3 RISC-V: Add vlse/vsse C/C++ intrinsic testcases
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Summary of changes: gcc/config/riscv/predicates.md | 4 + gcc/config/riscv/riscv-vector-builtins-bases.cc | 26 +- gcc/config/riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/riscv-vector-builtins.cc | 33 +- gcc/config/riscv/vector.md | 108 +++- gcc/testsuite/g++.target/riscv/rvv/base/vlse-1.C | 345 +++++++++++ .../g++.target/riscv/rvv/base/vlse_tu-1.C | 345 +++++++++++ .../g++.target/riscv/rvv/base/vlse_tum-1.C | 345 +++++++++++ .../g++.target/riscv/rvv/base/vlse_tumu-1.C | 345 +++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vsse-1.C | 685 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse-3.c | 345 +++++++++++ .../riscv/rvv/base/vlse-vsse-constraint-1.c | 113 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_mu-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_mu-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_mu-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tu-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tu-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tu-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tum-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tum-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tum-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tumu-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tumu-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlse_tumu-3.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse-3.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-3.c | 345 +++++++++++ 36 files changed, 10600 insertions(+), 33 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlse-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlse_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlse_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlse_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsse-1.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse-vsse-constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsse_m-3.c