This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/llvm-project.
from 29ff1b4f465 [ARM] Fix integer UB in MVE load/store immediate handling. adds eb7080ac6e5 [ARM] Widening loads and narrowing stores adds 493a1202595 [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges adds 02e743586e9 [DebugInfo] Fix setStartAddress after r364637 adds fd0ad4b24d6 [ELF] Do not produce DT_JMPREL and DT_PLTGOT if .rela.plt i [...] adds ff70cbc8957 [ARM] MVE patterns for VABS and VNEG adds 28839440352 [ARM] Mark math routines as non-legal for MVE adds 9af44742538 [NFC][Codegen] Revisit test coverage for X % C == 0 fold adds 9dbdfe6b785 [ARM] Add MVE mul patterns adds a54e1a0f012 [X86] CombineShuffleWithExtract - only require 1 source to [...] adds 1d572ce3955 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg adds 13d9c723c89 [NFC][NewGVN] Pre-commit unary FNeg test to fpmath.ll adds 405f8fc812c [OPENMP]Fix checks for DSA in simd constructs. adds 40b88e07e2d [Hexagon] driver uses out-of-date option name and binary name adds 9fab46ca0bd [NFC][Float2Int] Pre-commit unary FNeg test to basic.ll adds b7c31ff4a22 [OPENMP]Fix DSA for loop iteration variables in simd loops. adds d12966c0883 [AMDGPU][MC] Fix for sanitizer failure in 364645 adds 9f1dffdb024 [NFC][InstCombine] Shift amount reassociation: add flag pre [...] adds 176b9f65168 [llvm-cov[ Fix lcov coverage report contains functions from [...] adds e39e958da36 [ARM] Add support for the MVE long shift instructions adds 73f9d9aa64b [OPENMP]Fix top DSA for static members. adds e1eb25ff3e5 [AMDGPU][MC] Fix 2 for sanitizer failure in 364645 adds 3b4f086df4a [NFC][InstCombine] Shift amount reassociation: revisit flag [...] adds 633d222d30b [WebAssembly] Added visibility and ident directives to Wasm [...] adds 5cbff431782 [COFF] Fix .rsrc sections with differing permissions adds 0b8b4195371 [NFC][Codegen] Revisit test coverage for X % C == 0 fold on [...] adds 5be69ebe121 [TSan] Improve handling of stack pointer mangling in {set,l [...] adds 021d2f20933 Update CODE_OWNERS.txt for clang-doc adds 5f8b9092fff [ODRHash] Fix null pointer dereference for ObjC selectors w [...] adds 7108df964aa hwasan: Remove the old frame descriptor mechanism. adds 8864b4360aa Make sure the thread list is updated before you set the sto [...] adds 978a08c8854 [X86] CombineShuffleWithExtract - recurse through EXTRACT_S [...] adds 7d78e5cc811 [UpdateChecks] Add support for armv7-apple-darwin adds 9db6073381d [GDBRemote] Remove code that flushes GDB remote packets adds 93a290fdc97 [clang-doc] De-duplicate comments and locations adds 36c3d1312a0 [unittests][Support] Fix LLVM-Unit :: Support/./SupportTest [...] adds 62a627ae781 Re-apply r364600 with fixes. adds 70a8027c60f [llvm-ar] Document response file support in --help adds d900ef0a5b1 [clang-doc] Handle anonymous namespaces adds 4b733ca617e Default to Secure PLT on PPC for musl libc. adds 1c6337ca5ab [TSan] Fix build build breakage on Android adds 9a6cef74d8a [demangle] Support for C++2a char8_t adds ab4b2364e56 [GVNSink] Add unary FNeg support to GVNSink pass adds 642fe780abe Revert enabling frame pointer elimination on OpenBSD for now. adds 30e5cf1d8f3 [NewGVN] Add unary FNeg support to NewGVN pass adds 597ba180086 [WebAssembly] Assembler: Improve section parsing. adds fc222e23cae [WebAssembly] Assembler: Allow offsets and p2align in symbol load. adds 1242d8f333a [OPENMP]Improve analysis of implicit captures. adds 573b241c68a [Lanai] auto-generate complete test checks; NFC adds b671535983f [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll adds f2128b28cdb Get the expression parser to handle missing weak symbols. M [...] adds 9126c84f50f [x86] remove stale comment about cmov; NFC adds 35bcba4fae8 [WebAssembly] Allow @object in .type directives. adds 319c87d94fd [WebAssembly] Assembler: support .int16/32/64 directives. adds caf4cee6fe8 [clang][test][NFC] Explicitly specify clang ABI in AST Dumper test adds 69d9c314337 AMDGPU: Add baseline test for packed shufflevector adds da47e2cac38 Revert "[clang][NewPM] Fix broken profile test" adds 1504b6ee7ea [IndVars] Remove a bit of manual constant folding [NFC] adds ade51624327 AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics adds 6aafb3068f9 AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas adds 5ea3c9adb27 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics adds b416d5fc8b8 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics adds adb1f21e521 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics adds fd82cf4f4d0 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec adds be4148062b1 [TSan] Attempt to fix linker error for Linux on AArch64 adds 0d452097571 AMDGPU/GlobalISel: RegBankSelect for update.dpp adds a83e94ebf26 Use const auto * adds 7889d4ce66f AMDGPU/GlobalISel: Add some more tests for icmp select adds 765eba38c8d [Driver] Fix style issues of --print-supported-cpus after D63105 adds b72664fd21c Partial revert of "[llvm-ar] Document response file support [...] new 2d756c4feb6 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang-tools-extra/CODE_OWNERS.TXT | 4 + clang-tools-extra/clang-doc/Representation.cpp | 39 + clang-tools-extra/clang-doc/Representation.h | 50 + clang-tools-extra/clang-doc/Serialize.cpp | 75 +- clang-tools-extra/clang-doc/tool/ClangDocMain.cpp | 7 +- .../unittests/clang-doc/MergeTest.cpp | 36 +- .../unittests/clang-doc/SerializeTest.cpp | 1 + clang/include/clang/Driver/Options.td | 6 +- clang/lib/AST/ODRHash.cpp | 7 +- clang/lib/CodeGen/BackendUtil.cpp | 6 - clang/lib/Driver/Driver.cpp | 20 +- clang/lib/Driver/ToolChains/Clang.cpp | 13 - clang/lib/Driver/ToolChains/Hexagon.cpp | 4 +- clang/lib/Frontend/CompilerInvocation.cpp | 2 +- clang/lib/Sema/SemaOpenMP.cpp | 82 +- .../AST/ast-dump-record-definition-data-json.cpp | 2 +- clang/test/Driver/frame-pointer-elim.c | 13 - clang/test/Driver/print-supported-cpus.c | 36 +- clang/test/Modules/odr_hash.mm | 31 + .../distribute_parallel_for_default_messages.cpp | 8 +- ...stribute_parallel_for_simd_default_messages.cpp | 8 +- clang/test/OpenMP/nvptx_lambda_capturing.cpp | 4 +- clang/test/OpenMP/simd_loop_messages.cpp | 32 +- .../target_parallel_for_default_messages.cpp | 4 +- .../target_parallel_for_simd_default_messages.cpp | 4 +- ...rget_teams_distribute_firstprivate_messages.cpp | 2 +- .../teams_distribute_firstprivate_messages.cpp | 2 +- .../teams_distribute_lastprivate_messages.cpp | 2 +- ...stribute_parallel_for_firstprivate_messages.cpp | 2 +- ...istribute_parallel_for_lastprivate_messages.cpp | 2 +- ..._distribute_parallel_for_reduction_messages.cpp | 4 +- ...stribute_parallel_for_simd_aligned_messages.cpp | 2 +- ...ute_parallel_for_simd_firstprivate_messages.cpp | 2 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 2 +- ...istribute_parallel_for_simd_linear_messages.cpp | 4 +- ...ribute_parallel_for_simd_reduction_messages.cpp | 4 +- .../OpenMP/teams_distribute_reduction_messages.cpp | 4 +- .../teams_distribute_simd_aligned_messages.cpp | 2 +- ...teams_distribute_simd_firstprivate_messages.cpp | 2 +- .../teams_distribute_simd_lastprivate_messages.cpp | 2 +- .../teams_distribute_simd_linear_messages.cpp | 4 +- .../teams_distribute_simd_reduction_messages.cpp | 4 +- clang/test/OpenMP/teams_firstprivate_messages.cpp | 2 +- clang/test/OpenMP/teams_reduction_messages.cpp | 4 +- clang/test/Profile/gcc-flag-compatibility.c | 12 +- clang/tools/driver/cc1_main.cpp | 9 +- compiler-rt/lib/tsan/rtl/tsan_interceptors.cc | 3 + compiler-rt/lib/tsan/rtl/tsan_platform.h | 1 + compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc | 34 + compiler-rt/lib/tsan/rtl/tsan_platform_mac.cc | 4 + compiler-rt/lib/tsan/rtl/tsan_rtl_aarch64.S | 8 - libcxxabi/src/demangle/ItaniumDemangle.h | 4 + libcxxabi/test/test_demangle.pass.cpp | 3 + lld/COFF/Writer.cpp | 32 +- lld/ELF/SyntheticSections.cpp | 2 +- lld/test/COFF/Inputs/id.res.o | Bin 0 -> 220 bytes lld/test/COFF/resource-objs.test | 5 + .../ELF/linkerscript/empty-relaplt-dyntags.test | 44 + lldb/include/lldb/Expression/IRExecutionUnit.h | 12 +- lldb/include/lldb/Symbol/Symbol.h | 7 +- lldb/include/lldb/lldb-enumerations.h | 2 + .../test/expression_command/weak_symbols/Makefile | 26 + .../weak_symbols/TestWeakSymbols.py | 83 + .../test/expression_command/weak_symbols/dylib.c | 14 + .../test/expression_command/weak_symbols/dylib.h | 8 + .../test/expression_command/weak_symbols/main.c | 23 + .../weak_symbols/module.modulemap | 3 + .../gdb_remote_client/TestRecognizeBreakpoint.py | 139 + .../gdb_remote_client/gdbclientutils.py | 5 + .../gdb_remote_client/operating_system_2.py | 62 + lldb/source/Expression/IRExecutionUnit.cpp | 91 +- lldb/source/Expression/IRInterpreter.cpp | 5 +- .../Plugins/ExpressionParser/Clang/IRForTarget.cpp | 18 +- .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 2 + .../gdb-remote/GDBRemoteCommunicationClient.cpp | 7 - .../Process/gdb-remote/ProcessGDBRemote.cpp | 17 +- .../SymbolFile/DWARF/DWARFDebugInfoEntry.cpp | 10 +- lldb/source/Symbol/Block.cpp | 4 +- lldb/source/Symbol/Symbol.cpp | 15 +- lldb/source/Target/Process.cpp | 10 +- llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h | 12 +- llvm/include/llvm/DebugInfo/GSYM/Range.h | 60 +- llvm/include/llvm/Demangle/ItaniumDemangle.h | 4 + llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp | 3 +- llvm/lib/DebugInfo/GSYM/InlineInfo.cpp | 2 +- llvm/lib/DebugInfo/GSYM/Range.cpp | 44 +- llvm/lib/MC/MCParser/WasmAsmParser.cpp | 97 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 93 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 262 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 +- llvm/lib/Target/AMDGPU/SIDefines.h | 13 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 108 + llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 42 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 91 +- llvm/lib/Target/ARM/ARMISelLowering.h | 5 + llvm/lib/Target/ARM/ARMInstrInfo.td | 11 + llvm/lib/Target/ARM/ARMInstrMVE.td | 86 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 3 +- .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 35 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 24 +- llvm/lib/Target/X86/X86ISelLowering.h | 3 +- .../Instrumentation/HWAddressSanitizer.cpp | 81 - llvm/lib/Transforms/Scalar/GVNSink.cpp | 1 + llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 88 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 1 + .../CodeGen/AArch64/urem-seteq-vec-nonsplat.ll | 649 ++++- llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll | 183 +- llvm/test/CodeGen/AArch64/urem-seteq.ll | 106 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 112 +- .../GlobalISel/regbankselect-amdgcn.atomic.dec.mir | 80 + .../GlobalISel/regbankselect-amdgcn.atomic.inc.mir | 80 + .../GlobalISel/regbankselect-amdgcn.div.fmas.mir | 106 + .../GlobalISel/regbankselect-amdgcn.ds.append.mir | 36 + .../regbankselect-amdgcn.ds.bpermute.mir | 24 + .../GlobalISel/regbankselect-amdgcn.ds.consume.mir | 36 + .../GlobalISel/regbankselect-amdgcn.ds.fmax.mir | 83 + .../GlobalISel/regbankselect-amdgcn.ds.fmin.mir | 83 + .../GlobalISel/regbankselect-amdgcn.ds.permute.mir | 24 + .../GlobalISel/regbankselect-amdgcn.fcmp.mir | 67 + .../regbankselect-amdgcn.groupstaticsize.mir | 14 + .../GlobalISel/regbankselect-amdgcn.icmp.mir | 67 + ...bankselect-amdgcn.s.get.waveid.in.workgroup.mir | 14 + .../GlobalISel/regbankselect-amdgcn.s.getpc.mir | 14 + .../GlobalISel/regbankselect-amdgcn.s.getreg.mir | 14 + .../regbankselect-amdgcn.s.memrealtime.mir | 14 + .../GlobalISel/regbankselect-amdgcn.s.memtime.mir | 14 + .../GlobalISel/regbankselect-amdgcn.update.dpp.mir | 82 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll | 2 +- llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll | 928 +++++++ llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll | 14 +- llvm/test/CodeGen/ARM/shift_parts.ll | 221 ++ llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll | 117 +- llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll | 2 + llvm/test/CodeGen/Thumb2/mve-fmath.ll | 2322 ++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll | 169 ++ llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll | 437 +-- llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll | 420 +-- llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll | 414 +-- llvm/test/CodeGen/Thumb2/mve-shuffle.ll | 25 +- llvm/test/CodeGen/Thumb2/mve-simple-arith.ll | 127 + llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll | 127 + .../test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll | 31 +- llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll | 31 +- llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll | 2854 ++++++++++++++++---- llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll | 496 ++-- llvm/test/CodeGen/X86/urem-seteq.ll | 127 +- llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll | 5 +- .../JITLink/X86/MachO_x86-64_relocations.s | 12 + .../Instrumentation/HWAddressSanitizer/basic.ll | 2 - .../HWAddressSanitizer/frame-descriptor.ll | 27 - .../HWAddressSanitizer/with-calls.ll | 1 - llvm/test/MC/AMDGPU/sopp-err.s | 103 +- llvm/test/MC/AMDGPU/sopp.s | 126 +- .../test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt | 4 +- llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt | 23 +- llvm/test/MC/WebAssembly/basic-assembly.s | 78 +- llvm/test/Transforms/Float2Int/basic.ll | 16 + llvm/test/Transforms/GVNSink/fpmath.ll | 3 +- .../IndVarSimplify/2011-11-01-lftrptr.ll | 7 +- .../test/Transforms/IndVarSimplify/lftr-pr41998.ll | 5 +- .../InstCombine/shift-amount-reassociation.ll | 83 +- llvm/test/Transforms/NewGVN/fpmath.ll | 19 +- llvm/test/tools/llvm-cov/multiple-files.test | 12 + llvm/tools/llvm-ar/llvm-ar.cpp | 1 + llvm/tools/llvm-cov/CoverageExporterLcov.cpp | 2 +- llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp | 47 +- llvm/unittests/Support/Path.cpp | 5 +- llvm/utils/UpdateTestChecks/asm.py | 9 + 168 files changed, 10922 insertions(+), 2930 deletions(-) create mode 100644 lld/test/COFF/Inputs/id.res.o create mode 100644 lld/test/COFF/resource-objs.test create mode 100644 lld/test/ELF/linkerscript/empty-relaplt-dyntags.test create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpe [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.con [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.per [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groups [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memr [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update [...] create mode 100644 llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll create mode 100644 llvm/test/CodeGen/ARM/shift_parts.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-fmath.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll delete mode 100644 llvm/test/Instrumentation/HWAddressSanitizer/frame-descriptor.ll