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from a2676383adf RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SU [...] new 04655110837 RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instru [...]
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Summary of changes: gcc/config/riscv/riscv-vsetvl.cc | 5 ++++ .../gcc.target/riscv/rvv/base/scalar_move-10.c | 31 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c