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from d506595 AMDGPU: Make AMDGPUMachineFunction fields private new 04defbc Re-committing r275284: add support to inline __builtin_mempcpy new d96170e GlobalISel: omit braces on MachineInstr types when there's only one. new b450d54 [Hexagon] Add support for proper handling of H and L constraints
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Summary of changes: include/llvm/Analysis/TargetLibraryInfo.def | 3 ++ include/llvm/Analysis/TargetLibraryInfo.h | 2 +- lib/Analysis/TargetLibraryInfo.cpp | 1 + lib/CodeGen/MIRParser/MIParser.cpp | 14 +++++-- lib/CodeGen/MIRPrinter.cpp | 9 +++-- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 47 ++++++++++++++++++++++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 1 + lib/Target/Hexagon/HexagonAsmPrinter.cpp | 24 +++++++---- lib/Transforms/Utils/BuildLibCalls.cpp | 1 + .../AArch64/GlobalISel/arm64-irtranslator.ll | 22 +++++----- .../AArch64/GlobalISel/arm64-regbankselect.mir | 42 +++++++++---------- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 18 ++++----- .../AMDGPU/GlobalISel/amdgpu-irtranslator.ll | 2 +- test/CodeGen/Hexagon/inline-asm-hexagon.ll | 16 ++++++++ test/CodeGen/MIR/X86/generic-virtual-registers.mir | 20 ++++----- test/Transforms/InferFunctionAttrs/annotate.ll | 3 ++ test/Transforms/InferFunctionAttrs/no-proto.ll | 3 ++ 17 files changed, 159 insertions(+), 69 deletions(-) create mode 100644 test/CodeGen/Hexagon/inline-asm-hexagon.ll