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from a520636d371 [AMDGPU] add LDS f32 intrinsics new 6d1111277e3 [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR new 0e62a1a1e76 [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.n [...]
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Summary of changes: lib/Target/ARM/ARMRegisterBankInfo.cpp | 18 +++++++++ lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 26 +++++++++---- test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 45 +++++++++++++++++++++++ test/MC/RISCV/cnop.s | 26 +++++++++++++ 4 files changed, 107 insertions(+), 8 deletions(-) create mode 100644 test/MC/RISCV/cnop.s