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from 10ad4e0 [llvm-cov] Strip redundant path components from filenames (fi [...] new b20570e Revert r282872 "CVP. Turn marking adds as no wrap on by default" new a328146 ARM: make sure FastISel bails on f64 operations for Cortex-M4. new 6bc216c [NVPTX] Added support for .f16x2 instructions.
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Summary of changes: lib/Target/ARM/ARMFastISel.cpp | 21 +- lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp | 3 + lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 + lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 346 ++++- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 + lib/Target/NVPTX/NVPTXISelLowering.cpp | 332 +++-- lib/Target/NVPTX/NVPTXISelLowering.h | 6 +- lib/Target/NVPTX/NVPTXInstrInfo.cpp | 2 + lib/Target/NVPTX/NVPTXInstrInfo.td | 124 +- lib/Target/NVPTX/NVPTXIntrinsics.td | 8 + lib/Target/NVPTX/NVPTXRegisterInfo.cpp | 4 + lib/Target/NVPTX/NVPTXRegisterInfo.td | 2 + .../Scalar/CorrelatedValuePropagation.cpp | 5 + test/CodeGen/ARM/fp-only-sp.ll | 62 + test/CodeGen/NVPTX/LoadStoreVectorizer.ll | 34 + test/CodeGen/NVPTX/f16-instructions.ll | 16 +- test/CodeGen/NVPTX/f16x2-instructions.ll | 1433 ++++++++++++++++++++ test/CodeGen/NVPTX/param-load-store.ll | 182 ++- test/Transforms/CorrelatedValuePropagation/add.ll | 2 +- 19 files changed, 2424 insertions(+), 162 deletions(-) create mode 100644 test/CodeGen/ARM/fp-only-sp.ll create mode 100644 test/CodeGen/NVPTX/f16x2-instructions.ll