[Tcwg-commits] [gcc] branch master updated (9cc2b97458b -> 5ee961b6f26)

31 Oct 2023


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unknown user pushed a change to branch master
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from  9cc2b97458b Fix incorrect option mask and avx512cd target push
       new  711d703d07c match.pd: Support combine cond_len_op + vec_cond similar to [...]
       new  5ee961b6f26 RISC-V: Add assert of the number of vmerge in autovec cond  [...]
The 2 revisions listed above as "new" are entirely new to this
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Summary of changes:
 gcc/gimple-match.h                                 | 72 ++++++++++++++++++++++
 gcc/match.pd                                       | 39 ++++++++++++
 .../riscv/rvv/autovec/cond/cond_arith-1.c          |  1 +
 .../cond/{cond_arith-1.c => cond_arith-10.c}       |  6 +-
 .../cond/{cond_arith-2.c => cond_arith-11.c}       |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-2.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-3.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-4.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-5.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-6.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-7.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_arith-8.c          |  1 +
 .../rvv/autovec/cond/cond_arith_run-10.c}          | 20 +++---
 .../{cond_arith_run-6.c => cond_arith_run-11.c}    |  2 +-
 .../autovec/cond/cond_convert_float2float-rv32-1.c |  1 +
 .../autovec/cond/cond_convert_float2float-rv32-2.c |  1 +
 .../autovec/cond/cond_convert_float2float-rv64-1.c |  1 +
 .../autovec/cond/cond_convert_float2float-rv64-2.c |  1 +
 .../autovec/cond/cond_convert_float2int-rv32-1.c   |  1 +
 .../autovec/cond/cond_convert_float2int-rv32-2.c   |  1 +
 .../autovec/cond/cond_convert_float2int-rv64-1.c   |  1 +
 .../autovec/cond/cond_convert_float2int-rv64-2.c   |  1 +
 .../autovec/cond/cond_convert_int2float-rv32-1.c   |  2 +
 .../autovec/cond/cond_convert_int2float-rv32-2.c   |  2 +
 .../autovec/cond/cond_convert_int2float-rv64-1.c   |  2 +
 .../autovec/cond/cond_convert_int2float-rv64-2.c   |  2 +
 .../rvv/autovec/cond/cond_convert_int2int-rv32-1.c |  2 +-
 .../rvv/autovec/cond/cond_convert_int2int-rv32-2.c |  1 +
 .../rvv/autovec/cond/cond_convert_int2int-rv64-1.c |  1 +
 .../rvv/autovec/cond/cond_convert_int2int-rv64-2.c |  1 +
 .../riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c |  1 +
 .../riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c |  1 +
 .../riscv/rvv/autovec/cond/cond_fadd-1.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fadd-2.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fadd-3.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fadd-4.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-2.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c       | 39 ++++++------
 .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c       |  2 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-7.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma-8.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c   | 38 ++++++------
 .../riscv/rvv/autovec/cond/cond_fmax-1.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmax-2.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmax-3.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmax-4.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmin-1.c           |  2 +-
 .../riscv/rvv/autovec/cond/cond_fmin-2.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmin-3.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmin-4.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c       |  1 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c       |  2 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c       |  2 +
 .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c       |  2 +
 .../riscv/rvv/autovec/cond/cond_fmul-1.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmul-2.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmul-3.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmul-4.c           |  1 +
 .../riscv/rvv/autovec/cond/cond_fmul-5.c           | 29 +++++++++
 .../rvv/autovec/cond/cond_fmul_run-5.c}            | 15 ++---
 .../rvv/autovec/cond/cond_logical_min_max-1.c      |  1 +
 .../rvv/autovec/cond/cond_logical_min_max-2.c      |  1 +
 .../rvv/autovec/cond/cond_logical_min_max-3.c      |  1 +
 .../rvv/autovec/cond/cond_logical_min_max-4.c      |  1 +
 .../rvv/autovec/cond/cond_logical_min_max-5.c      |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-1.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-2.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-3.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-4.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-5.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-6.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-7.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-8.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_shift-9.c          |  1 +
 .../riscv/rvv/autovec/cond/cond_sqrt-1.c           |  2 +
 .../riscv/rvv/autovec/cond/cond_sqrt-2.c           |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-1.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-2.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-3.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-4.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-5.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-6.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-7.c          |  2 +
 .../riscv/rvv/autovec/cond/cond_unary-8.c          |  2 +
 89 files changed, 301 insertions(+), 59 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_arith-1.c => cond_arith [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_arith-2.c => cond_arith [...]
 copy gcc/testsuite/gcc.target/{gcn/cond_fmaxnm_3_run.c => riscv/rvv/autovec/cond/c [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_arith_run-6.c => cond_a [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
 copy gcc/testsuite/gcc.target/{gcn/cond_fmaxnm_1_run.c => riscv/rvv/autovec/cond/c [...]
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[Tcwg-commits] [gcc] branch master updated (9cc2b97458b -> 5ee961b6f26)