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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/llvm-project.
from d890620fb27 [MC] Clean up MacroInstantiation. NFC adds 811a031c36f CodeGenRegBank - make functions const to fix cppcheck warnings. adds eb79d2da8a5 Path - fix uninitialized variable warnings. NFCI. adds b96ebc0a424 PODSmallVector - fix MSVC uninitialized variable warnings. NFCI. adds 616a7f6ca0a TableGen - fix uninitialized variable warnings. NFCI. adds a3c715e9788 Twine - fix uninitialized variable warnings. NFCI. adds 446581a3002 [NFC][Codegen] Add `x u% C1 == C2` with C1 u<= C2 tautologi [...] adds 6c94068da99 [Driver] Remove unused variable. NFC. adds 4ff246fef25 Remove unused variable (which allows us to remove vector in [...] adds ef02831f0a4 [InstCombine] avoid crash from deleting an instruction that [...] adds be0fead7bff [RISCV][NFC] Add CFI-related tests adds 1c737f54bee [RISCV] Fix CFA when doing split sp adjustment with fp adds b0ac26a6326 Revert "[InstCombine] avoid crash from deleting an instruct [...] adds bcca123bd0c Docs: Updates Sphinx Quickstart template for new contributors adds 7874db75ef4 [NFC][Codegen] Add `x u% C1 == C2` with C1 u> C2 non-tautol [...] adds 8e9e433a2af clang/Modules: Remove unused parameter from ModuleManager:: [...] adds c250ebf7bca getArgOperandNo helper function. adds 56b2aee1875 [InstCombine] avoid crash from deleting an instruction that [...] adds d115b9fd4a4 Revert "[InstCombine] avoid crash from deleting an instruct [...] adds d37db750c25 [InstCombine] Add a test case for suboptimal handling of (d [...] adds aafde063aaf [InstCombine] Turn (extractelement <1 x i64/double> (bitcas [...] adds 3d3445e3e69 Revert "Fixed a profdata file size detection on Windows system." adds 6ef63638cb8 [DirectedGraph]: Add setTargetNode member function Summary: [...] adds af5df83671b [NFC] Add one test to verify the dependency brings by Macro [...] adds 2f4fb200b6b libc++ status page: New papers and issues adopted in Belfast adds b4f46a9bb42 [clangd] Fixes colon escaping on Windows adds 06456daa9e5 [yaml2obj] - Add a way to describe the custom data that is [...] adds 84a0c8e3ae9 [AArch64][SVE] Spilling/filling of SVE callee-saves. adds a26d7b62982 [FixBB] - An attemp to fix clang-armv7-linux-build-cache builder. adds e6c9a9af398 Use MCRegister in copyPhysReg adds 6b15c5dface [FixBB] - Fix one more std::min -> std::min<uint64_t> to ma [...] adds e0012c5d6ac [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold [...] adds add7f2aba7b [NFC] Add one test to verify the sign_extend of vector type.
No new revisions were added by this update.
Summary of changes: .../clangd/clients/clangd-vscode/package-lock.json | 2 +- .../clangd/clients/clangd-vscode/package.json | 2 +- .../clangd-vscode/src/semantic-highlighting.ts | 42 +- clang/include/clang/Serialization/ModuleManager.h | 4 +- clang/lib/Driver/ToolChains/Darwin.cpp | 1 - clang/lib/Serialization/ASTReader.cpp | 6 +- clang/lib/Serialization/ModuleManager.cpp | 5 +- libcxx/www/cxx2a_status.html | 63 ++- llvm/docs/SphinxQuickstartTemplate.rst | 103 ++--- llvm/include/llvm/ADT/DirectedGraph.h | 3 + llvm/include/llvm/ADT/Twine.h | 4 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +- llvm/include/llvm/Demangle/ItaniumDemangle.h | 2 +- llvm/include/llvm/IR/InstrTypes.h | 13 + llvm/include/llvm/ObjectYAML/ELFYAML.h | 149 ++++--- llvm/include/llvm/ObjectYAML/YAML.h | 3 +- llvm/include/llvm/Support/Path.h | 16 +- llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 4 + llvm/lib/AsmParser/LLToken.h | 1 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 15 +- llvm/lib/IR/AsmWriter.cpp | 3 + llvm/lib/ObjectYAML/ELFEmitter.cpp | 168 +++++--- llvm/lib/ObjectYAML/ELFYAML.cpp | 62 ++- llvm/lib/ObjectYAML/YAML.cpp | 12 +- llvm/lib/TableGen/TGLexer.h | 10 +- llvm/lib/TableGen/TGParser.h | 2 +- .../lib/Target/AArch64/AArch64CallingConvention.td | 10 +- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 289 ++++++++++++-- llvm/lib/Target/AArch64/AArch64FrameLowering.h | 6 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 24 +- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 6 +- .../Target/AArch64/AArch64MachineFunctionInfo.h | 22 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 5 +- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/R600InstrInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +- llvm/lib/Target/ARC/ARCInstrInfo.cpp | 4 +- llvm/lib/Target/ARC/ARCInstrInfo.h | 2 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 2 +- llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 4 +- llvm/lib/Target/ARM/Thumb1InstrInfo.h | 2 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.h | 2 +- llvm/lib/Target/AVR/AVRInstrInfo.cpp | 4 +- llvm/lib/Target/AVR/AVRInstrInfo.h | 2 +- llvm/lib/Target/BPF/BPFInstrInfo.cpp | 4 +- llvm/lib/Target/BPF/BPFInstrInfo.h | 2 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 2 +- llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 4 +- llvm/lib/Target/Lanai/LanaiInstrInfo.h | 4 +- llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 4 +- llvm/lib/Target/MSP430/MSP430InstrInfo.h | 2 +- llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 4 +- llvm/lib/Target/Mips/Mips16InstrInfo.h | 2 +- llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 4 +- llvm/lib/Target/Mips/MipsSEInstrInfo.h | 2 +- llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 4 +- llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 2 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 14 +- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 42 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 4 +- llvm/lib/Target/Sparc/SparcInstrInfo.h | 2 +- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 28 +- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 2 +- .../Target/WebAssembly/WebAssemblyInstrInfo.cpp | 4 +- llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h | 2 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 4 +- llvm/lib/Target/X86/X86InstrInfo.h | 2 +- llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 4 +- llvm/lib/Target/XCore/XCoreInstrInfo.h | 2 +- llvm/lib/Transforms/IPO/Attributor.cpp | 4 +- .../InstCombine/InstCombineVectorOps.cpp | 7 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 3 - llvm/test/CodeGen/AArch64/framelayout-sve.mir | 184 +++++++++ llvm/test/CodeGen/AArch64/macro-fusion.ll | 23 ++ llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll | 247 ++++++++++++ .../test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll | 118 ++++++ .../CodeGen/AArch64/urem-seteq-vec-tautological.ll | 127 ++++++ llvm/test/CodeGen/ARM/signext-inreg.ll | 17 + .../CodeGen/MSP430/shift-amount-threshold-b.ll | 39 +- llvm/test/CodeGen/RISCV/frame-info.ll | 245 +++++++++++- llvm/test/CodeGen/RISCV/large-stack.ll | 8 +- llvm/test/CodeGen/RISCV/vararg.ll | 260 +++++++++++- llvm/test/CodeGen/X86/urem-seteq-nonzero.ll | 434 +++++++++++++++++++++ llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll | 434 +++++++++++++++++++++ .../CodeGen/X86/urem-seteq-vec-tautological.ll | 347 ++++++++++++++++ .../Transforms/InstCombine/bitcast-vec-canon.ll | 14 +- llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- llvm/test/tools/yaml2obj/custom-fill.yaml | 298 ++++++++++++++ .../tools/yaml2obj/duplicate-section-names.test | 6 +- llvm/test/tools/yaml2obj/program-header.yaml | 4 +- llvm/tools/obj2yaml/elf2yaml.cpp | 36 +- llvm/utils/TableGen/CodeGenRegisters.h | 8 +- 101 files changed, 3668 insertions(+), 468 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/macro-fusion.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll create mode 100644 llvm/test/CodeGen/ARM/signext-inreg.ll create mode 100644 llvm/test/CodeGen/X86/urem-seteq-nonzero.ll create mode 100644 llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll create mode 100644 llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll create mode 100644 llvm/test/tools/yaml2obj/custom-fill.yaml