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from 42e9b96ddfd Remove an unneeded (& mislayered) include from Target/Targe [...] new b22cddf04e5 [Pipeliner] Check for affine expression in isLoopCarriedOrder new 92d40b0a3d4 [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs new 476b2588b14 [AMDGPU] Improve disassembler error handling new e67cab7ed99 [Pipeliner] Several node-ordering fixes
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Summary of changes: lib/CodeGen/MachinePipeliner.cpp | 48 ++++++++++++--------- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 5 ++- lib/Target/X86/X86ScheduleBtVer2.td | 21 ++++++++-- test/CodeGen/X86/sse-schedule.ll | 16 +++---- test/CodeGen/X86/sse2-schedule.ll | 16 +++---- test/MC/AMDGPU/data.s | 27 ++++++++++++ test/tools/llvm-mca/X86/BtVer2/resources-sse1.s | 8 ++-- tools/llvm-objdump/llvm-objdump.cpp | 49 +++++++++++++++------- 8 files changed, 130 insertions(+), 60 deletions(-) create mode 100644 test/MC/AMDGPU/data.s