[Tcwg-commits] [gcc] branch master updated (a37a0cb303d -> 167b04b9b8a)

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unknown user pushed a change to branch master in repository gcc.

from a37a0cb303d Daily bump. new 61122017132 RISC-V: Add RVV shift.vx C/C++ API support new fae260ebfb1 RISC-V: Add vsrl.vx C API tests new f890b9e76f9 RISC-V: Add vsra.vx C API tests new 07fba8d6f2d RISC-V: Add vsll.vx C++ API tests new 6c93c1fb396 RISC-V: Add shift constraint tests new b0a2abcd79e RISC-V: Add vsrl.vx C++ API tests new f08acad732e RISC-V: Add vsra.vx C++ API tests new d8bd2c5f22e RISC-V: Add vsll.vx C++ API tests new f3a10f4fff3 RISC-V: Fix constraint bug for binary operation new 167b04b9b8a RISC-V: Remove unnecessary register class.

The 10 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/predicates.md | 8 + gcc/config/riscv/riscv-vector-builtins-bases.cc | 10 +- .../riscv/riscv-vector-builtins-functions.def | 3 + gcc/config/riscv/riscv-vector-builtins.cc | 13 + gcc/config/riscv/riscv.cc | 8 +- gcc/config/riscv/riscv.h | 8 +- gcc/config/riscv/vector-iterators.md | 86 +-- gcc/config/riscv/vector.md | 49 +- .../g++.target/riscv/rvv/base/vsll_vx-1.C | 578 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsll_vx-2.C | 578 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsll_vx-3.C | 578 +++++++++++++++++++++ .../rvv/base/{vsll_vv_mu-1.C => vsll_vx_mu-1.C} | 132 ++--- .../rvv/base/{vsll_vv_mu-2.C => vsll_vx_mu-2.C} | 132 ++--- .../rvv/base/{vsll_vv_mu-3.C => vsll_vx_mu-3.C} | 132 ++--- .../rvv/base/{vsll_vv_tu-1.C => vsll_vx_tu-1.C} | 132 ++--- .../rvv/base/{vsll_vv_tu-2.C => vsll_vx_tu-2.C} | 132 ++--- .../rvv/base/{vsll_vv_tu-3.C => vsll_vx_tu-3.C} | 132 ++--- .../rvv/base/{vsll_vv_tum-1.C => vsll_vx_tum-1.C} | 132 ++--- .../rvv/base/{vsll_vv_tum-2.C => vsll_vx_tum-2.C} | 132 ++--- .../rvv/base/{vsll_vv_tum-3.C => vsll_vx_tum-3.C} | 132 ++--- .../base/{vsll_vv_tumu-1.C => vsll_vx_tumu-1.C} | 132 ++--- .../base/{vsll_vv_tumu-2.C => vsll_vx_tumu-2.C} | 132 ++--- .../base/{vsll_vv_tumu-3.C => vsll_vx_tumu-3.C} | 132 ++--- .../g++.target/riscv/rvv/base/vsra_vx-1.C | 314 +++++++++++ .../g++.target/riscv/rvv/base/vsra_vx-2.C | 314 +++++++++++ .../g++.target/riscv/rvv/base/vsra_vx-3.C | 314 +++++++++++ .../rvv/base/{vsra_vv_mu-1.C => vsra_vx_mu-1.C} | 88 ++-- .../rvv/base/{vsra_vv_mu-2.C => vsra_vx_mu-2.C} | 88 ++-- .../rvv/base/{vsra_vv_mu-3.C => vsra_vx_mu-3.C} | 88 ++-- .../rvv/base/{vsra_vv_tu-1.C => vsra_vx_tu-1.C} | 88 ++-- .../rvv/base/{vsra_vv_tu-2.C => vsra_vx_tu-2.C} | 88 ++-- .../rvv/base/{vsra_vv_tu-3.C => vsra_vx_tu-3.C} | 88 ++-- .../rvv/base/{vsra_vv_tum-1.C => vsra_vx_tum-1.C} | 88 ++-- .../rvv/base/{vsra_vv_tum-2.C => vsra_vx_tum-2.C} | 88 ++-- .../rvv/base/{vsra_vv_tum-3.C => vsra_vx_tum-3.C} | 88 ++-- .../base/{vsra_vv_tumu-1.C => vsra_vx_tumu-1.C} | 88 ++-- .../base/{vsra_vv_tumu-2.C => vsra_vx_tumu-2.C} | 88 ++-- .../base/{vsra_vv_tumu-3.C => vsra_vx_tumu-3.C} | 88 ++-- .../g++.target/riscv/rvv/base/vsrl_vx-1.C | 314 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vx-2.C | 314 +++++++++++ .../g++.target/riscv/rvv/base/vsrl_vx-3.C | 314 +++++++++++ .../rvv/base/{vsrl_vv_mu-1.C => vsrl_vx_mu-1.C} | 88 ++-- .../rvv/base/{vsrl_vv_mu-2.C => vsrl_vx_mu-2.C} | 88 ++-- .../rvv/base/{vsrl_vv_mu-3.C => vsrl_vx_mu-3.C} | 88 ++-- .../rvv/base/{vsrl_vv_tu-1.C => vsrl_vx_tu-1.C} | 88 ++-- .../rvv/base/{vsrl_vv_tu-2.C => vsrl_vx_tu-2.C} | 88 ++-- .../rvv/base/{vsrl_vv_tu-3.C => vsrl_vx_tu-3.C} | 88 ++-- .../rvv/base/{vsrl_vv_tum-1.C => vsrl_vx_tum-1.C} | 88 ++-- .../rvv/base/{vsrl_vv_tum-2.C => vsrl_vx_tum-2.C} | 88 ++-- .../rvv/base/{vsrl_vv_tum-3.C => vsrl_vx_tum-3.C} | 88 ++-- .../base/{vsrl_vv_tumu-1.C => vsrl_vx_tumu-1.C} | 88 ++-- .../base/{vsrl_vv_tumu-2.C => vsrl_vx_tumu-2.C} | 88 ++-- .../base/{vsrl_vv_tumu-3.C => vsrl_vx_tumu-3.C} | 88 ++-- .../riscv/rvv/base/binop_vv_constraint-1.c | 8 +- ...p_vv_constraint-1.c => shift_vx_constraint-1.c} | 54 +- .../gcc.target/riscv/rvv/base/vsll_vx-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_m-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_m-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_m-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_mu-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_mu-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_mu-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tu-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tu-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tu-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tum-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tum-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tum-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tumu-1.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tumu-2.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsll_vx_tumu-3.c | 292 +++++++++++ .../gcc.target/riscv/rvv/base/vsra_vx-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_m-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_m-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_m-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_mu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_mu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_mu-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tu-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tum-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tum-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tum-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c | 160 ++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c | 160 ++++++ 109 files changed, 16632 insertions(+), 1945 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_mu-1.C => vsll_vx_mu-1.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_mu-2.C => vsll_vx_mu-2.C} (64%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_mu-3.C => vsll_vx_mu-3.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tu-1.C => vsll_vx_tu-1.C} (65%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tu-2.C => vsll_vx_tu-2.C} (66%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tu-3.C => vsll_vx_tu-3.C} (65%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tum-1.C => vsll_vx_tum-1.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tum-2.C => vsll_vx_tum-2.C} (64%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tum-3.C => vsll_vx_tum-3.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tumu-1.C => vsll_vx_tumu-1.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tumu-2.C => vsll_vx_tumu-2.C} (64%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsll_vv_tumu-3.C => vsll_vx_tumu-3.C} (63%) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-3.C copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_mu-1.C => vsra_vx_mu-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_mu-2.C => vsra_vx_mu-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_mu-3.C => vsra_vx_mu-3.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tu-1.C => vsra_vx_tu-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tu-2.C => vsra_vx_tu-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tu-3.C => vsra_vx_tu-3.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tum-1.C => vsra_vx_tum-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tum-2.C => vsra_vx_tum-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tum-3.C => vsra_vx_tum-3.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tumu-1.C => vsra_vx_tumu-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tumu-2.C => vsra_vx_tumu-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsra_vv_tumu-3.C => vsra_vx_tumu-3.C} (58%) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-3.C copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_mu-1.C => vsrl_vx_mu-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_mu-2.C => vsrl_vx_mu-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_mu-3.C => vsrl_vx_mu-3.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tu-1.C => vsrl_vx_tu-1.C} (61%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tu-2.C => vsrl_vx_tu-2.C} (63%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tu-3.C => vsrl_vx_tu-3.C} (61%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tum-1.C => vsrl_vx_tum-1.C} (57%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tum-2.C => vsrl_vx_tum-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tum-3.C => vsrl_vx_tum-3.C} (57%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tumu-1.C => vsrl_vx_tumu-1.C} (58%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tumu-2.C => vsrl_vx_tumu-2.C} (60%) copy gcc/testsuite/g++.target/riscv/rvv/base/{vsrl_vv_tumu-3.C => vsrl_vx_tumu-3.C} (58%) copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => shift_vx_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c