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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/llvm-project.
from 5cf616530a1 Fix check-prefixes typo adds 763a2e1f360 [llvm-nm][llvm-readelf] Avoid single-dash -long-option in tests adds 15c072a1619 [lli] Fix a typo in a cl::opt description. adds 913bfd3363f [X86] Add vector boolean reduction tests (PR38840) adds 2a2d4224002 [X86][AVX512] Improve vector bool reductions adds e2849a031c0 Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateAD [...] adds 399746eaf6f [X86][AVX] Cleanup and add additional expandload and compre [...] adds 4118be3af60 [X86][SSE] Add support for <64 x i1> bool reduction adds 1a4a43250ed [X86][AVX] Add additional SSE/AVX expandload and compressst [...] adds 03c4e2663ce Revert rL359389: [X86][SSE] Add support for <64 x i1> bool [...] adds bd35a309403 [X86] Remove (V)MOV64toSDrr/m and (V)MOVDI2SSrr/m. Use 128- [...] adds 8eeb33497cd [PowerPC][Clang] Add tests for PowerPC MMX intrinsics adds 8651edf8985 [CMake] Don't modify `FUZZER_SUPPORTED_ARCH` is place. adds fed302ae37e [X86][AVX] Add AVX512DQ coverage for masked memory ops test [...] adds 93ad48210cb [X86][SSE] Optimize llvm.experimental.vector.reduce.xor.vXi [...] adds 43003f0fec7 [MCA] Fix typo in AVX2 gather tests. NFC adds fb9a5307a94 [DAGCombiner] try repeated fdiv divisor transform before bu [...] adds ce8cfe96f76 [SelectionDAG] include FP min/max variants as binary operators adds 22d1476bfa8 [X86][AVX] Combine non-lane crossing binary shuffles using [...] adds d394195221a [X86][AVX] Enabled AVX512F tests and add PR40815 test case adds 7a94795b2b7 [ConstantRange] Add makeExactNoWrapRegion() adds 2f5f9a159bc Attempt to switch to auto-scaling bots
No new revisions were added by this update.
Summary of changes: clang/test/CodeGen/ppc-mmintrin.c | 1284 ++++- compiler-rt/test/fuzzer/CMakeLists.txt | 5 +- libcxx/utils/docker/debian9/Dockerfile | 2 + libcxx/utils/docker/scripts/run_buildbot.sh | 10 + libcxx/utils/docker/scripts/run_buildbot_new.sh | 105 + .../Instruction/ARM/EmulateInstructionARM.cpp | 2 +- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 8 +- llvm/include/llvm/IR/ConstantRange.h | 12 +- llvm/lib/Analysis/LazyValueInfo.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +- llvm/lib/IR/ConstantRange.cpp | 14 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 69 +- llvm/lib/Target/X86/X86InstrAVX512.td | 29 +- llvm/lib/Target/X86/X86InstrFoldTables.cpp | 6 - llvm/lib/Target/X86/X86InstrSSE.td | 57 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 296 +- llvm/test/CodeGen/X86/evex-to-vex-compress.mir | 16 - llvm/test/CodeGen/X86/extract-fp.ll | 37 +- llvm/test/CodeGen/X86/fast-isel-fneg.ll | 13 +- llvm/test/CodeGen/X86/fdiv-combine-vec.ll | 66 +- llvm/test/CodeGen/X86/insertelement-ones.ll | 21 +- llvm/test/CodeGen/X86/masked_compressstore.ll | 5656 ++++++++++++++++---- llvm/test/CodeGen/X86/masked_expandload.ll | 5399 ++++++++++++++++--- llvm/test/CodeGen/X86/masked_load.ll | 1015 +++- llvm/test/CodeGen/X86/masked_store.ll | 874 ++- llvm/test/CodeGen/X86/oddsubvector.ll | 75 + llvm/test/CodeGen/X86/peephole.mir | 40 - llvm/test/CodeGen/X86/pr41619.ll | 27 + .../CodeGen/X86/shuffle-strided-with-offset-256.ll | 95 +- .../test/CodeGen/X86/shuffle-vs-trunc-256-widen.ll | 259 +- llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll | 137 +- .../test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll | 8 +- llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll | 8 +- llvm/test/CodeGen/X86/vec_smulo.ll | 74 +- llvm/test/CodeGen/X86/vec_umulo.ll | 72 +- llvm/test/CodeGen/X86/vector-compare-all_of.ll | 175 +- llvm/test/CodeGen/X86/vector-compare-any_of.ll | 188 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 7 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 6 +- llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 1461 +++++ llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 1455 +++++ llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 1647 ++++++ llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll | 145 +- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 118 +- llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll | 288 +- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 32 +- llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll | 25 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 97 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 191 +- llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll | 5 +- .../X86/vector-shuffle-combining-avx512vbmi.ll | 6 +- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 14 +- llvm/test/CodeGen/X86/vector-trunc-widen.ll | 36 +- llvm/test/CodeGen/X86/vector-trunc.ll | 44 +- .../DebugInfo/X86/xray-split-dwarf-interaction.ll | 2 +- llvm/test/DebugInfo/debuglineinfo-path.ll | 6 +- llvm/test/LTO/X86/runtime-library.ll | 2 +- llvm/test/MC/Mips/tls-symbols.s | 5 +- llvm/test/Other/llvm-nm-without-aliases.ll | 6 +- llvm/test/ThinLTO/X86/cache-icall.ll | 4 +- llvm/test/tools/gold/X86/bcsection.ll | 4 +- llvm/test/tools/llvm-ar/coff-weak.yaml | 2 +- .../tools/llvm-mca/X86/Broadwell/resources-avx2.s | 6 +- .../tools/llvm-mca/X86/Generic/resources-avx2.s | 6 +- .../tools/llvm-mca/X86/Haswell/resources-avx2.s | 6 +- .../llvm-mca/X86/SkylakeClient/resources-avx2.s | 6 +- .../llvm-mca/X86/SkylakeServer/resources-avx2.s | 6 +- .../tools/llvm-mca/X86/Znver1/resources-avx2.s | 6 +- llvm/test/tools/llvm-nm/X86/IRobj.test | 2 +- llvm/test/tools/llvm-nm/X86/dyldinfo.test | 4 +- llvm/test/tools/llvm-nm/X86/radix.s | 10 +- .../elf-reloc-symbol-with-versioning.test | 4 +- llvm/test/tools/llvm-readobj/elf-versioninfo.test | 4 +- llvm/test/tools/lto/opt-level.ll | 4 +- llvm/test/tools/yaml2obj/dynamic-symbols.yaml | 2 +- llvm/test/tools/yaml2obj/symbol-index.yaml | 2 +- llvm/tools/lli/lli.cpp | 2 +- llvm/tools/llvm-nm/llvm-nm.cpp | 4 - llvm/unittests/IR/ConstantRangeTest.cpp | 12 +- 79 files changed, 18618 insertions(+), 3240 deletions(-) create mode 100755 libcxx/utils/docker/scripts/run_buildbot_new.sh delete mode 100644 llvm/test/CodeGen/X86/peephole.mir create mode 100644 llvm/test/CodeGen/X86/pr41619.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-and-bool.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-or-bool.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll