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from bb043cd3da5 arm: [MVE intrinsics] rework vshrq vrshrq new 3365956d55a RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET new 0c1eaac3fd3 RISC-V: Legitimise the const0_rtx for RVV indexed load/store
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Summary of changes: gcc/config/riscv/riscv.h | 5 ++ gcc/config/riscv/vector.md | 62 +++++++++++----------- .../riscv/rvv/base/integer_compare_insn_shortcut.c | 6 +-- .../rvv/base/zero_base_load_store_optimization.c | 3 +- 4 files changed, 39 insertions(+), 37 deletions(-)