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from dd3dfa3790f testsuite: Add support for GCOV_UNDER_TEST new 1b1b3896a2a libstdc++: Update baseline symbols for riscv64-linux new bd8a48500c1 [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
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Summary of changes: gcc/config/riscv/riscv-cores.def | 48 +++++++++++++++++++ gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c | 48 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c | 50 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c | 35 ++++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c | 51 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c | 34 +++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c | 56 ++++++++++++++++++++++ .../post/riscv64-linux-gnu/baseline_symbols.txt | 15 ++++++ 9 files changed, 340 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c