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from d65619850cf [X86] Add support for avx512bf16 for __builtin_cpu_supports [...] new 91ae0b70af9 [Attributor] Deal more explicit with non-exact definitions new 4610ea6eb2f GlobalISel: Define GINodeEquiv for undef new e2d7eae2972 GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns new d6d1c465084 AMDGPU/GlobalISel: Make 16-bit constants legal
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Summary of changes: .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 + include/llvm/Transforms/IPO/Attributor.h | 34 ++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 16 +- lib/Transforms/IPO/Attributor.cpp | 105 ++-- .../AMDGPU/GlobalISel/artifact-combiner-sext.mir | 25 +- .../AMDGPU/GlobalISel/artifact-combiner-zext.mir | 9 +- test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 46 +- .../AMDGPU/GlobalISel/legalize-constant.mir | 3 +- .../GlobalISel/legalize-extract-vector-elt.mir | 3 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 15 +- test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 29 +- .../AMDGPU/GlobalISel/legalize-fconstant.mir | 35 +- .../AMDGPU/GlobalISel/legalize-fcopysign.mir | 180 +++---- test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 36 +- .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 3 +- test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 36 +- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 552 +++++++++------------ test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir | 7 +- test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 8 +- test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 58 +-- test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir | 30 +- test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir | 30 +- test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir | 22 +- test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir | 22 +- test/Transforms/FunctionAttrs/arg_returned.ll | 30 ++ test/Transforms/FunctionAttrs/nonnull.ll | 12 + test/Transforms/FunctionAttrs/noreturn_async.ll | 2 +- test/Transforms/FunctionAttrs/nounwind.ll | 2 +- utils/TableGen/GlobalISelEmitter.cpp | 56 ++- 29 files changed, 632 insertions(+), 775 deletions(-)