This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-defconfig in repository toolchain/ci/gcc.
from 50a42922d35 Daily bump. adds a1f8dca201e [AArch64] PR92424: Fix -fpatchable-function-entry=N,M with BTI adds c6613dd33ce Daily bump. adds 9d9679132e0 c++: Drop alignas restriction for stack variables. adds afb84a42ad8 RISC-V: Disallow regrenme if the TO register never used bef [...]
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 23 +++++++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 5 +++ gcc/c-family/c-attribs.c | 62 +--------------------------- gcc/config/aarch64/aarch64.c | 31 ++++++++++++++ gcc/config/aarch64/aarch64.h | 1 + gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.c | 13 ++++++ gcc/config/riscv/riscv.h | 2 + gcc/testsuite/ChangeLog | 17 ++++++++ gcc/testsuite/g++.dg/cpp0x/alignas17.C | 14 +++++++ gcc/testsuite/gcc.target/aarch64/pr92424-2.c | 12 ++++++ gcc/testsuite/gcc.target/aarch64/pr92424-3.c | 12 ++++++ gcc/testsuite/gcc.target/riscv/pr93304.c | 19 +++++++++ 14 files changed, 153 insertions(+), 62 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/alignas17.C create mode 100644 gcc/testsuite/gcc.target/aarch64/pr92424-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr92424-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr93304.c