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from 2e48b5a57e9 [X86][SSE] Ensure vector partial load/stores use the WriteV [...] new 96a67f12563 [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency
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Summary of changes: lib/Target/X86/X86ScheduleBtVer2.td | 4 ++-- test/CodeGen/X86/mmx-schedule.ll | 2 +- test/CodeGen/X86/sse-schedule.ll | 10 +++++----- test/CodeGen/X86/sse2-schedule.ll | 24 ++++++++++++------------ test/tools/llvm-mca/X86/BtVer2/resources-avx1.s | 16 ++++++++-------- test/tools/llvm-mca/X86/BtVer2/resources-mmx.s | 4 ++-- test/tools/llvm-mca/X86/BtVer2/resources-sse1.s | 6 +++--- test/tools/llvm-mca/X86/BtVer2/resources-sse2.s | 10 +++++----- 8 files changed, 38 insertions(+), 38 deletions(-)