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from 4768f3d [mips] Fix typos in spelling of lowerRETURNADDR. new 1123323 GlobalISel: give MachineInstrBuilder a uniform interface. NFC. new 27d9a7f GlobalISel: add specialized buildCopy function to MachineInst [...] new ee4cdb7 AMDGPU: Add fp legacy instruction intrinsics new cc67a0a AMDGPU: Add missing tests for xnack option for HSA new d506595 AMDGPU: Make AMDGPUMachineFunction fields private
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Summary of changes: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 97 +++++++++++++--------- include/llvm/IR/IntrinsicsAMDGPU.td | 8 ++ lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 64 ++++---------- lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 11 +-- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 ++---- lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 + lib/Target/AMDGPU/AMDGPUInstrInfo.td | 5 ++ lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | 44 +++++++--- lib/Target/AMDGPU/AMDGPUMachineFunction.h | 43 +++++++--- lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- lib/Target/AMDGPU/SIISelLowering.cpp | 13 ++- lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- lib/Target/AMDGPU/SIInstructions.td | 5 +- lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 3 - lib/Target/AMDGPU/SIMachineFunctionInfo.h | 1 - test/CodeGen/AMDGPU/flat-scratch-reg.ll | 26 ++++-- test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll | 54 ++++++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll | 42 ++++++++++ 21 files changed, 304 insertions(+), 154 deletions(-) create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll