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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/qemu.
from 75ee62ac60 Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-n [...] adds 10b43754cf hw/riscv: sifive_u: Add UART1 DT node in the generated DTB adds dfc973ecc1 hw/riscv: microchip_pfsoc: add QSPI NOR flash adds b3d2a4296f hw/core/register.c: Don't use '#' flag of printf format adds c63ca4ff7f target/riscv: Fix the bug of HLVX/HLV/HSV adds 529577457c target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR adds 54a581c228 intc/ibex_plic: Clear interrupts that occur during claim process adds 617448a46b hw/riscv: Expand the is 32-bit check to support more CPUs adds c0a635f397 target/riscv: Add a TYPE_RISCV_CPU_BASE CPU adds dc4d4aaee3 riscv: spike: Remove target macro conditionals adds 09fe17125e riscv: virt: Remove target macro conditionals adds 7893677184 hw/riscv: boot: Remove compile time XLEN checks adds 9d01143063 hw/riscv: virt: Remove compile time XLEN checks adds bd62c13ea8 hw/riscv: spike: Remove compile time XLEN checks adds 2206ffa68f hw/riscv: sifive_u: Remove compile time XLEN checks adds 5b6c291b8d target/riscv: fpu_helper: Match function defs in HELPER macros adds 51ae0cabc6 target/riscv: Add a riscv_cpu_is_32bit() helper function adds 114baaca51 target/riscv: Specify the XLEN for CPUs adds 5c5a47f10c target/riscv: cpu: Remove compile time XLEN checks adds f08c7ff3dc target/riscv: cpu_helper: Remove compile time XLEN checks adds 8987cdc481 target/riscv: csr: Remove compile time XLEN checks adds 094b072c68 target/riscv: cpu: Set XLEN independently from target adds 3ed2b8ac2d hw/riscv: Use the CPU to determine if 32-bit adds d31e970a01 riscv/opentitan: Update the OpenTitan memory layout adds a05f8ecd88 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...]
No new revisions were added by this update.
Summary of changes: hw/core/register.c | 16 ++-- hw/intc/ibex_plic.c | 13 ++- hw/riscv/boot.c | 70 ++++++++------- hw/riscv/microchip_pfsoc.c | 21 +++++ hw/riscv/opentitan.c | 81 ++++++++++++----- hw/riscv/sifive_u.c | 74 ++++++++++------ hw/riscv/spike.c | 52 ++++++----- hw/riscv/virt.c | 39 ++++---- include/hw/riscv/boot.h | 14 +-- include/hw/riscv/microchip_pfsoc.h | 3 + include/hw/riscv/opentitan.h | 23 +++-- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_helper.c | 15 ++-- target/riscv/csr.c | 176 +++++++++++++++++++------------------ target/riscv/fpu_helper.c | 8 -- target/riscv/helper.h | 24 ++--- 20 files changed, 434 insertions(+), 307 deletions(-)