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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/qemu.
from 57c9363c45 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 64baad62cd target/loongarch: Add README adds 228021f05e target/loongarch: Add core definition adds f8da88d78f target/loongarch: Add main translation routines adds 143d6785ef target/loongarch: Add fixed point arithmetic instruction tra [...] adds 63cfcd47d7 target/loongarch: Add fixed point shift instruction translation adds ad08cb3f97 target/loongarch: Add fixed point bit instruction translation adds bb79174d4e target/loongarch: Add fixed point load/store instruction tra [...] adds 94b02d57b0 target/loongarch: Add fixed point atomic instruction translation adds 8708a04a61 target/loongarch: Add fixed point extra instruction translation adds d578ca6cbb target/loongarch: Add floating point arithmetic instruction [...] adds 9b7410763a target/loongarch: Add floating point comparison instruction [...] adds 7c1f88703d target/loongarch: Add floating point conversion instruction [...] adds b7dabd5624 target/loongarch: Add floating point move instruction translation adds e616bdfd01 target/loongarch: Add floating point load/store instruction [...] adds ee86bd58b8 target/loongarch: Add branch instruction translation adds aae1746c72 target/loongarch: Add disassembler adds 14f2b0b741 target/loongarch: Add target build suport adds d88b51dc26 target/loongarch: Add system emulation introduction adds 398cecb9c3 target/loongarch: Add CSRs definition adds 67ebd42a48 target/loongarch: Add basic vmstate description of CPU. adds 425876f5d8 target/loongarch: Implement qmp_query_cpu_definitions() adds 7e1c521e2a target/loongarch: Add MMU support for LoongArch CPU. adds f757a2cd69 target/loongarch: Add LoongArch interrupt and exception handle adds dd615fa48d target/loongarch: Add constant timer support adds 5b1dedfe84 target/loongarch: Add LoongArch CSR instruction adds f84a2aacf5 target/loongarch: Add LoongArch IOCSR instruction adds fcbbeb8ecd target/loongarch: Add TLB instruction support adds d2cba6f7ce target/loongarch: Add other core instructions support adds f9bf50745f target/loongarch: Add timer related instructions support. adds a8a506c390 hw/loongarch: Add support loongson3 virt machine type. adds f6783e3438 hw/loongarch: Add LoongArch ipi interrupt support(IPI) adds 0f4fcf1845 hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) adds 249ad85a4b hw/intc: Add LoongArch ls7a msi interrupt controller support [...] adds cbff2db1e9 hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) adds 69d9c74fa9 hw/loongarch: Add irq hierarchy for the system adds 256309e188 Enable common virtio pci support for LoongArch adds dc93b8df8a hw/loongarch: Add some devices support for 3A5000. adds c117f68a46 hw/loongarch: Add LoongArch ls7a rtc device support adds 6a6f26f481 hw/loongarch: Add LoongArch load elf function. adds 9e6602d657 hw/loongarch: Add LoongArch virt power manager support. adds ca61e75071 target/loongarch: Add gdb support. adds c429333398 tests/tcg/loongarch64: Add hello/memory test in loongarch64 system adds 34bb43b074 target/loongarch: 'make check-tcg' support adds 9b1f588549 Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/q [...] adds 4d84bb6c8b hw/tpm/tpm_tis_common.c: Assert that locty is in range adds e37a0ef460 tpm_crb: mark command buffer as dirty on request completion adds 6d940eff47 Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stef [...] adds ec6600be0d vfio/common: remove spurious warning on vfio_listener_region_del adds 05911658cb Merge tag 'vfio-updates-20220608.0' of https://gitlab.com/al [...] adds d507bc3b05 target/arm: Declare support for FEAT_RASv1p1 adds 7ac610206a target/arm: Implement FEAT_DoubleFault adds 9323e79f10 Fix 'writeable' typos adds d2008b3355 xlnx_dp: fix the wrong register size adds 759ae1b47e xlnx_dp: Introduce a vblank signal adds 39f40d02f6 xlnx_dp: Fix the interrupt disable logic adds b3f5cc3fda xlnx-zynqmp: fix the irq mapping for the display port and its dma adds d8cca960a9 target/arm: Move stage_1_mmu_idx decl to internals.h adds 8ae0886002 target/arm: Move get_phys_addr to ptw.c adds f2d2f5ceb8 target/arm: Move get_phys_addr_v5 to ptw.c adds 53c038efb7 target/arm: Move get_phys_addr_v6 to ptw.c adds 9a12fb366d target/arm: Move get_phys_addr_pmsav5 to ptw.c adds 7d2e08c960 target/arm: Move get_phys_addr_pmsav7_default to ptw.c adds 1f2e87e5ab target/arm: Move get_phys_addr_pmsav7 to ptw.c adds 730d5c31d8 target/arm: Move get_phys_addr_pmsav8 to ptw.c adds fedbaa0503 target/arm: Move pmsav8_mpu_lookup to ptw.c adds c8e436c9f7 target/arm: Move pmsav7_use_background_region to ptw.c adds 2c1f429df3 target/arm: Move v8m_security_lookup to ptw.c adds 47ff5ba9d0 target/arm: Move m_is_{ppb,system}_region to ptw.c adds 4c74ab157b target/arm: Move get_level1_table_address to ptw.c adds 966f4bb7d8 target/arm: Move combine_cacheattrs and subroutines to ptw.c adds 3283222acd target/arm: Move get_phys_addr_lpae to ptw.c adds 11552bb0d9 target/arm: Move arm_{ldl,ldq}_ptw to ptw.c adds cd6bc4d517 target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_ [...] adds 1c73d84807 target/arm: Move arm_pamax, pamax_map into ptw.c adds f8526edc2f target/arm: Move get_S1prot, get_S2prot to ptw.c adds c5168785d2 target/arm: Move check_s2_mmu_setup to ptw.c adds 2f0ec92e94 target/arm: Move aa32_va_parameters to ptw.c adds 4845d3be12 target/arm: Move ap_to_tw_prot etc to ptw.c adds 0c23d56fc1 target/arm: Move regime_is_user to ptw.c adds 3b318aaeef target/arm: Move regime_ttbr to ptw.c adds 8db1a3a0bb target/arm: Move regime_translation_disabled to ptw.c adds 23971205cf target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c adds 1d26125536 target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c adds 5e79887ba6 target/arm: Pass CPUARMState to arm_ld[lq]_ptw adds f45ce4c35f target/arm: Rename TBFLAG_A64 ZCR_LEN to VL adds 8b599e5c02 linux-user/aarch64: Introduce sve_vq adds 61a8c23a3b target/arm: Remove route_to_el2 check from sve_exception_el adds 397d922c62 target/arm: Remove fp checks from sve_exception_el adds 19668718ad target/arm: Add el_is_in_host adds c6225bebc2 target/arm: Use el_is_in_host for sve_zcr_len_for_el adds aa4451b60e target/arm: Use el_is_in_host for sve_exception_el adds 7d38cb92aa target/arm: Hoist arm_is_el2_enabled check in sve_exception_el adds 87252bdecd target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset adds 9b5f422559 target/arm: Merge aarch64_sve_zcr_get_valid_len into caller adds 886902ece7 target/arm: Use uint32_t instead of bitmap for sve vq's adds 5ef3cc5636 target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el adds d1ce862602 target/arm: Split out load/store primitives to sve_ldst_internal.h adds 0b68112b39 target/arm: Export sve contiguous ldst support functions adds 820e0bb9ce target/arm: Move expand_pred_b to vec_internal.h adds 05dd14bdfa target/arm: Use expand_pred_b in mve_helper.c adds a613cf2d4a target/arm: Move expand_pred_h to vec_internal.h adds 72db2aa353 target/arm: Export bfdotadd from vec_helper.c adds f305bf9436 target/arm: Add isar_feature_aa64_sme adds 414c54d515 target/arm: Add ID_AA64SMFR0_EL1 adds 028f2361d0 Merge tag 'pull-target-arm-20220609' of https://git.linaro.o [...] adds 7851b21a81 hw/ide/piix: Remove redundant "piix3-ide-xen" device class adds 3690241746 hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug() adds 6a8a8b62bd include/hw/ide: Unexport pci_piix3_xen_ide_unplug() adds 9cc1bf1ebc Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git [...] adds efe1592c43 MAINTAINERS: Cover hw/core/uboot_image.h within Generic Load [...] adds de799beba7 target/riscv: add support for zmmul extension v0.1 adds f9a461b2d3 hw/riscv: virt: Generate fw_cfg DT node correctly adds 40244040a7 hw/intc: sifive_plic: Avoid overflowing the addr_config buffer adds af9751316e hw/core/loader: return image sizes as ssize_t adds 8f42415fc1 target/riscv: Wake on VS-level external interrupts adds d1d8541217 target/riscv/debug.c: keep experimental rv128 support working adds 8a085fb2ad target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed adds 25eae0486d target/riscv: rvv: Prune redundant access_type parameter passed adds c7b8a4213b target/riscv: rvv: Rename ambiguous esz adds 41d3d7f76a target/riscv: rvv: Early exit when vstart >= vl adds f1eed927fb target/riscv: rvv: Add tail agnostic for vv instructions adds 752614cab8 target/riscv: rvv: Add tail agnostic for vector load / store [...] adds 5c19fc156e target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions adds 7b1bff41c1 target/riscv: rvv: Add tail agnostic for vector integer shif [...] adds 38581e5c9a target/riscv: rvv: Add tail agnostic for vector integer comp [...] adds 89a32de2d5 target/riscv: rvv: Add tail agnostic for vector integer merg [...] adds 09106eed30 target/riscv: rvv: Add tail agnostic for vector fix-point ar [...] adds 5eacf7d8a0 target/riscv: rvv: Add tail agnostic for vector floating-poi [...] adds df4f52a758 target/riscv: rvv: Add tail agnostic for vector reduction in [...] adds acc6ffd482 target/riscv: rvv: Add tail agnostic for vector mask instructions adds 803963f7cb target/riscv: rvv: Add tail agnostic for vector permutation [...] adds b8312675d6 target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable opti [...] adds 26b2bc5859 target/riscv: Don't expose the CPU properties on names CPUs adds 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 adds b3cd3b5a66 Merge tag 'pull-riscv-to-apply-20220610' of github.com:alist [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 25 + accel/hvf/hvf-accel-ops.c | 4 +- accel/kvm/kvm-all.c | 4 +- accel/tcg/user-exec.c | 6 +- configs/devices/loongarch64-softmmu/default.mak | 3 + configs/targets/loongarch64-softmmu.mak | 4 + configure | 1 + docs/interop/vhost-user.rst | 2 +- docs/specs/vmgenid.txt | 4 +- docs/system/arm/emulation.rst | 2 + docs/system/loongarch/loongson3.rst | 41 + gdb-xml/loongarch-base64.xml | 44 + gdb-xml/loongarch-fpu64.xml | 57 + hw/Kconfig | 1 + hw/acpi/ghes.c | 2 +- hw/arm/armv7m.c | 2 +- hw/arm/boot.c | 8 +- hw/arm/xlnx-zynqmp.c | 4 +- hw/core/generic-loader.c | 2 +- hw/core/loader.c | 81 +- hw/display/xlnx_dp.c | 49 +- hw/i386/pc_piix.c | 3 +- hw/i386/x86.c | 2 +- hw/i386/xen/xen_platform.c | 48 +- hw/ide/piix.c | 42 - hw/intc/Kconfig | 15 + hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/loongarch_extioi.c | 312 ++ hw/intc/loongarch_ipi.c | 242 ++ hw/intc/loongarch_pch_msi.c | 73 + hw/intc/loongarch_pch_pic.c | 431 +++ hw/intc/meson.build | 4 + hw/intc/riscv_aclint.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/intc/sifive_plic.c | 19 +- hw/intc/trace-events | 22 + hw/loongarch/Kconfig | 16 + hw/loongarch/loongson3.c | 382 +++ hw/loongarch/meson.build | 4 + hw/meson.build | 1 + hw/pci/shpc.c | 2 +- hw/riscv/boot.c | 5 +- hw/riscv/virt.c | 28 +- hw/rtc/Kconfig | 3 + hw/rtc/ls7a_rtc.c | 528 ++++ hw/rtc/meson.build | 1 + hw/scsi/mfi.h | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/sse-timer.c | 2 +- hw/tpm/tpm_crb.c | 1 + hw/tpm/tpm_tis_common.c | 7 +- hw/vfio/common.c | 10 +- hw/vfio/trace-events | 2 +- include/disas/dis-asm.h | 2 + include/exec/poison.h | 2 + include/hw/display/xlnx_dp.h | 12 +- include/hw/ide.h | 3 - include/hw/intc/loongarch_extioi.h | 62 + include/hw/intc/loongarch_ipi.h | 52 + include/hw/intc/loongarch_pch_msi.h | 20 + include/hw/intc/loongarch_pch_pic.h | 69 + include/hw/loader.h | 55 +- include/hw/loongarch/virt.h | 33 + include/hw/pci-host/ls7a.h | 44 + include/sysemu/arch_init.h | 1 + linux-user/aarch64/signal.c | 4 +- linux-user/aarch64/target_prctl.h | 18 +- meson.build | 1 + python/qemu/machine/machine.py | 2 +- qapi/machine-target.json | 6 +- qapi/machine.json | 2 +- softmmu/qdev-monitor.c | 3 +- target/Kconfig | 1 + target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 5 +- target/arm/cpu.h | 66 +- target/arm/cpu64.c | 120 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 3042 ++------------------ target/arm/hvf/hvf.c | 4 +- target/arm/internals.h | 45 +- target/arm/kvm64.c | 47 +- target/arm/kvm_arm.h | 7 +- target/arm/meson.build | 1 + target/arm/mve_helper.c | 6 +- target/arm/ptw.c | 2540 ++++++++++++++++ target/arm/sve_helper.c | 232 +- target/arm/sve_ldst_internal.h | 221 ++ target/arm/tlb_helper.c | 26 + target/arm/translate-a64.c | 2 +- target/arm/translate-a64.h | 2 +- target/arm/translate-sve.c | 2 +- target/arm/translate.h | 2 +- target/arm/vec_helper.c | 28 +- target/arm/vec_internal.h | 28 +- target/i386/cpu-sysemu.c | 2 +- target/i386/hvf/vmcs.h | 2 +- target/i386/hvf/vmx.h | 2 +- target/loongarch/Kconfig | 2 + target/loongarch/README | 64 + target/loongarch/constant_timer.c | 64 + target/loongarch/cpu-csr.h | 208 ++ target/loongarch/cpu-param.h | 18 + target/loongarch/cpu.c | 704 +++++ target/loongarch/cpu.h | 391 +++ target/loongarch/csr_helper.c | 87 + target/loongarch/disas.c | 757 +++++ target/loongarch/fpu_helper.c | 862 ++++++ target/loongarch/gdbstub.c | 81 + target/loongarch/helper.h | 130 + target/loongarch/insn_trans/trans_arith.c.inc | 304 ++ target/loongarch/insn_trans/trans_atomic.c.inc | 113 + target/loongarch/insn_trans/trans_bit.c.inc | 212 ++ target/loongarch/insn_trans/trans_branch.c.inc | 83 + target/loongarch/insn_trans/trans_extra.c.inc | 101 + target/loongarch/insn_trans/trans_farith.c.inc | 105 + target/loongarch/insn_trans/trans_fcmp.c.inc | 56 + target/loongarch/insn_trans/trans_fcnv.c.inc | 33 + target/loongarch/insn_trans/trans_fmemory.c.inc | 153 + target/loongarch/insn_trans/trans_fmov.c.inc | 157 + target/loongarch/insn_trans/trans_memory.c.inc | 229 ++ target/loongarch/insn_trans/trans_privileged.c.inc | 466 +++ target/loongarch/insn_trans/trans_shift.c.inc | 106 + target/loongarch/insns.decode | 486 ++++ target/loongarch/internals.h | 56 + target/loongarch/iocsr_helper.c | 67 + target/loongarch/machine.c | 102 + target/loongarch/meson.build | 30 + target/loongarch/op_helper.c | 133 + target/loongarch/tlb_helper.c | 763 +++++ target/loongarch/translate.c | 281 ++ target/loongarch/translate.h | 45 + target/meson.build | 1 + target/riscv/cpu.c | 68 +- target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 4 +- target/riscv/debug.c | 2 + target/riscv/insn_trans/trans_rvm.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 106 +- target/riscv/internals.h | 6 +- target/riscv/translate.c | 4 + target/riscv/vector_helper.c | 1588 ++++++---- target/s390x/ioinst.c | 2 +- tests/tcg/loongarch64/Makefile.softmmu-target | 33 + tests/tcg/loongarch64/system/boot.S | 56 + tests/tcg/loongarch64/system/kernel.ld | 30 + tests/tcg/loongarch64/system/regdef.h | 86 + tests/tcg/x86_64/system/boot.S | 2 +- 151 files changed, 14856 insertions(+), 4000 deletions(-) create mode 100644 configs/devices/loongarch64-softmmu/default.mak create mode 100644 configs/targets/loongarch64-softmmu.mak create mode 100644 docs/system/loongarch/loongson3.rst create mode 100644 gdb-xml/loongarch-base64.xml create mode 100644 gdb-xml/loongarch-fpu64.xml create mode 100644 hw/intc/loongarch_extioi.c create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongarch_pch_msi.c create mode 100644 hw/intc/loongarch_pch_pic.c create mode 100644 hw/loongarch/Kconfig create mode 100644 hw/loongarch/loongson3.c create mode 100644 hw/loongarch/meson.build create mode 100644 hw/rtc/ls7a_rtc.c create mode 100644 include/hw/intc/loongarch_extioi.h create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongarch_pch_msi.h create mode 100644 include/hw/intc/loongarch_pch_pic.h create mode 100644 include/hw/loongarch/virt.h create mode 100644 include/hw/pci-host/ls7a.h create mode 100644 target/arm/ptw.c create mode 100644 target/arm/sve_ldst_internal.h create mode 100644 target/loongarch/Kconfig create mode 100644 target/loongarch/README create mode 100644 target/loongarch/constant_timer.c create mode 100644 target/loongarch/cpu-csr.h create mode 100644 target/loongarch/cpu-param.h create mode 100644 target/loongarch/cpu.c create mode 100644 target/loongarch/cpu.h create mode 100644 target/loongarch/csr_helper.c create mode 100644 target/loongarch/disas.c create mode 100644 target/loongarch/fpu_helper.c create mode 100644 target/loongarch/gdbstub.c create mode 100644 target/loongarch/helper.h create mode 100644 target/loongarch/insn_trans/trans_arith.c.inc create mode 100644 target/loongarch/insn_trans/trans_atomic.c.inc create mode 100644 target/loongarch/insn_trans/trans_bit.c.inc create mode 100644 target/loongarch/insn_trans/trans_branch.c.inc create mode 100644 target/loongarch/insn_trans/trans_extra.c.inc create mode 100644 target/loongarch/insn_trans/trans_farith.c.inc create mode 100644 target/loongarch/insn_trans/trans_fcmp.c.inc create mode 100644 target/loongarch/insn_trans/trans_fcnv.c.inc create mode 100644 target/loongarch/insn_trans/trans_fmemory.c.inc create mode 100644 target/loongarch/insn_trans/trans_fmov.c.inc create mode 100644 target/loongarch/insn_trans/trans_memory.c.inc create mode 100644 target/loongarch/insn_trans/trans_privileged.c.inc create mode 100644 target/loongarch/insn_trans/trans_shift.c.inc create mode 100644 target/loongarch/insns.decode create mode 100644 target/loongarch/internals.h create mode 100644 target/loongarch/iocsr_helper.c create mode 100644 target/loongarch/machine.c create mode 100644 target/loongarch/meson.build create mode 100644 target/loongarch/op_helper.c create mode 100644 target/loongarch/tlb_helper.c create mode 100644 target/loongarch/translate.c create mode 100644 target/loongarch/translate.h create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target create mode 100644 tests/tcg/loongarch64/system/boot.S create mode 100644 tests/tcg/loongarch64/system/kernel.ld create mode 100644 tests/tcg/loongarch64/system/regdef.h