This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from 752b9de47d1 [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s new ed761d68673 [RISCV] Only mark fp as reserved if the function has a dedi [...] new 17d355768ce [X86][AVX] Add combineConcatVectors support to improve subv [...]
The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/Target/RISCV/RISCVRegisterInfo.cpp | 4 +- lib/Target/X86/X86ISelLowering.cpp | 39 + test/CodeGen/RISCV/atomic-rmw.ll | 4800 ++++++++++---------- test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 88 +- test/CodeGen/RISCV/callee-saved-gprs.ll | 48 +- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 8 +- .../calling-conv-ilp32-ilp32f-ilp32d-common.ll | 8 +- test/CodeGen/RISCV/calling-conv-ilp32.ll | 8 +- .../RISCV/calling-conv-lp64-lp64f-common.ll | 8 +- test/CodeGen/RISCV/calling-conv-lp64.ll | 8 +- test/CodeGen/RISCV/calls.ll | 16 +- test/CodeGen/RISCV/double-intrinsics.ll | 44 +- test/CodeGen/RISCV/double-mem.ll | 20 +- test/CodeGen/RISCV/float-br-fcmp.ll | 10 +- test/CodeGen/RISCV/float-intrinsics.ll | 32 +- test/CodeGen/RISCV/float-mem.ll | 16 +- test/CodeGen/RISCV/large-stack.ll | 8 +- test/CodeGen/RISCV/remat.ll | 96 +- test/CodeGen/RISCV/rv32i-rv64i-float-double.ll | 38 +- .../RISCV/umulo-128-legalisation-lowering.ll | 162 +- test/CodeGen/RISCV/vararg.ll | 8 +- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 228 +- test/CodeGen/X86/oddshuffles.ll | 42 +- test/CodeGen/X86/pr34657.ll | 10 +- test/CodeGen/X86/shuffle-vs-trunc-256-widen.ll | 4 +- test/CodeGen/X86/subvector-broadcast.ll | 16 +- 26 files changed, 2906 insertions(+), 2863 deletions(-)