This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-arm-build_cross in repository toolchain/ci/qemu.
from c40ae5a3ee Merge remote-tracking branch 'remotes/mst/tags/for_upstream' [...] adds e586edcb41 virtiofs: drop remapped security.capability xattr as needed adds cb90ecf934 Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/p [...] adds 1e8b6f2b49 ui/cocoa: Remove the uses of full screen APIs adds 8eb13bbbac ui/gtk: vte: fix sending multiple characeters adds d9c32b8f7f ui/cocoa: Fix stride resolution of pixman image adds bc6a3565c8 configure: Improve OpenGL dependency detections adds 4313739a57 ui/cocoa: Replace fprintf with error_report adds b5a087b071 ui/console: Add placeholder flag to message surface adds c821a58ee7 ui/console: Pass placeholder surface to displays adds ed8f3fe689 virtio-gpu: Do not distinguish the primary console adds fe352f5c00 Merge remote-tracking branch 'remotes/kraxel/tags/ui-2021030 [...] adds 6f03770dac target/riscv: Declare csr_ops[] with a known size adds a033d8008d hw/misc: sifive_u_otp: Use error_report() when block operati [...] adds 454d1e7cf2 roms/opensbi: Upgrade from v0.8 to v0.9 adds 43a9658889 target-riscv: support QMP dump-guest-memory adds 10509e1095 hw/block: m25p80: Add ISSI SPI flash support adds 62d1076678 hw/block: m25p80: Add various ISSI flash information adds 0694dabe97 hw/ssi: Add SiFive SPI controller support adds 145b299139 hw/riscv: sifive_u: Add QSPI0 controller and connect a flash adds 722f1352b6 hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card adds 8e3c886870 hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value adds 1921e4276d docs/system: Sort targets in alphabetical order adds d6d9896814 docs/system: Add RISC-V documentation adds 01153d2b60 docs/system: riscv: Add documentation for sifive_u machine adds 6b9409ba5f goldfish_rtc: re-arm the alarm after migration adds 4fcad93156 MAINTAINERS: Add a SiFive machine section adds 732612856a hw/riscv: Drop 'struct MemmapEntry' adds 2fa3c7b6ee hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() adds cfeb8a17c8 hw/riscv: virt: Limit RAM size in a 32-bit system adds 19800265d4 hw/riscv: virt: Map high mmio for PCIe adds 9a7beaad3d Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] new d71a243220 error: Fix "Converting to ERRP_GUARD()" doc on "valid at return" new 96291f1343 qga: Utilize QAPI_LIST_APPEND in qmp_guest_network_get_interfaces new a0e61807a3 qapi: Remove QMP events and commands from user-mode builds new 0e92a19b8c qapi: Fix parse errors for removal of null from schema language new bb736b20a3 Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi- [...] new 0110253e69 s390x/cpu_model: disallow unpack for --only-migratable new ea1b90b4fc target/s390x/arch_dump: Fix warning for the name field in th [...] new 24056cbfd5 hw/s390x: fix build for virtio-9p-ccw new 403af209db s390x/pci: restore missing Query PCI Function CLP data new 151fcdfd62 virtio-ccw: commands on revision-less devices new a54b8ac340 css: SCHIB measurement block origin must be aligned new d6cd66311f vfio-ccw: Do not read region ret_code after write new 39d5d1404e target/s390x/kvm: Simplify debug code new 91e92cad67 Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s39 [...]
The 14 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: MAINTAINERS | 9 + configure | 37 +-- docs/interop/vhost-user.json | 3 +- docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++ docs/system/target-riscv.rst | 72 +++++ docs/system/targets.rst | 20 +- docs/tools/virtiofsd.rst | 4 + hw/block/m25p80.c | 57 +++- hw/display/vhost-user-gpu.c | 6 +- hw/display/virtio-gpu-3d.c | 10 +- hw/display/virtio-gpu-base.c | 3 - hw/display/virtio-gpu.c | 9 +- hw/misc/sifive_u_otp.c | 13 +- hw/riscv/Kconfig | 3 + hw/riscv/microchip_pfsoc.c | 9 +- hw/riscv/opentitan.c | 9 +- hw/riscv/sifive_e.c | 9 +- hw/riscv/sifive_u.c | 102 +++++- hw/riscv/spike.c | 9 +- hw/riscv/virt.c | 68 +++- hw/rtc/goldfish_rtc.c | 2 + hw/s390x/meson.build | 4 +- hw/s390x/s390-pci-inst.c | 5 + hw/s390x/virtio-ccw.c | 21 +- hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + hw/ssi/sifive_spi.c | 358 +++++++++++++++++++++ hw/vfio/ccw.c | 12 +- include/hw/riscv/sifive_u.h | 9 +- .../hw/{misc/sifive_test.h => ssi/sifive_spi.h} | 44 +-- include/qapi/error.h | 2 +- include/ui/console.h | 10 +- include/ui/egl-helpers.h | 9 +- include/ui/spice-display.h | 2 +- meson.build | 2 +- pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 62144 -> 78680 bytes pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 558668 -> 727464 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 70792 -> 75096 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 620424 -> 781264 bytes qapi/meson.build | 12 +- qga/commands-posix.c | 75 ++--- roms/opensbi | 2 +- scripts/qapi/parser.py | 8 +- target/riscv/arch_dump.c | 202 ++++++++++++ target/riscv/cpu.c | 2 + target/riscv/cpu.h | 6 +- target/riscv/cpu_bits.h | 1 + target/riscv/meson.build | 1 + target/s390x/arch_dump.c | 4 +- target/s390x/cpu_models.c | 10 + target/s390x/ioinst.c | 6 + target/s390x/kvm.c | 3 +- tests/qapi-schema/leading-comma-list.err | 2 +- tests/qapi-schema/trailing-comma-list.err | 2 +- tools/virtiofsd/passthrough_ll.c | 77 ++++- ui/cocoa.m | 55 ++-- ui/console.c | 28 +- ui/egl-helpers.c | 8 +- ui/gtk-egl.c | 6 +- ui/gtk-gl-area.c | 2 +- ui/gtk.c | 29 +- ui/meson.build | 8 +- ui/sdl2-2d.c | 7 +- ui/sdl2-gl.c | 4 +- ui/spice-display.c | 6 +- ui/vnc.c | 10 - 66 files changed, 1565 insertions(+), 284 deletions(-) create mode 100644 docs/system/riscv/sifive_u.rst create mode 100644 docs/system/target-riscv.rst create mode 100644 hw/ssi/sifive_spi.c copy include/hw/{misc/sifive_test.h => ssi/sifive_spi.h} (53%) create mode 100644 target/riscv/arch_dump.c