[Tcwg-commits] [llvm] branch master updated (1437cc9a527 -> e4959200b5c)

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from 1437cc9a527 [RISCV] Prepare for the use of variable-sized register classes new e4959200b5c [X86] Add scalar (abs (abs x)) -> (abs x) combine test.

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Summary of changes: test/CodeGen/X86/combine-abs.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)