This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from dd6e1cbac86 RISC-V: Fix VL operand bug in VSETVL PASS[PR110264] new d0cf0c6c844 RISC-V: Bugfix for RVV integer reduction in ZVE32/64.
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 13 +- gcc/config/riscv/vector-iterators.md | 61 ++++++ gcc/config/riscv/vector.md | 208 +++++++++++++++------ .../gcc.target/riscv/rvv/base/pr110265-1.c | 13 ++ .../gcc.target/riscv/rvv/base/pr110265-1.h | 65 +++++++ .../gcc.target/riscv/rvv/base/pr110265-2.c | 14 ++ .../gcc.target/riscv/rvv/base/pr110265-2.h | 57 ++++++ .../gcc.target/riscv/rvv/base/pr110265-3.c | 14 ++ 8 files changed, 385 insertions(+), 60 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c