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from 332260473f3 AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spills new d965de356db [ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASM new 5d5f1f607e4 [AArch64] check for INLINEASM_BR along w/ INLINEASM
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Summary of changes: lib/Target/AArch64/AArch64InstrInfo.cpp | 7 +++++-- lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 ++++++++++---------- lib/Target/ARM/Thumb2InstrInfo.cpp | 2 +- 3 files changed, 16 insertions(+), 13 deletions(-)