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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gcc.
from 2dc835cd0b5 RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern adds b343a29dbcb rs6000: Fix ICE of vect cost related to V1TI [PR102767] adds eed248bb8cc tree-optimization/102949 - fix base object alignment adds a84b9d5373c middle-end/57245 - honor -frounding-math in real truncation adds 7f6c2258522 Make back_threader_registry inherit from back_jt_path_registry. adds 113dab2b9d5 Improve backward threading with switches.
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Summary of changes: gcc/config/rs6000/rs6000.c | 64 +++++++++++----------- gcc/fold-const.c | 6 ++ gcc/simplify-rtx.c | 5 ++ .../gcc.dg/torture/fp-double-convert-float-1.c | 41 ++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/vrp106.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/vrp113.c | 2 - .../gcc.target/powerpc/ppc-fortran/pr102767.f90 | 21 +++++++ gcc/tree-ssa-threadbackward.c | 29 +++------- gcc/tree-vect-stmts.c | 8 ++- 9 files changed, 123 insertions(+), 57 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/fp-double-convert-float-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr102767.f90